From: Thomas Richard Date: Mon, 5 May 2025 08:28:59 +0000 (+0200) Subject: kernel/stm32: Restore kernel files for v6.6 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=234eadd07e48d6d535447d93dab50c9b4abc75a1;p=thirdparty%2Fopenwrt.git kernel/stm32: Restore kernel files for v6.6 This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. For the original discussion see: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html Signed-off-by: Thomas Richard Link: https://github.com/openwrt/openwrt/pull/18740 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/stm32/patches-6.6/001-net-stmmac-dwmac-stm32-use-devm_stmmac_probe_config_.patch b/target/linux/stm32/patches-6.6/001-net-stmmac-dwmac-stm32-use-devm_stmmac_probe_config_.patch new file mode 100644 index 00000000000..cf192fdef48 --- /dev/null +++ b/target/linux/stm32/patches-6.6/001-net-stmmac-dwmac-stm32-use-devm_stmmac_probe_config_.patch @@ -0,0 +1,69 @@ +From 1ddced59ac1f7c739f21e930d87b126a30c561bb Mon Sep 17 00:00:00 2001 +From: Jisheng Zhang +Date: Sat, 16 Sep 2023 15:58:23 +0800 +Subject: [PATCH 1/8] net: stmmac: dwmac-stm32: use + devm_stmmac_probe_config_dt() + +Simplify the driver's probe() function by using the devres +variant of stmmac_probe_config_dt(). + +Signed-off-by: Jisheng Zhang +Signed-off-by: David S. Miller +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 17 ++++++----------- + 1 file changed, 6 insertions(+), 11 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -372,21 +372,18 @@ static int stm32_dwmac_probe(struct plat + if (ret) + return ret; + +- plat_dat = stmmac_probe_config_dt(pdev, stmmac_res.mac); ++ plat_dat = devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL); +- if (!dwmac) { +- ret = -ENOMEM; +- goto err_remove_config_dt; +- } ++ if (!dwmac) ++ return -ENOMEM; + + data = of_device_get_match_data(&pdev->dev); + if (!data) { + dev_err(&pdev->dev, "no of match data provided\n"); +- ret = -EINVAL; +- goto err_remove_config_dt; ++ return -EINVAL; + } + + dwmac->ops = data; +@@ -395,14 +392,14 @@ static int stm32_dwmac_probe(struct plat + ret = stm32_dwmac_parse_data(dwmac, &pdev->dev); + if (ret) { + dev_err(&pdev->dev, "Unable to parse OF data\n"); +- goto err_remove_config_dt; ++ return ret; + } + + plat_dat->bsp_priv = dwmac; + + ret = stm32_dwmac_init(plat_dat); + if (ret) +- goto err_remove_config_dt; ++ return ret; + + ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) +@@ -412,8 +409,6 @@ static int stm32_dwmac_probe(struct plat + + err_clk_disable: + stm32_dwmac_clk_disable(dwmac); +-err_remove_config_dt: +- stmmac_remove_config_dt(pdev, plat_dat); + + return ret; + } diff --git a/target/linux/stm32/patches-6.6/002-net-stmmac-dwmac-stm32-refactor-clock-config.patch b/target/linux/stm32/patches-6.6/002-net-stmmac-dwmac-stm32-refactor-clock-config.patch new file mode 100644 index 00000000000..dd791dab6a0 --- /dev/null +++ b/target/linux/stm32/patches-6.6/002-net-stmmac-dwmac-stm32-refactor-clock-config.patch @@ -0,0 +1,241 @@ +From 73c350e3fb32e9598b66f61081c7e06a7fba49f8 Mon Sep 17 00:00:00 2001 +From: Ben Wolsieffer +Date: Mon, 9 Oct 2023 10:59:04 -0400 +Subject: [PATCH 2/8] net: stmmac: dwmac-stm32: refactor clock config + +Currently, clock configuration is spread throughout the driver and +partially duplicated for the STM32MP1 and STM32 MCU variants. This makes +it difficult to keep track of which clocks need to be enabled or disabled +in various scenarios. + +This patch adds symmetric stm32_dwmac_clk_enable/disable() functions +that handle all clock configuration, including quirks required while +suspending or resuming. syscfg_clk and clk_eth_ck are not present on +STM32 MCUs, but it is fine to try to configure them anyway since NULL +clocks are ignored. + +Signed-off-by: Ben Wolsieffer +Signed-off-by: David S. Miller +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 113 +++++++----------- + 1 file changed, 45 insertions(+), 68 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -98,7 +98,6 @@ struct stm32_dwmac { + + struct stm32_ops { + int (*set_mode)(struct plat_stmmacenet_data *plat_dat); +- int (*clk_prepare)(struct stm32_dwmac *dwmac, bool prepare); + int (*suspend)(struct stm32_dwmac *dwmac); + void (*resume)(struct stm32_dwmac *dwmac); + int (*parse_data)(struct stm32_dwmac *dwmac, +@@ -107,62 +106,55 @@ struct stm32_ops { + bool clk_rx_enable_in_suspend; + }; + +-static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat) ++static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume) + { +- struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + int ret; + +- if (dwmac->ops->set_mode) { +- ret = dwmac->ops->set_mode(plat_dat); +- if (ret) +- return ret; +- } +- + ret = clk_prepare_enable(dwmac->clk_tx); + if (ret) +- return ret; ++ goto err_clk_tx; + +- if (!dwmac->ops->clk_rx_enable_in_suspend || +- !dwmac->dev->power.is_suspended) { ++ if (!dwmac->ops->clk_rx_enable_in_suspend || !resume) { + ret = clk_prepare_enable(dwmac->clk_rx); +- if (ret) { +- clk_disable_unprepare(dwmac->clk_tx); +- return ret; +- } ++ if (ret) ++ goto err_clk_rx; + } + +- if (dwmac->ops->clk_prepare) { +- ret = dwmac->ops->clk_prepare(dwmac, true); +- if (ret) { +- clk_disable_unprepare(dwmac->clk_rx); +- clk_disable_unprepare(dwmac->clk_tx); +- } ++ ret = clk_prepare_enable(dwmac->syscfg_clk); ++ if (ret) ++ goto err_syscfg_clk; ++ ++ if (dwmac->enable_eth_ck) { ++ ret = clk_prepare_enable(dwmac->clk_eth_ck); ++ if (ret) ++ goto err_clk_eth_ck; + } + + return ret; ++ ++err_clk_eth_ck: ++ clk_disable_unprepare(dwmac->syscfg_clk); ++err_syscfg_clk: ++ if (!dwmac->ops->clk_rx_enable_in_suspend || !resume) ++ clk_disable_unprepare(dwmac->clk_rx); ++err_clk_rx: ++ clk_disable_unprepare(dwmac->clk_tx); ++err_clk_tx: ++ return ret; + } + +-static int stm32mp1_clk_prepare(struct stm32_dwmac *dwmac, bool prepare) ++static int stm32_dwmac_init(struct plat_stmmacenet_data *plat_dat, bool resume) + { +- int ret = 0; ++ struct stm32_dwmac *dwmac = plat_dat->bsp_priv; ++ int ret; + +- if (prepare) { +- ret = clk_prepare_enable(dwmac->syscfg_clk); ++ if (dwmac->ops->set_mode) { ++ ret = dwmac->ops->set_mode(plat_dat); + if (ret) + return ret; +- if (dwmac->enable_eth_ck) { +- ret = clk_prepare_enable(dwmac->clk_eth_ck); +- if (ret) { +- clk_disable_unprepare(dwmac->syscfg_clk); +- return ret; +- } +- } +- } else { +- clk_disable_unprepare(dwmac->syscfg_clk); +- if (dwmac->enable_eth_ck) +- clk_disable_unprepare(dwmac->clk_eth_ck); + } +- return ret; ++ ++ return stm32_dwmac_clk_enable(dwmac, resume); + } + + static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) +@@ -252,13 +244,15 @@ static int stm32mcu_set_mode(struct plat + dwmac->ops->syscfg_eth_mask, val << 23); + } + +-static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac) ++static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend) + { + clk_disable_unprepare(dwmac->clk_tx); +- clk_disable_unprepare(dwmac->clk_rx); ++ if (!dwmac->ops->clk_rx_enable_in_suspend || !suspend) ++ clk_disable_unprepare(dwmac->clk_rx); + +- if (dwmac->ops->clk_prepare) +- dwmac->ops->clk_prepare(dwmac, false); ++ clk_disable_unprepare(dwmac->syscfg_clk); ++ if (dwmac->enable_eth_ck) ++ clk_disable_unprepare(dwmac->clk_eth_ck); + } + + static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, +@@ -397,7 +391,7 @@ static int stm32_dwmac_probe(struct plat + + plat_dat->bsp_priv = dwmac; + +- ret = stm32_dwmac_init(plat_dat); ++ ret = stm32_dwmac_init(plat_dat, false); + if (ret) + return ret; + +@@ -408,7 +402,7 @@ static int stm32_dwmac_probe(struct plat + return 0; + + err_clk_disable: +- stm32_dwmac_clk_disable(dwmac); ++ stm32_dwmac_clk_disable(dwmac, false); + + return ret; + } +@@ -421,7 +415,7 @@ static void stm32_dwmac_remove(struct pl + + stmmac_dvr_remove(&pdev->dev); + +- stm32_dwmac_clk_disable(priv->plat->bsp_priv); ++ stm32_dwmac_clk_disable(dwmac, false); + + if (dwmac->irq_pwr_wakeup >= 0) { + dev_pm_clear_wake_irq(&pdev->dev); +@@ -431,18 +425,7 @@ static void stm32_dwmac_remove(struct pl + + static int stm32mp1_suspend(struct stm32_dwmac *dwmac) + { +- int ret = 0; +- +- ret = clk_prepare_enable(dwmac->clk_ethstp); +- if (ret) +- return ret; +- +- clk_disable_unprepare(dwmac->clk_tx); +- clk_disable_unprepare(dwmac->syscfg_clk); +- if (dwmac->enable_eth_ck) +- clk_disable_unprepare(dwmac->clk_eth_ck); +- +- return ret; ++ return clk_prepare_enable(dwmac->clk_ethstp); + } + + static void stm32mp1_resume(struct stm32_dwmac *dwmac) +@@ -450,14 +433,6 @@ static void stm32mp1_resume(struct stm32 + clk_disable_unprepare(dwmac->clk_ethstp); + } + +-static int stm32mcu_suspend(struct stm32_dwmac *dwmac) +-{ +- clk_disable_unprepare(dwmac->clk_tx); +- clk_disable_unprepare(dwmac->clk_rx); +- +- return 0; +-} +- + #ifdef CONFIG_PM_SLEEP + static int stm32_dwmac_suspend(struct device *dev) + { +@@ -468,6 +443,10 @@ static int stm32_dwmac_suspend(struct de + int ret; + + ret = stmmac_suspend(dev); ++ if (ret) ++ return ret; ++ ++ stm32_dwmac_clk_disable(dwmac, true); + + if (dwmac->ops->suspend) + ret = dwmac->ops->suspend(dwmac); +@@ -485,7 +464,7 @@ static int stm32_dwmac_resume(struct dev + if (dwmac->ops->resume) + dwmac->ops->resume(dwmac); + +- ret = stm32_dwmac_init(priv->plat); ++ ret = stm32_dwmac_init(priv->plat, true); + if (ret) + return ret; + +@@ -500,13 +479,11 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ + + static struct stm32_ops stm32mcu_dwmac_data = { + .set_mode = stm32mcu_set_mode, +- .suspend = stm32mcu_suspend, + .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK + }; + + static struct stm32_ops stm32mp1_dwmac_data = { + .set_mode = stm32mp1_set_mode, +- .clk_prepare = stm32mp1_clk_prepare, + .suspend = stm32mp1_suspend, + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, diff --git a/target/linux/stm32/patches-6.6/003-net-stmmac-dwmac-stm32-Separate-out-external-clock-r.patch b/target/linux/stm32/patches-6.6/003-net-stmmac-dwmac-stm32-Separate-out-external-clock-r.patch new file mode 100644 index 00000000000..bcdd23b4ebf --- /dev/null +++ b/target/linux/stm32/patches-6.6/003-net-stmmac-dwmac-stm32-Separate-out-external-clock-r.patch @@ -0,0 +1,125 @@ +From 23c08dc4ff28b5ca1aa5ee745a5e9688561e8f6a Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Tue, 11 Jun 2024 10:36:00 +0200 +Subject: [PATCH 3/8] net: stmmac: dwmac-stm32: Separate out external clock + rate validation + +Pull the external clock frequency validation into a separate function, +to avoid conflating it with external clock DT property decoding and +clock mux register configuration. This should make the code easier to +read and understand. + +This does change the code behavior slightly. The clock mux PMCR register +setting now depends solely on the DT properties which configure the clock +mux between external clock and internal RCC generated clock. The mux PMCR +register settings no longer depend on the supplied clock frequency, that +supplied clock frequency is now only validated, and if the clock frequency +is invalid for a mode, it is rejected. + +Previously, the code would switch the PMCR register clock mux to internal +RCC generated clock if external clock couldn't provide suitable frequency, +without checking whether the RCC generated clock frequency is correct. Such +behavior is risky at best, user should have configured their clock correctly +in the first place, so this behavior is removed here. + +Signed-off-by: Marek Vasut +Signed-off-by: Christophe Roullier +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 +++++++++++++++---- + 1 file changed, 41 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -157,25 +157,54 @@ static int stm32_dwmac_init(struct plat_ + return stm32_dwmac_clk_enable(dwmac, resume); + } + ++static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) ++{ ++ struct stm32_dwmac *dwmac = plat_dat->bsp_priv; ++ const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck); ++ ++ switch (plat_dat->mac_interface) { ++ case PHY_INTERFACE_MODE_MII: ++ case PHY_INTERFACE_MODE_GMII: ++ if (clk_rate == ETH_CK_F_25M) ++ return 0; ++ break; ++ case PHY_INTERFACE_MODE_RMII: ++ if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) ++ return 0; ++ break; ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ if (clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) ++ return 0; ++ break; ++ default: ++ break; ++ } ++ ++ dev_err(dwmac->dev, "Mode %s does not match eth-ck frequency %d Hz", ++ phy_modes(plat_dat->mac_interface), clk_rate); ++ return -EINVAL; ++} ++ + static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) + { + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; +- u32 reg = dwmac->mode_reg, clk_rate; +- int val; ++ u32 reg = dwmac->mode_reg; ++ int val, ret; + +- clk_rate = clk_get_rate(dwmac->clk_eth_ck); + dwmac->enable_eth_ck = false; + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: +- if (clk_rate == ETH_CK_F_25M && dwmac->ext_phyclk) ++ if (dwmac->ext_phyclk) + dwmac->enable_eth_ck = true; + val = SYSCFG_PMCR_ETH_SEL_MII; + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); + break; + case PHY_INTERFACE_MODE_GMII: + val = SYSCFG_PMCR_ETH_SEL_GMII; +- if (clk_rate == ETH_CK_F_25M && +- (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { ++ if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { + dwmac->enable_eth_ck = true; + val |= SYSCFG_PMCR_ETH_CLK_SEL; + } +@@ -183,8 +212,7 @@ static int stm32mp1_set_mode(struct plat + break; + case PHY_INTERFACE_MODE_RMII: + val = SYSCFG_PMCR_ETH_SEL_RMII; +- if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_50M) && +- (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk)) { ++ if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) { + dwmac->enable_eth_ck = true; + val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; + } +@@ -195,8 +223,7 @@ static int stm32mp1_set_mode(struct plat + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + val = SYSCFG_PMCR_ETH_SEL_RGMII; +- if ((clk_rate == ETH_CK_F_25M || clk_rate == ETH_CK_F_125M) && +- (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk)) { ++ if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { + dwmac->enable_eth_ck = true; + val |= SYSCFG_PMCR_ETH_CLK_SEL; + } +@@ -209,6 +236,10 @@ static int stm32mp1_set_mode(struct plat + return -EINVAL; + } + ++ ret = stm32mp1_validate_ethck_rate(plat_dat); ++ if (ret) ++ return ret; ++ + /* Need to update PMCCLRR (clear register) */ + regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, + dwmac->ops->syscfg_eth_mask); diff --git a/target/linux/stm32/patches-6.6/004-net-stmmac-dwmac-stm32-Separate-out-external-clock-s.patch b/target/linux/stm32/patches-6.6/004-net-stmmac-dwmac-stm32-Separate-out-external-clock-s.patch new file mode 100644 index 00000000000..2e8f76158d4 --- /dev/null +++ b/target/linux/stm32/patches-6.6/004-net-stmmac-dwmac-stm32-Separate-out-external-clock-s.patch @@ -0,0 +1,132 @@ +From d23ba64e733580db2809e6f6dbf6f093fbd1b91b Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Tue, 11 Jun 2024 10:36:01 +0200 +Subject: [PATCH 4/8] net: stmmac: dwmac-stm32: Separate out external clock + selector + +Pull the external clock selector into a separate function, to avoid +conflating it with external clock rate validation and clock mux +register configuration. This should make the code easier to read and +understand. + +The dwmac->enable_eth_ck variable in the end indicates whether the MAC +clock are supplied by external oscillator (true) or internal RCC clock +IP (false). The dwmac->enable_eth_ck value is set based on multiple DT +properties, some of them deprecated, some of them specific to bus mode. + +The following DT properties and variables are taken into account. In +each case, if the property is present or true, MAC clock is supplied +by external oscillator. +- "st,ext-phyclk", assigned to variable dwmac->ext_phyclk + - Used in any mode (MII/RMII/GMII/RGMII) + - The only non-deprecated DT property of the three +- "st,eth-clk-sel", assigned to variable dwmac->eth_clk_sel_reg + - Valid only in GMII/RGMII mode + - Deprecated property, backward compatibility only +- "st,eth-ref-clk-sel", assigned to variable dwmac->eth_ref_clk_sel_reg + - Valid only in RMII mode + - Deprecated property, backward compatibility only + +The stm32mp1_select_ethck_external() function handles the aforementioned +DT properties and sets dwmac->enable_eth_ck accordingly. + +The stm32mp1_set_mode() is adjusted to call stm32mp1_select_ethck_external() +first and then only use dwmac->enable_eth_ck to determine hardware clock mux +settings. + +No functional change intended. + +Signed-off-by: Marek Vasut +Signed-off-by: Christophe Roullier +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 50 ++++++++++++++----- + 1 file changed, 38 insertions(+), 12 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -157,6 +157,37 @@ static int stm32_dwmac_init(struct plat_ + return stm32_dwmac_clk_enable(dwmac, resume); + } + ++static int stm32mp1_select_ethck_external(struct plat_stmmacenet_data *plat_dat) ++{ ++ struct stm32_dwmac *dwmac = plat_dat->bsp_priv; ++ ++ switch (plat_dat->mac_interface) { ++ case PHY_INTERFACE_MODE_MII: ++ dwmac->enable_eth_ck = dwmac->ext_phyclk; ++ return 0; ++ case PHY_INTERFACE_MODE_GMII: ++ dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || ++ dwmac->ext_phyclk; ++ return 0; ++ case PHY_INTERFACE_MODE_RMII: ++ dwmac->enable_eth_ck = dwmac->eth_ref_clk_sel_reg || ++ dwmac->ext_phyclk; ++ return 0; ++ case PHY_INTERFACE_MODE_RGMII: ++ case PHY_INTERFACE_MODE_RGMII_ID: ++ case PHY_INTERFACE_MODE_RGMII_RXID: ++ case PHY_INTERFACE_MODE_RGMII_TXID: ++ dwmac->enable_eth_ck = dwmac->eth_clk_sel_reg || ++ dwmac->ext_phyclk; ++ return 0; ++ default: ++ dwmac->enable_eth_ck = false; ++ dev_err(dwmac->dev, "Mode %s not supported", ++ phy_modes(plat_dat->mac_interface)); ++ return -EINVAL; ++ } ++} ++ + static int stm32mp1_validate_ethck_rate(struct plat_stmmacenet_data *plat_dat) + { + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; +@@ -194,28 +225,25 @@ static int stm32mp1_set_mode(struct plat + u32 reg = dwmac->mode_reg; + int val, ret; + +- dwmac->enable_eth_ck = false; ++ ret = stm32mp1_select_ethck_external(plat_dat); ++ if (ret) ++ return ret; ++ + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: +- if (dwmac->ext_phyclk) +- dwmac->enable_eth_ck = true; + val = SYSCFG_PMCR_ETH_SEL_MII; + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); + break; + case PHY_INTERFACE_MODE_GMII: + val = SYSCFG_PMCR_ETH_SEL_GMII; +- if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { +- dwmac->enable_eth_ck = true; ++ if (dwmac->enable_eth_ck) + val |= SYSCFG_PMCR_ETH_CLK_SEL; +- } + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); + break; + case PHY_INTERFACE_MODE_RMII: + val = SYSCFG_PMCR_ETH_SEL_RMII; +- if (dwmac->eth_ref_clk_sel_reg || dwmac->ext_phyclk) { +- dwmac->enable_eth_ck = true; ++ if (dwmac->enable_eth_ck) + val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; +- } + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); + break; + case PHY_INTERFACE_MODE_RGMII: +@@ -223,10 +251,8 @@ static int stm32mp1_set_mode(struct plat + case PHY_INTERFACE_MODE_RGMII_RXID: + case PHY_INTERFACE_MODE_RGMII_TXID: + val = SYSCFG_PMCR_ETH_SEL_RGMII; +- if (dwmac->eth_clk_sel_reg || dwmac->ext_phyclk) { +- dwmac->enable_eth_ck = true; ++ if (dwmac->enable_eth_ck) + val |= SYSCFG_PMCR_ETH_CLK_SEL; +- } + pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); + break; + default: diff --git a/target/linux/stm32/patches-6.6/005-net-stmmac-dwmac-stm32-Extract-PMCR-configuration.patch b/target/linux/stm32/patches-6.6/005-net-stmmac-dwmac-stm32-Extract-PMCR-configuration.patch new file mode 100644 index 00000000000..b28884df586 --- /dev/null +++ b/target/linux/stm32/patches-6.6/005-net-stmmac-dwmac-stm32-Extract-PMCR-configuration.patch @@ -0,0 +1,71 @@ +From bb7ab910631ee0ade0758a3c4aa8dadc3b6934b6 Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Tue, 11 Jun 2024 10:36:02 +0200 +Subject: [PATCH 5/8] net: stmmac: dwmac-stm32: Extract PMCR configuration + +Pull the PMCR clock mux configuration into a separate function. This is +the final change of three, which moves external clock rate validation, +external clock selector decoding, and clock mux configuration into +separate functions. This should make the code easier to understand. +No functional change intended. + +Signed-off-by: Marek Vasut +Signed-off-by: Christophe Roullier +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 27 ++++++++++++------- + 1 file changed, 17 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -219,15 +219,11 @@ static int stm32mp1_validate_ethck_rate( + return -EINVAL; + } + +-static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) ++static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) + { + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + u32 reg = dwmac->mode_reg; +- int val, ret; +- +- ret = stm32mp1_select_ethck_external(plat_dat); +- if (ret) +- return ret; ++ int val; + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: +@@ -262,10 +258,6 @@ static int stm32mp1_set_mode(struct plat + return -EINVAL; + } + +- ret = stm32mp1_validate_ethck_rate(plat_dat); +- if (ret) +- return ret; +- + /* Need to update PMCCLRR (clear register) */ + regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, + dwmac->ops->syscfg_eth_mask); +@@ -275,6 +267,21 @@ static int stm32mp1_set_mode(struct plat + dwmac->ops->syscfg_eth_mask, val); + } + ++static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) ++{ ++ int ret; ++ ++ ret = stm32mp1_select_ethck_external(plat_dat); ++ if (ret) ++ return ret; ++ ++ ret = stm32mp1_validate_ethck_rate(plat_dat); ++ if (ret) ++ return ret; ++ ++ return stm32mp1_configure_pmcr(plat_dat); ++} ++ + static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) + { + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; diff --git a/target/linux/stm32/patches-6.6/006-net-stmmac-dwmac-stm32-Clean-up-the-debug-prints.patch b/target/linux/stm32/patches-6.6/006-net-stmmac-dwmac-stm32-Clean-up-the-debug-prints.patch new file mode 100644 index 00000000000..45050ae0775 --- /dev/null +++ b/target/linux/stm32/patches-6.6/006-net-stmmac-dwmac-stm32-Clean-up-the-debug-prints.patch @@ -0,0 +1,83 @@ +From 0476213f50452446fedd1a918b7bc72eb39a4c46 Mon Sep 17 00:00:00 2001 +From: Marek Vasut +Date: Tue, 11 Jun 2024 10:36:03 +0200 +Subject: [PATCH 6/8] net: stmmac: dwmac-stm32: Clean up the debug prints + +Use dev_err()/dev_dbg() and phy_modes() to print PHY mode instead of +pr_debug() and hand-written PHY mode decoding. This way, each debug +print has associated device with it and duplicated mode decoding is +removed. + +Signed-off-by: Marek Vasut +Signed-off-by: Christophe Roullier +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 18 ++++++++---------- + 1 file changed, 8 insertions(+), 10 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -228,19 +228,16 @@ static int stm32mp1_configure_pmcr(struc + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + val = SYSCFG_PMCR_ETH_SEL_MII; +- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); + break; + case PHY_INTERFACE_MODE_GMII: + val = SYSCFG_PMCR_ETH_SEL_GMII; + if (dwmac->enable_eth_ck) + val |= SYSCFG_PMCR_ETH_CLK_SEL; +- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_GMII\n"); + break; + case PHY_INTERFACE_MODE_RMII: + val = SYSCFG_PMCR_ETH_SEL_RMII; + if (dwmac->enable_eth_ck) + val |= SYSCFG_PMCR_ETH_REF_CLK_SEL; +- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); + break; + case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RGMII_ID: +@@ -249,15 +246,16 @@ static int stm32mp1_configure_pmcr(struc + val = SYSCFG_PMCR_ETH_SEL_RGMII; + if (dwmac->enable_eth_ck) + val |= SYSCFG_PMCR_ETH_CLK_SEL; +- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RGMII\n"); + break; + default: +- pr_debug("SYSCFG init : Do not manage %d interface\n", +- plat_dat->mac_interface); ++ dev_err(dwmac->dev, "Mode %s not supported", ++ phy_modes(plat_dat->mac_interface)); + /* Do not manage others interfaces */ + return -EINVAL; + } + ++ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); ++ + /* Need to update PMCCLRR (clear register) */ + regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, + dwmac->ops->syscfg_eth_mask); +@@ -291,19 +289,19 @@ static int stm32mcu_set_mode(struct plat + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + val = SYSCFG_MCU_ETH_SEL_MII; +- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_MII\n"); + break; + case PHY_INTERFACE_MODE_RMII: + val = SYSCFG_MCU_ETH_SEL_RMII; +- pr_debug("SYSCFG init : PHY_INTERFACE_MODE_RMII\n"); + break; + default: +- pr_debug("SYSCFG init : Do not manage %d interface\n", +- plat_dat->mac_interface); ++ dev_err(dwmac->dev, "Mode %s not supported", ++ phy_modes(plat_dat->mac_interface)); + /* Do not manage others interfaces */ + return -EINVAL; + } + ++ dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); ++ + return regmap_update_bits(dwmac->regmap, reg, + dwmac->ops->syscfg_eth_mask, val << 23); + } diff --git a/target/linux/stm32/patches-6.6/007-net-stmmac-dwmac-stm32-Mask-support-for-PMCR-configu.patch b/target/linux/stm32/patches-6.6/007-net-stmmac-dwmac-stm32-Mask-support-for-PMCR-configu.patch new file mode 100644 index 00000000000..336378abb34 --- /dev/null +++ b/target/linux/stm32/patches-6.6/007-net-stmmac-dwmac-stm32-Mask-support-for-PMCR-configu.patch @@ -0,0 +1,101 @@ +From 796669a85c5c4fa80cb8790e9adcccbbd99750e8 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Tue, 11 Jun 2024 10:36:05 +0200 +Subject: [PATCH 7/8] net: stmmac: dwmac-stm32: Mask support for PMCR + configuration + +Add possibility to have second argument in syscon property to manage +mask. This mask will be used to address right BITFIELDS of PMCR register. + +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 28 +++++++++++++------ + 1 file changed, 19 insertions(+), 9 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -90,6 +90,7 @@ struct stm32_dwmac { + int eth_ref_clk_sel_reg; + int irq_pwr_wakeup; + u32 mode_reg; /* MAC glue-logic mode register */ ++ u32 mode_mask; + struct regmap *regmap; + u32 speed; + const struct stm32_ops *ops; +@@ -102,8 +103,8 @@ struct stm32_ops { + void (*resume)(struct stm32_dwmac *dwmac); + int (*parse_data)(struct stm32_dwmac *dwmac, + struct device *dev); +- u32 syscfg_eth_mask; + bool clk_rx_enable_in_suspend; ++ u32 syscfg_clr_off; + }; + + static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume) +@@ -256,13 +257,16 @@ static int stm32mp1_configure_pmcr(struc + + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + ++ /* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */ ++ val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK); ++ + /* Need to update PMCCLRR (clear register) */ +- regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET, +- dwmac->ops->syscfg_eth_mask); ++ regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off, ++ dwmac->mode_mask); + + /* Update PMCSETR (set register) */ + return regmap_update_bits(dwmac->regmap, reg, +- dwmac->ops->syscfg_eth_mask, val); ++ dwmac->mode_mask, val); + } + + static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat) +@@ -303,7 +307,7 @@ static int stm32mcu_set_mode(struct plat + dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface)); + + return regmap_update_bits(dwmac->regmap, reg, +- dwmac->ops->syscfg_eth_mask, val << 23); ++ SYSCFG_MCU_ETH_MASK, val << 23); + } + + static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend) +@@ -348,8 +352,15 @@ static int stm32_dwmac_parse_data(struct + return PTR_ERR(dwmac->regmap); + + err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg); +- if (err) ++ if (err) { + dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err); ++ return err; ++ } ++ ++ dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; ++ err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); ++ if (err) ++ dev_dbg(dev, "Warning sysconfig register mask not set\n"); + + return err; + } +@@ -540,8 +551,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ + stm32_dwmac_suspend, stm32_dwmac_resume); + + static struct stm32_ops stm32mcu_dwmac_data = { +- .set_mode = stm32mcu_set_mode, +- .syscfg_eth_mask = SYSCFG_MCU_ETH_MASK ++ .set_mode = stm32mcu_set_mode + }; + + static struct stm32_ops stm32mp1_dwmac_data = { +@@ -549,7 +559,7 @@ static struct stm32_ops stm32mp1_dwmac_d + .suspend = stm32mp1_suspend, + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, +- .syscfg_eth_mask = SYSCFG_MP1_ETH_MASK, ++ .syscfg_clr_off = 0x44, + .clk_rx_enable_in_suspend = true + }; + diff --git a/target/linux/stm32/patches-6.6/008-net-stmmac-dwmac-stm32-add-management-of-stm32mp13-f.patch b/target/linux/stm32/patches-6.6/008-net-stmmac-dwmac-stm32-add-management-of-stm32mp13-f.patch new file mode 100644 index 00000000000..c2526019e2c --- /dev/null +++ b/target/linux/stm32/patches-6.6/008-net-stmmac-dwmac-stm32-add-management-of-stm32mp13-f.patch @@ -0,0 +1,94 @@ +From 8d28aaf5d5dbfd1f452286fa6ac571df0bcf00ad Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Tue, 11 Jun 2024 10:36:06 +0200 +Subject: [PATCH 8/8] net: stmmac: dwmac-stm32: add management of stm32mp13 for + stm32 + +Add Ethernet support for STM32MP13. +STM32MP13 is STM32 SOC with 2 GMACs instances. +GMAC IP version is SNPS 4.20. +GMAC IP configure with 1 RX and 1 TX queue. +DMA HW capability register supported +RX Checksum Offload Engine supported +TX Checksum insertion supported +Wake-Up On Lan supported +TSO supported + +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Signed-off-by: Paolo Abeni +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 32 ++++++++++++++++--- + 1 file changed, 28 insertions(+), 4 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -104,6 +104,7 @@ struct stm32_ops { + int (*parse_data)(struct stm32_dwmac *dwmac, + struct device *dev); + bool clk_rx_enable_in_suspend; ++ bool is_mp13; + u32 syscfg_clr_off; + }; + +@@ -224,11 +225,18 @@ static int stm32mp1_configure_pmcr(struc + { + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + u32 reg = dwmac->mode_reg; +- int val; ++ int val = 0; + + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: +- val = SYSCFG_PMCR_ETH_SEL_MII; ++ /* ++ * STM32MP15xx supports both MII and GMII, STM32MP13xx MII only. ++ * SYSCFG_PMCSETR ETH_SELMII is present only on STM32MP15xx and ++ * acts as a selector between 0:GMII and 1:MII. As STM32MP13xx ++ * supports only MII, ETH_SELMII is not present. ++ */ ++ if (!dwmac->ops->is_mp13) /* Select MII mode on STM32MP15xx */ ++ val |= SYSCFG_PMCR_ETH_SEL_MII; + break; + case PHY_INTERFACE_MODE_GMII: + val = SYSCFG_PMCR_ETH_SEL_GMII; +@@ -359,8 +367,12 @@ static int stm32_dwmac_parse_data(struct + + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; + err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); +- if (err) +- dev_dbg(dev, "Warning sysconfig register mask not set\n"); ++ if (err) { ++ if (dwmac->ops->is_mp13) ++ dev_err(dev, "Sysconfig register mask must be set (%d)\n", err); ++ else ++ dev_dbg(dev, "Warning sysconfig register mask not set\n"); ++ } + + return err; + } +@@ -560,12 +572,24 @@ static struct stm32_ops stm32mp1_dwmac_d + .resume = stm32mp1_resume, + .parse_data = stm32mp1_parse_data, + .syscfg_clr_off = 0x44, ++ .is_mp13 = false, ++ .clk_rx_enable_in_suspend = true ++}; ++ ++static struct stm32_ops stm32mp13_dwmac_data = { ++ .set_mode = stm32mp1_set_mode, ++ .suspend = stm32mp1_suspend, ++ .resume = stm32mp1_resume, ++ .parse_data = stm32mp1_parse_data, ++ .syscfg_clr_off = 0x08, ++ .is_mp13 = true, + .clk_rx_enable_in_suspend = true + }; + + static const struct of_device_id stm32_dwmac_match[] = { + { .compatible = "st,stm32-dwmac", .data = &stm32mcu_dwmac_data}, + { .compatible = "st,stm32mp1-dwmac", .data = &stm32mp1_dwmac_data}, ++ { .compatible = "st,stm32mp13-dwmac", .data = &stm32mp13_dwmac_data}, + { } + }; + MODULE_DEVICE_TABLE(of, stm32_dwmac_match); diff --git a/target/linux/stm32/patches-6.6/009-net-stmmac-dwmac-stm32-Add-test-to-verify-if-ETHCK-i.patch b/target/linux/stm32/patches-6.6/009-net-stmmac-dwmac-stm32-Add-test-to-verify-if-ETHCK-i.patch new file mode 100644 index 00000000000..8cec988556e --- /dev/null +++ b/target/linux/stm32/patches-6.6/009-net-stmmac-dwmac-stm32-Add-test-to-verify-if-ETHCK-i.patch @@ -0,0 +1,32 @@ +From 3cd1d4651cebe9776a0142ade36ff9f2e3545436 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 1 Jul 2024 08:48:37 +0200 +Subject: [PATCH] net: stmmac: dwmac-stm32: Add test to verify if ETHCK is used + before checking clk rate + +When we want to use clock from RCC to clock Ethernet PHY (with ETHCK) +we need to check if value of clock rate is authorized. +If ETHCK is unused, the ETHCK frequency is 0Hz and validation fails. +It makes no sense to validate unused ETHCK, so skip the validation. + +Fixes: 582ac134963e ("net: stmmac: dwmac-stm32: Separate out external clock rate validation") +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Tested-by: Mark Brown +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 3 +++ + 1 file changed, 3 insertions(+) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -195,6 +195,9 @@ static int stm32mp1_validate_ethck_rate( + struct stm32_dwmac *dwmac = plat_dat->bsp_priv; + const u32 clk_rate = clk_get_rate(dwmac->clk_eth_ck); + ++ if (!dwmac->enable_eth_ck) ++ return 0; ++ + switch (plat_dat->mac_interface) { + case PHY_INTERFACE_MODE_MII: + case PHY_INTERFACE_MODE_GMII: diff --git a/target/linux/stm32/patches-6.6/010-net-stmmac-dwmac-stm32-update-err-status-in-case-dif.patch b/target/linux/stm32/patches-6.6/010-net-stmmac-dwmac-stm32-update-err-status-in-case-dif.patch new file mode 100644 index 00000000000..c9d6356e492 --- /dev/null +++ b/target/linux/stm32/patches-6.6/010-net-stmmac-dwmac-stm32-update-err-status-in-case-dif.patch @@ -0,0 +1,39 @@ +From f8dbe58e2f1a3c091531b3f8ef86b393ceee67d1 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 1 Jul 2024 08:48:38 +0200 +Subject: [PATCH] net: stmmac: dwmac-stm32: update err status in case different + of stm32mp13 + +The mask parameter of syscfg property is mandatory for MP13 but +optional for all other cases. +The function should not return error code because for non-MP13 +the missing syscfg phandle in DT is not considered an error. +So reset err to 0 in that case to support existing DTs without +syscfg phandle. + +Fixes: 50bbc0393114 ("net: stmmac: dwmac-stm32: add management of stm32mp13 for stm32") +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Tested-by: Mark Brown +Signed-off-by: Paolo Abeni +--- + drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -371,10 +371,12 @@ static int stm32_dwmac_parse_data(struct + dwmac->mode_mask = SYSCFG_MP1_ETH_MASK; + err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask); + if (err) { +- if (dwmac->ops->is_mp13) ++ if (dwmac->ops->is_mp13) { + dev_err(dev, "Sysconfig register mask must be set (%d)\n", err); +- else ++ } else { + dev_dbg(dev, "Warning sysconfig register mask not set\n"); ++ err = 0; ++ } + } + + return err; diff --git a/target/linux/stm32/patches-6.6/020-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch b/target/linux/stm32/patches-6.6/020-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch new file mode 100644 index 00000000000..f00001bc473 --- /dev/null +++ b/target/linux/stm32/patches-6.6/020-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch @@ -0,0 +1,1192 @@ +From d788961c5b25d9d822c4230bfbc536a6736b91ff Mon Sep 17 00:00:00 2001 +From: Gatien Chevallier +Date: Fri, 5 Jan 2024 14:04:03 +0100 +Subject: [PATCH 1/5] ARM: dts: stm32: add ETZPC as a system bus for STM32MP13x + boards + +ETZPC is a firewall controller. Put all peripherals filtered by the +ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for +backward compatibility. + +Signed-off-by: Gatien Chevallier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp131.dtsi | 1020 +++++++++++++------------ + arch/arm/boot/dts/st/stm32mp133.dtsi | 50 +- + arch/arm/boot/dts/st/stm32mp13xc.dtsi | 18 +- + arch/arm/boot/dts/st/stm32mp13xf.dtsi | 18 +- + 4 files changed, 569 insertions(+), 537 deletions(-) + +--- a/arch/arm/boot/dts/st/stm32mp131.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp131.dtsi +@@ -745,340 +745,6 @@ + dma-channels = <16>; + }; + +- adc_2: adc@48004000 { +- compatible = "st,stm32mp13-adc-core"; +- reg = <0x48004000 0x400>; +- interrupts = ; +- clocks = <&rcc ADC2>, <&rcc ADC2_K>; +- clock-names = "bus", "adc"; +- interrupt-controller; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- +- adc2: adc@0 { +- compatible = "st,stm32mp13-adc"; +- #io-channel-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- interrupt-parent = <&adc_2>; +- interrupts = <0>; +- dmas = <&dmamux1 10 0x400 0x80000001>; +- dma-names = "rx"; +- status = "disabled"; +- +- channel@13 { +- reg = <13>; +- label = "vrefint"; +- }; +- channel@14 { +- reg = <14>; +- label = "vddcore"; +- }; +- channel@16 { +- reg = <16>; +- label = "vddcpu"; +- }; +- channel@17 { +- reg = <17>; +- label = "vddq_ddr"; +- }; +- }; +- }; +- +- usbotg_hs: usb@49000000 { +- compatible = "st,stm32mp15-hsotg", "snps,dwc2"; +- reg = <0x49000000 0x40000>; +- clocks = <&rcc USBO_K>; +- clock-names = "otg"; +- resets = <&rcc USBO_R>; +- reset-names = "dwc2"; +- interrupts = ; +- g-rx-fifo-size = <512>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <256 16 16 16 16 16 16 16>; +- dr_mode = "otg"; +- otg-rev = <0x200>; +- usb33d-supply = <&scmi_usb33>; +- status = "disabled"; +- }; +- +- usart1: serial@4c000000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4c000000 0x400>; +- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART1_K>; +- resets = <&rcc USART1_R>; +- wakeup-source; +- dmas = <&dmamux1 41 0x400 0x5>, +- <&dmamux1 42 0x400 0x1>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- usart2: serial@4c001000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4c001000 0x400>; +- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART2_K>; +- resets = <&rcc USART2_R>; +- wakeup-source; +- dmas = <&dmamux1 43 0x400 0x5>, +- <&dmamux1 44 0x400 0x1>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2s4: audio-controller@4c002000 { +- compatible = "st,stm32h7-i2s"; +- reg = <0x4c002000 0x400>; +- #sound-dai-cells = <0>; +- interrupts = ; +- dmas = <&dmamux1 83 0x400 0x01>, +- <&dmamux1 84 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi4: spi@4c002000 { +- compatible = "st,stm32h7-spi"; +- reg = <0x4c002000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI4_K>; +- resets = <&rcc SPI4_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmamux1 83 0x400 0x01>, +- <&dmamux1 84 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- spi5: spi@4c003000 { +- compatible = "st,stm32h7-spi"; +- reg = <0x4c003000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI5_K>; +- resets = <&rcc SPI5_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmamux1 85 0x400 0x01>, +- <&dmamux1 86 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- i2c3: i2c@4c004000 { +- compatible = "st,stm32mp13-i2c"; +- reg = <0x4c004000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C3_K>; +- resets = <&rcc I2C3_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmamux1 73 0x400 0x1>, +- <&dmamux1 74 0x400 0x1>; +- dma-names = "rx", "tx"; +- st,syscfg-fmp = <&syscfg 0x4 0x4>; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- i2c4: i2c@4c005000 { +- compatible = "st,stm32mp13-i2c"; +- reg = <0x4c005000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C4_K>; +- resets = <&rcc I2C4_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmamux1 75 0x400 0x1>, +- <&dmamux1 76 0x400 0x1>; +- dma-names = "rx", "tx"; +- st,syscfg-fmp = <&syscfg 0x4 0x8>; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- i2c5: i2c@4c006000 { +- compatible = "st,stm32mp13-i2c"; +- reg = <0x4c006000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C5_K>; +- resets = <&rcc I2C5_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- dmas = <&dmamux1 115 0x400 0x1>, +- <&dmamux1 116 0x400 0x1>; +- dma-names = "rx", "tx"; +- st,syscfg-fmp = <&syscfg 0x4 0x10>; +- i2c-analog-filter; +- status = "disabled"; +- }; +- +- timers12: timer@4c007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x4c007000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM12_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@11 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <11>; +- status = "disabled"; +- }; +- }; +- +- timers13: timer@4c008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x4c008000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM13_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@12 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <12>; +- status = "disabled"; +- }; +- }; +- +- timers14: timer@4c009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x4c009000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM14_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@13 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <13>; +- status = "disabled"; +- }; +- }; +- +- timers15: timer@4c00a000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x4c00a000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM15_K>; +- clock-names = "int"; +- dmas = <&dmamux1 105 0x400 0x1>, +- <&dmamux1 106 0x400 0x1>, +- <&dmamux1 107 0x400 0x1>, +- <&dmamux1 108 0x400 0x1>; +- dma-names = "ch1", "up", "trig", "com"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@14 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <14>; +- status = "disabled"; +- }; +- }; +- +- timers16: timer@4c00b000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x4c00b000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM16_K>; +- clock-names = "int"; +- dmas = <&dmamux1 109 0x400 0x1>, +- <&dmamux1 110 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@15 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <15>; +- status = "disabled"; +- }; +- }; +- +- timers17: timer@4c00c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x4c00c000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM17_K>; +- clock-names = "int"; +- dmas = <&dmamux1 111 0x400 0x1>, +- <&dmamux1 112 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@16 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <16>; +- status = "disabled"; +- }; +- }; +- + rcc: rcc@50000000 { + compatible = "st,stm32mp13-rcc", "syscon"; + reg = <0x50000000 0x1000>; +@@ -1105,69 +771,6 @@ + clocks = <&rcc SYSCFG>; + }; + +- lptimer2: timer@50021000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50021000 0x400>; +- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM2_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@1 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- +- timer { +- compatible = "st,stm32-lptimer-timer"; +- status = "disabled"; +- }; +- }; +- +- lptimer3: timer@50022000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50022000 0x400>; +- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM3_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@2 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- +- timer { +- compatible = "st,stm32-lptimer-timer"; +- status = "disabled"; +- }; +- }; +- + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; +@@ -1220,79 +823,10 @@ + dma-requests = <48>; + }; + +- fmc: memory-controller@58002000 { +- compatible = "st,stm32mp1-fmc2-ebi"; +- reg = <0x58002000 0x1000>; +- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ +- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ +- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ +- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ +- <4 0 0x80000000 0x10000000>; /* NAND */ +- #address-cells = <2>; +- #size-cells = <1>; +- clocks = <&rcc FMC_K>; +- resets = <&rcc FMC_R>; +- status = "disabled"; +- +- nand-controller@4,0 { +- compatible = "st,stm32mp1-fmc2-nfc"; +- reg = <4 0x00000000 0x1000>, +- <4 0x08010000 0x1000>, +- <4 0x08020000 0x1000>, +- <4 0x01000000 0x1000>, +- <4 0x09010000 0x1000>, +- <4 0x09020000 0x1000>; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, +- <&mdma 24 0x2 0x12000a08 0x0 0x0>, +- <&mdma 25 0x2 0x12000a0a 0x0 0x0>; +- dma-names = "tx", "rx", "ecc"; +- status = "disabled"; +- }; +- }; +- +- qspi: spi@58003000 { +- compatible = "st,stm32f469-qspi"; +- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; +- reg-names = "qspi", "qspi_mm"; +- #address-cells = <1>; +- #size-cells = <0>; +- interrupts = ; +- dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, +- <&mdma 26 0x2 0x10100008 0x0 0x0>; +- dma-names = "tx", "rx"; +- clocks = <&rcc QSPI_K>; +- resets = <&rcc QSPI_R>; +- status = "disabled"; +- }; +- +- sdmmc1: mmc@58005000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x20253180>; +- reg = <0x58005000 0x1000>, <0x58006000 0x1000>; +- interrupts = ; +- clocks = <&rcc SDMMC1_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC1_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <130000000>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@58007000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x20253180>; +- reg = <0x58007000 0x1000>, <0x58008000 0x1000>; +- interrupts = ; +- clocks = <&rcc SDMMC2_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC2_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <130000000>; ++ crc1: crc@58009000 { ++ compatible = "st,stm32f7-crc"; ++ reg = <0x58009000 0x400>; ++ clocks = <&rcc CRC1>; + status = "disabled"; + }; + +@@ -1323,29 +857,6 @@ + status = "disabled"; + }; + +- usbphyc: usbphyc@5a006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "st,stm32mp1-usbphyc"; +- reg = <0x5a006000 0x1000>; +- clocks = <&rcc USBPHY_K>; +- resets = <&rcc USBPHY_R>; +- vdda1v1-supply = <&scmi_reg11>; +- vdda1v8-supply = <&scmi_reg18>; +- status = "disabled"; +- +- usbphyc_port0: usb-phy@0 { +- #phy-cells = <0>; +- reg = <0>; +- }; +- +- usbphyc_port1: usb-phy@1 { +- #phy-cells = <1>; +- reg = <1>; +- }; +- }; +- + rtc: rtc@5c004000 { + compatible = "st,stm32mp1-rtc"; + reg = <0x5c004000 0x400>; +@@ -1374,6 +885,529 @@ + }; + }; + ++ etzpc: bus@5c007000 { ++ compatible = "simple-bus"; ++ reg = <0x5c007000 0x400>; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges; ++ ++ adc_2: adc@48004000 { ++ compatible = "st,stm32mp13-adc-core"; ++ reg = <0x48004000 0x400>; ++ interrupts = ; ++ clocks = <&rcc ADC2>, <&rcc ADC2_K>; ++ clock-names = "bus", "adc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ ++ adc2: adc@0 { ++ compatible = "st,stm32mp13-adc"; ++ #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; ++ interrupt-parent = <&adc_2>; ++ interrupts = <0>; ++ dmas = <&dmamux1 10 0x400 0x80000001>; ++ dma-names = "rx"; ++ status = "disabled"; ++ ++ channel@13 { ++ reg = <13>; ++ label = "vrefint"; ++ }; ++ channel@14 { ++ reg = <14>; ++ label = "vddcore"; ++ }; ++ channel@16 { ++ reg = <16>; ++ label = "vddcpu"; ++ }; ++ channel@17 { ++ reg = <17>; ++ label = "vddq_ddr"; ++ }; ++ }; ++ }; ++ ++ usbotg_hs: usb@49000000 { ++ compatible = "st,stm32mp15-hsotg", "snps,dwc2"; ++ reg = <0x49000000 0x40000>; ++ clocks = <&rcc USBO_K>; ++ clock-names = "otg"; ++ resets = <&rcc USBO_R>; ++ reset-names = "dwc2"; ++ interrupts = ; ++ g-rx-fifo-size = <512>; ++ g-np-tx-fifo-size = <32>; ++ g-tx-fifo-size = <256 16 16 16 16 16 16 16>; ++ dr_mode = "otg"; ++ otg-rev = <0x200>; ++ usb33d-supply = <&scmi_usb33>; ++ status = "disabled"; ++ }; ++ ++ usart1: serial@4c000000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x4c000000 0x400>; ++ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART1_K>; ++ resets = <&rcc USART1_R>; ++ wakeup-source; ++ dmas = <&dmamux1 41 0x400 0x5>, ++ <&dmamux1 42 0x400 0x1>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ usart2: serial@4c001000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x4c001000 0x400>; ++ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART2_K>; ++ resets = <&rcc USART2_R>; ++ wakeup-source; ++ dmas = <&dmamux1 43 0x400 0x5>, ++ <&dmamux1 44 0x400 0x1>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ i2s4: audio-controller@4c002000 { ++ compatible = "st,stm32h7-i2s"; ++ reg = <0x4c002000 0x400>; ++ #sound-dai-cells = <0>; ++ interrupts = ; ++ dmas = <&dmamux1 83 0x400 0x01>, ++ <&dmamux1 84 0x400 0x01>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ spi4: spi@4c002000 { ++ compatible = "st,stm32h7-spi"; ++ reg = <0x4c002000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI4_K>; ++ resets = <&rcc SPI4_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dmamux1 83 0x400 0x01>, ++ <&dmamux1 84 0x400 0x01>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ spi5: spi@4c003000 { ++ compatible = "st,stm32h7-spi"; ++ reg = <0x4c003000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI5_K>; ++ resets = <&rcc SPI5_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dmamux1 85 0x400 0x01>, ++ <&dmamux1 86 0x400 0x01>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ i2c3: i2c@4c004000 { ++ compatible = "st,stm32mp13-i2c"; ++ reg = <0x4c004000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C3_K>; ++ resets = <&rcc I2C3_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dmamux1 73 0x400 0x1>, ++ <&dmamux1 74 0x400 0x1>; ++ dma-names = "rx", "tx"; ++ st,syscfg-fmp = <&syscfg 0x4 0x4>; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; ++ ++ i2c4: i2c@4c005000 { ++ compatible = "st,stm32mp13-i2c"; ++ reg = <0x4c005000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C4_K>; ++ resets = <&rcc I2C4_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dmamux1 75 0x400 0x1>, ++ <&dmamux1 76 0x400 0x1>; ++ dma-names = "rx", "tx"; ++ st,syscfg-fmp = <&syscfg 0x4 0x8>; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; ++ ++ i2c5: i2c@4c006000 { ++ compatible = "st,stm32mp13-i2c"; ++ reg = <0x4c006000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C5_K>; ++ resets = <&rcc I2C5_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ dmas = <&dmamux1 115 0x400 0x1>, ++ <&dmamux1 116 0x400 0x1>; ++ dma-names = "rx", "tx"; ++ st,syscfg-fmp = <&syscfg 0x4 0x10>; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; ++ ++ timers12: timer@4c007000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x4c007000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM12_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@11 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <11>; ++ status = "disabled"; ++ }; ++ }; ++ ++ timers13: timer@4c008000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x4c008000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM13_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@12 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <12>; ++ status = "disabled"; ++ }; ++ }; ++ ++ timers14: timer@4c009000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x4c009000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM14_K>; ++ clock-names = "int"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@13 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <13>; ++ status = "disabled"; ++ }; ++ }; ++ ++ timers15: timer@4c00a000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x4c00a000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM15_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 105 0x400 0x1>, ++ <&dmamux1 106 0x400 0x1>, ++ <&dmamux1 107 0x400 0x1>, ++ <&dmamux1 108 0x400 0x1>; ++ dma-names = "ch1", "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@14 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <14>; ++ status = "disabled"; ++ }; ++ }; ++ ++ timers16: timer@4c00b000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x4c00b000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM16_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 109 0x400 0x1>, ++ <&dmamux1 110 0x400 0x1>; ++ dma-names = "ch1", "up"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@15 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <15>; ++ status = "disabled"; ++ }; ++ }; ++ ++ timers17: timer@4c00c000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x4c00c000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM17_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 111 0x400 0x1>, ++ <&dmamux1 112 0x400 0x1>; ++ dma-names = "ch1", "up"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@16 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <16>; ++ status = "disabled"; ++ }; ++ }; ++ ++ lptimer2: timer@50021000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50021000 0x400>; ++ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM2_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ trigger@1 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-lptimer-counter"; ++ status = "disabled"; ++ }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; ++ }; ++ ++ lptimer3: timer@50022000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50022000 0x400>; ++ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM3_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ trigger@2 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ ++ timer { ++ compatible = "st,stm32-lptimer-timer"; ++ status = "disabled"; ++ }; ++ }; ++ ++ hash: hash@54003000 { ++ compatible = "st,stm32mp13-hash"; ++ reg = <0x54003000 0x400>; ++ interrupts = ; ++ clocks = <&rcc HASH1>; ++ resets = <&rcc HASH1_R>; ++ dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; ++ dma-names = "in"; ++ status = "disabled"; ++ }; ++ ++ rng: rng@54004000 { ++ compatible = "st,stm32mp13-rng"; ++ reg = <0x54004000 0x400>; ++ clocks = <&rcc RNG1_K>; ++ resets = <&rcc RNG1_R>; ++ status = "disabled"; ++ }; ++ ++ fmc: memory-controller@58002000 { ++ compatible = "st,stm32mp1-fmc2-ebi"; ++ reg = <0x58002000 0x1000>; ++ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ ++ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ ++ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ ++ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ ++ <4 0 0x80000000 0x10000000>; /* NAND */ ++ #address-cells = <2>; ++ #size-cells = <1>; ++ clocks = <&rcc FMC_K>; ++ resets = <&rcc FMC_R>; ++ status = "disabled"; ++ ++ nand-controller@4,0 { ++ compatible = "st,stm32mp1-fmc2-nfc"; ++ reg = <4 0x00000000 0x1000>, ++ <4 0x08010000 0x1000>, ++ <4 0x08020000 0x1000>, ++ <4 0x01000000 0x1000>, ++ <4 0x09010000 0x1000>, ++ <4 0x09020000 0x1000>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ dmas = <&mdma 24 0x2 0x12000a02 0x0 0x0>, ++ <&mdma 24 0x2 0x12000a08 0x0 0x0>, ++ <&mdma 25 0x2 0x12000a0a 0x0 0x0>; ++ dma-names = "tx", "rx", "ecc"; ++ status = "disabled"; ++ }; ++ }; ++ ++ qspi: spi@58003000 { ++ compatible = "st,stm32f469-qspi"; ++ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; ++ reg-names = "qspi", "qspi_mm"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ interrupts = ; ++ dmas = <&mdma 26 0x2 0x10100002 0x0 0x0>, ++ <&mdma 26 0x2 0x10100008 0x0 0x0>; ++ dma-names = "tx", "rx"; ++ clocks = <&rcc QSPI_K>; ++ resets = <&rcc QSPI_R>; ++ status = "disabled"; ++ }; ++ ++ sdmmc1: mmc@58005000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x20253180>; ++ reg = <0x58005000 0x1000>, <0x58006000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc SDMMC1_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC1_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <130000000>; ++ status = "disabled"; ++ }; ++ ++ sdmmc2: mmc@58007000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x20253180>; ++ reg = <0x58007000 0x1000>, <0x58008000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc SDMMC2_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC2_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <130000000>; ++ status = "disabled"; ++ }; ++ ++ usbphyc: usbphyc@5a006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "st,stm32mp1-usbphyc"; ++ reg = <0x5a006000 0x1000>; ++ clocks = <&rcc USBPHY_K>; ++ resets = <&rcc USBPHY_R>; ++ vdda1v1-supply = <&scmi_reg11>; ++ vdda1v8-supply = <&scmi_reg18>; ++ status = "disabled"; ++ ++ usbphyc_port0: usb-phy@0 { ++ #phy-cells = <0>; ++ reg = <0>; ++ }; ++ ++ usbphyc_port1: usb-phy@1 { ++ #phy-cells = <1>; ++ reg = <1>; ++ }; ++ }; ++ }; ++ + /* + * Break node order to solve dependency probe issue between + * pinctrl and exti. +--- a/arch/arm/boot/dts/st/stm32mp133.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp133.dtsi +@@ -33,35 +33,37 @@ + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; + status = "disabled"; + }; ++ }; ++}; ++ ++&etzpc { ++ adc_1: adc@48003000 { ++ compatible = "st,stm32mp13-adc-core"; ++ reg = <0x48003000 0x400>; ++ interrupts = ; ++ clocks = <&rcc ADC1>, <&rcc ADC1_K>; ++ clock-names = "bus", "adc"; ++ interrupt-controller; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; + +- adc_1: adc@48003000 { +- compatible = "st,stm32mp13-adc-core"; +- reg = <0x48003000 0x400>; +- interrupts = ; +- clocks = <&rcc ADC1>, <&rcc ADC1_K>; +- clock-names = "bus", "adc"; +- interrupt-controller; +- #interrupt-cells = <1>; ++ adc1: adc@0 { ++ compatible = "st,stm32mp13-adc"; ++ #io-channel-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; ++ reg = <0x0>; ++ interrupt-parent = <&adc_1>; ++ interrupts = <0>; ++ dmas = <&dmamux1 9 0x400 0x80000001>; ++ dma-names = "rx"; + status = "disabled"; + +- adc1: adc@0 { +- compatible = "st,stm32mp13-adc"; +- #io-channel-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- reg = <0x0>; +- interrupt-parent = <&adc_1>; +- interrupts = <0>; +- dmas = <&dmamux1 9 0x400 0x80000001>; +- dma-names = "rx"; +- status = "disabled"; +- +- channel@18 { +- reg = <18>; +- label = "vrefint"; +- }; ++ channel@18 { ++ reg = <18>; ++ label = "vrefint"; + }; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi +@@ -4,15 +4,13 @@ + * Author: Alexandre Torgue for STMicroelectronics. + */ + +-/ { +- soc { +- cryp: crypto@54002000 { +- compatible = "st,stm32mp1-cryp"; +- reg = <0x54002000 0x400>; +- interrupts = ; +- clocks = <&rcc CRYP1>; +- resets = <&rcc CRYP1_R>; +- status = "disabled"; +- }; ++&etzpc { ++ cryp: crypto@54002000 { ++ compatible = "st,stm32mp1-cryp"; ++ reg = <0x54002000 0x400>; ++ interrupts = ; ++ clocks = <&rcc CRYP1>; ++ resets = <&rcc CRYP1_R>; ++ status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi +@@ -4,15 +4,13 @@ + * Author: Alexandre Torgue for STMicroelectronics. + */ + +-/ { +- soc { +- cryp: crypto@54002000 { +- compatible = "st,stm32mp1-cryp"; +- reg = <0x54002000 0x400>; +- interrupts = ; +- clocks = <&rcc CRYP1>; +- resets = <&rcc CRYP1_R>; +- status = "disabled"; +- }; ++&etzpc { ++ cryp: crypto@54002000 { ++ compatible = "st,stm32mp1-cryp"; ++ reg = <0x54002000 0x400>; ++ interrupts = ; ++ clocks = <&rcc CRYP1>; ++ resets = <&rcc CRYP1_R>; ++ status = "disabled"; + }; + }; diff --git a/target/linux/stm32/patches-6.6/021-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch b/target/linux/stm32/patches-6.6/021-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch new file mode 100644 index 00000000000..e6a4eee0571 --- /dev/null +++ b/target/linux/stm32/patches-6.6/021-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch @@ -0,0 +1,265 @@ +From 21ca3d7c59595d76237faebeff4f6a979cf7ae82 Mon Sep 17 00:00:00 2001 +From: Alexandre Torgue +Date: Fri, 5 Apr 2024 13:45:24 +0200 +Subject: [PATCH 2/5] ARM: dts: stm32: put ETZPC as an access controller for + STM32MP13x boards + +Reference ETZPC as an access-control-provider. + +For more information on which peripheral is securable or supports MCU +isolation, please read the STM32MP13 reference manual + +Signed-off-by: Gatien Chevallier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp131.dtsi | 28 ++++++++++++++++++++++++++- + arch/arm/boot/dts/st/stm32mp133.dtsi | 1 + + arch/arm/boot/dts/st/stm32mp13xc.dtsi | 1 + + arch/arm/boot/dts/st/stm32mp13xf.dtsi | 1 + + 4 files changed, 30 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/st/stm32mp131.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp131.dtsi +@@ -886,10 +886,11 @@ + }; + + etzpc: bus@5c007000 { +- compatible = "simple-bus"; ++ compatible = "st,stm32-etzpc", "simple-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; ++ #access-controller-cells = <1>; + ranges; + + adc_2: adc@48004000 { +@@ -902,6 +903,7 @@ + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 33>; + status = "disabled"; + + adc2: adc@0 { +@@ -949,6 +951,7 @@ + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&scmi_usb33>; ++ access-controllers = <&etzpc 34>; + status = "disabled"; + }; + +@@ -962,6 +965,7 @@ + dmas = <&dmamux1 41 0x400 0x5>, + <&dmamux1 42 0x400 0x1>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 16>; + status = "disabled"; + }; + +@@ -975,6 +979,7 @@ + dmas = <&dmamux1 43 0x400 0x5>, + <&dmamux1 44 0x400 0x1>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 17>; + status = "disabled"; + }; + +@@ -986,6 +991,7 @@ + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 13>; + status = "disabled"; + }; + +@@ -1000,6 +1006,7 @@ + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 18>; + status = "disabled"; + }; + +@@ -1014,6 +1021,7 @@ + dmas = <&dmamux1 85 0x400 0x01>, + <&dmamux1 86 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 19>; + status = "disabled"; + }; + +@@ -1032,6 +1040,7 @@ + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x4>; + i2c-analog-filter; ++ access-controllers = <&etzpc 20>; + status = "disabled"; + }; + +@@ -1050,6 +1059,7 @@ + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x8>; + i2c-analog-filter; ++ access-controllers = <&etzpc 21>; + status = "disabled"; + }; + +@@ -1068,6 +1078,7 @@ + dma-names = "rx", "tx"; + st,syscfg-fmp = <&syscfg 0x4 0x10>; + i2c-analog-filter; ++ access-controllers = <&etzpc 22>; + status = "disabled"; + }; + +@@ -1080,6 +1091,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 23>; + status = "disabled"; + + pwm { +@@ -1104,6 +1116,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 24>; + status = "disabled"; + + pwm { +@@ -1128,6 +1141,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 25>; + status = "disabled"; + + pwm { +@@ -1157,6 +1171,7 @@ + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; ++ access-controllers = <&etzpc 26>; + status = "disabled"; + + pwm { +@@ -1184,6 +1199,7 @@ + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; ++ access-controllers = <&etzpc 27>; + status = "disabled"; + + pwm { +@@ -1211,6 +1227,7 @@ + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; ++ access-controllers = <&etzpc 28>; + status = "disabled"; + + pwm { +@@ -1235,6 +1252,7 @@ + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 1>; + status = "disabled"; + + pwm { +@@ -1269,6 +1287,7 @@ + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 2>; + status = "disabled"; + + pwm { +@@ -1297,6 +1316,7 @@ + resets = <&rcc HASH1_R>; + dmas = <&mdma 30 0x2 0x1000a02 0x0 0x0>; + dma-names = "in"; ++ access-controllers = <&etzpc 41>; + status = "disabled"; + }; + +@@ -1305,6 +1325,7 @@ + reg = <0x54004000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; ++ access-controllers = <&etzpc 40>; + status = "disabled"; + }; + +@@ -1320,6 +1341,7 @@ + #size-cells = <1>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; ++ access-controllers = <&etzpc 54>; + status = "disabled"; + + nand-controller@4,0 { +@@ -1353,6 +1375,7 @@ + dma-names = "tx", "rx"; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; ++ access-controllers = <&etzpc 55>; + status = "disabled"; + }; + +@@ -1367,6 +1390,7 @@ + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; ++ access-controllers = <&etzpc 50>; + status = "disabled"; + }; + +@@ -1381,6 +1405,7 @@ + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <130000000>; ++ access-controllers = <&etzpc 51>; + status = "disabled"; + }; + +@@ -1394,6 +1419,7 @@ + resets = <&rcc USBPHY_R>; + vdda1v1-supply = <&scmi_reg11>; + vdda1v8-supply = <&scmi_reg18>; ++ access-controllers = <&etzpc 5>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { +--- a/arch/arm/boot/dts/st/stm32mp133.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp133.dtsi +@@ -47,6 +47,7 @@ + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 32>; + status = "disabled"; + + adc1: adc@0 { +--- a/arch/arm/boot/dts/st/stm32mp13xc.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp13xc.dtsi +@@ -11,6 +11,7 @@ + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; ++ access-controllers = <&etzpc 42>; + status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp13xf.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp13xf.dtsi +@@ -11,6 +11,7 @@ + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; ++ access-controllers = <&etzpc 42>; + status = "disabled"; + }; + }; diff --git a/target/linux/stm32/patches-6.6/022-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch b/target/linux/stm32/patches-6.6/022-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch new file mode 100644 index 00000000000..123bde88417 --- /dev/null +++ b/target/linux/stm32/patches-6.6/022-ARM-dts-stm32-add-ethernet1-2-RMII-pins-for-STM32MP1.patch @@ -0,0 +1,126 @@ +From b1468a44e0c0f43a06e027efeff4183b3aee0cf7 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 10 Jun 2024 10:03:08 +0200 +Subject: [PATCH 3/5] ARM: dts: stm32: add ethernet1/2 RMII pins for + STM32MP13F-DK board + +Those pins are used for Ethernet 1 and 2 on STM32MP13F-DK board. +ethernet1: RMII with crystal. +ethernet2: RMII without crystal. +Add analog gpio pin configuration ("sleep") to manage power mode on +stm32mp13. + +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 98 +++++++++++++++++++++ + 1 file changed, 98 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +@@ -13,6 +13,104 @@ + }; + }; + ++ eth1_rgmii_pins_a: eth1-rgmii-0 { ++ pins1 { ++ pinmux = , /* ETH_RGMII_TXD0 */ ++ , /* ETH_RGMII_TXD1 */ ++ , /* ETH_RGMII_TXD2 */ ++ , /* ETH_RGMII_TXD3 */ ++ , /* ETH_RGMII_TX_CTL */ ++ , /* ETH_RGMII_GTX_CLK */ ++ , /* ETH_MDIO */ ++ ; /* ETH_MDC */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <2>; ++ }; ++ ++ pins2 { ++ pinmux = , /* ETH_RGMII_RXD0 */ ++ , /* ETH_RGMII_RXD1 */ ++ , /* ETH_RGMII_RXD2 */ ++ , /* ETH_RGMII_RXD3 */ ++ , /* ETH_RGMII_RX_CTL */ ++ ; /* ETH_RGMII_RX_CLK */ ++ bias-disable; ++ }; ++ ++ }; ++ ++ eth1_rmii_pins_a: eth1-rmii-0 { ++ pins1 { ++ pinmux = , /* ETH_RMII_TXD0 */ ++ , /* ETH_RMII_TXD1 */ ++ , /* ETH_RMII_TX_EN */ ++ , /* ETH_RMII_REF_CLK */ ++ , /* ETH_MDIO */ ++ ; /* ETH_MDC */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ ++ pins2 { ++ pinmux = , /* ETH_RMII_RXD0 */ ++ , /* ETH_RMII_RXD1 */ ++ ; /* ETH_RMII_CRS_DV */ ++ bias-disable; ++ }; ++ ++ }; ++ ++ eth1_rmii_sleep_pins_a: eth1-rmii-sleep-0 { ++ pins1 { ++ pinmux = , /* ETH_RMII_TXD0 */ ++ , /* ETH_RMII_TXD1 */ ++ , /* ETH_RMII_TX_EN */ ++ , /* ETH_RMII_REF_CLK */ ++ , /* ETH_MDIO */ ++ , /* ETH_MDC */ ++ , /* ETH_RMII_RXD0 */ ++ , /* ETH_RMII_RXD1 */ ++ ; /* ETH_RMII_CRS_DV */ ++ }; ++ }; ++ ++ eth2_rmii_pins_a: eth2-rmii-0 { ++ pins1 { ++ pinmux = , /* ETH_RMII_TXD0 */ ++ , /* ETH_RMII_TXD1 */ ++ , /* ETH_RMII_ETHCK */ ++ , /* ETH_RMII_TX_EN */ ++ , /* ETH_MDIO */ ++ ; /* ETH_MDC */ ++ bias-disable; ++ drive-push-pull; ++ slew-rate = <1>; ++ }; ++ ++ pins2 { ++ pinmux = , /* ETH_RMII_RXD0 */ ++ , /* ETH_RMII_RXD1 */ ++ ; /* ETH_RMII_CRS_DV */ ++ bias-disable; ++ }; ++ }; ++ ++ eth2_rmii_sleep_pins_a: eth2-rmii-sleep-0 { ++ pins1 { ++ pinmux = , /* ETH_RMII_TXD0 */ ++ , /* ETH_RMII_TXD1 */ ++ , /* ETH_RMII_ETHCK */ ++ , /* ETH_RMII_TX_EN */ ++ , /* ETH_MDIO */ ++ , /* ETH_MDC */ ++ , /* ETH_RMII_RXD0 */ ++ , /* ETH_RMII_RXD1 */ ++ ; /* ETH_RMII_CRS_DV */ ++ }; ++ }; ++ + i2c1_pins_a: i2c1-0 { + pins { + pinmux = , /* I2C1_SCL */ diff --git a/target/linux/stm32/patches-6.6/023-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch b/target/linux/stm32/patches-6.6/023-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch new file mode 100644 index 00000000000..947b1413244 --- /dev/null +++ b/target/linux/stm32/patches-6.6/023-ARM-dts-stm32-add-ethernet1-and-ethernet2-support-on.patch @@ -0,0 +1,108 @@ +From fcf6ca2da4650d0a7a9cd62c8c72341860931159 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 10 Jun 2024 10:03:07 +0200 +Subject: [PATCH 4/5] ARM: dts: stm32: add ethernet1 and ethernet2 support on + stm32mp13 + +Both instances ethernet based on GMAC SNPS IP on stm32mp13. +GMAC IP version is SNPS 4.20. + +Signed-off-by: Christophe Roullier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp131.dtsi | 38 ++++++++++++++++++++++++++++ + arch/arm/boot/dts/st/stm32mp133.dtsi | 31 +++++++++++++++++++++++ + 2 files changed, 69 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp131.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp131.dtsi +@@ -883,6 +883,12 @@ + ts_cal2: calib@5e { + reg = <0x5e 0x2>; + }; ++ ethernet_mac1_address: mac1@e4 { ++ reg = <0xe4 0x6>; ++ }; ++ ethernet_mac2_address: mac2@ea { ++ reg = <0xea 0x6>; ++ }; + }; + + etzpc: bus@5c007000 { +@@ -1409,6 +1415,38 @@ + status = "disabled"; + }; + ++ ethernet1: ethernet@5800a000 { ++ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; ++ reg = <0x5800a000 0x2000>; ++ reg-names = "stmmaceth"; ++ interrupts-extended = <&intc GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>, ++ <&exti 68 1>; ++ interrupt-names = "macirq", "eth_wake_irq"; ++ clock-names = "stmmaceth", ++ "mac-clk-tx", ++ "mac-clk-rx", ++ "ethstp", ++ "eth-ck"; ++ clocks = <&rcc ETH1MAC>, ++ <&rcc ETH1TX>, ++ <&rcc ETH1RX>, ++ <&rcc ETH1STP>, ++ <&rcc ETH1CK_K>; ++ st,syscon = <&syscfg 0x4 0xff0000>; ++ snps,mixed-burst; ++ snps,pbl = <2>; ++ snps,axi-config = <&stmmac_axi_config_1>; ++ snps,tso; ++ access-controllers = <&etzpc 48>; ++ status = "disabled"; ++ ++ stmmac_axi_config_1: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <0x7>; ++ snps,wr_osr_lmt = <0x7>; ++ }; ++ }; ++ + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; +--- a/arch/arm/boot/dts/st/stm32mp133.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp133.dtsi +@@ -68,4 +68,35 @@ + }; + }; + }; ++ ++ ethernet2: ethernet@5800e000 { ++ compatible = "st,stm32mp13-dwmac", "snps,dwmac-4.20a"; ++ reg = <0x5800e000 0x2000>; ++ reg-names = "stmmaceth"; ++ interrupts-extended = <&intc GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq"; ++ clock-names = "stmmaceth", ++ "mac-clk-tx", ++ "mac-clk-rx", ++ "ethstp", ++ "eth-ck"; ++ clocks = <&rcc ETH2MAC>, ++ <&rcc ETH2TX>, ++ <&rcc ETH2RX>, ++ <&rcc ETH2STP>, ++ <&rcc ETH2CK_K>; ++ st,syscon = <&syscfg 0x4 0xff000000>; ++ snps,mixed-burst; ++ snps,pbl = <2>; ++ snps,axi-config = <&stmmac_axi_config_2>; ++ snps,tso; ++ access-controllers = <&etzpc 49>; ++ status = "disabled"; ++ ++ stmmac_axi_config_2: stmmac-axi-config { ++ snps,blen = <0 0 0 0 16 8 4>; ++ snps,rd_osr_lmt = <0x7>; ++ snps,wr_osr_lmt = <0x7>; ++ }; ++ }; + }; diff --git a/target/linux/stm32/patches-6.6/024-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch b/target/linux/stm32/patches-6.6/024-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch new file mode 100644 index 00000000000..79408c5bade --- /dev/null +++ b/target/linux/stm32/patches-6.6/024-ARM-dts-stm32-add-ethernet1-for-STM32MP135F-DK-board.patch @@ -0,0 +1,58 @@ +From b255afeeb33efaa974b1b2454b1f58252d783b67 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Mon, 10 Jun 2024 10:03:09 +0200 +Subject: [PATCH 5/5] ARM: dts: stm32: add ethernet1 for STM32MP135F-DK board + +Ethernet1: RMII with crystal +Ethernet2: RMII with no cristal, need "phy-supply" property to work, +today this property was managed by Ethernet glue, but should be present +and managed in PHY node. So I will push second Ethernet in next step. + +PHYs used are SMSC (LAN8742A) + +Signed-off-by: Christophe Roullier +Reviewed-by: Marek Vasut +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp135f-dk.dts | 23 +++++++++++++++++++++++ + 1 file changed, 23 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts ++++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts +@@ -19,6 +19,7 @@ + compatible = "st,stm32mp135f-dk", "st,stm32mp135"; + + aliases { ++ ethernet0 = ðernet1; + serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; +@@ -92,6 +93,28 @@ + }; + }; + }; ++ ++ðernet1 { ++ status = "okay"; ++ pinctrl-0 = <ð1_rmii_pins_a>; ++ pinctrl-1 = <ð1_rmii_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ phy-mode = "rmii"; ++ phy-handle = <&phy0_eth1>; ++ ++ mdio { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ ++ phy0_eth1: ethernet-phy@0 { ++ compatible = "ethernet-phy-id0007.c131"; ++ reg = <0>; ++ reset-gpios = <&mcp23017 9 GPIO_ACTIVE_LOW>; ++ wakeup-source; ++ }; ++ }; ++}; + + &i2c1 { + pinctrl-names = "default", "sleep"; diff --git a/target/linux/stm32/patches-6.6/030-rtc-stm32-add-pinctrl-and-pinmux-interfaces.patch b/target/linux/stm32/patches-6.6/030-rtc-stm32-add-pinctrl-and-pinmux-interfaces.patch new file mode 100644 index 00000000000..e06ea134c5a --- /dev/null +++ b/target/linux/stm32/patches-6.6/030-rtc-stm32-add-pinctrl-and-pinmux-interfaces.patch @@ -0,0 +1,189 @@ +From c15671ce05a038b8c92a6f1e24b0b850a154ba59 Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Mon, 22 Jul 2024 18:00:20 +0200 +Subject: [PATCH] rtc: stm32: add pinctrl and pinmux interfaces + +STM32 RTC is capable to handle 3 specific pins of the soc. +"out1, out2 and out2_rmp". To handle this, we use pinctrl framework. +There is a single pin per group. + +Signed-off-by: Valentin Caron +Reviewed-by: Linus Walleij +Link: https://lore.kernel.org/r/20240722160022.454226-3-valentin.caron@foss.st.com +Signed-off-by: Alexandre Belloni +--- + drivers/rtc/Kconfig | 5 ++ + drivers/rtc/rtc-stm32.c | 120 ++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 125 insertions(+) + +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1887,6 +1887,11 @@ config RTC_DRV_STM32 + tristate "STM32 RTC" + select REGMAP_MMIO + depends on ARCH_STM32 || COMPILE_TEST ++ depends on OF ++ depends on PINCTRL ++ select PINMUX ++ select PINCONF ++ select GENERIC_PINCONF + help + If you say yes here you get support for the STM32 On-Chip + Real Time Clock. +--- a/drivers/rtc/rtc-stm32.c ++++ b/drivers/rtc/rtc-stm32.c +@@ -12,6 +12,9 @@ + #include + #include + #include ++#include ++#include ++#include + #include + #include + #include +@@ -94,6 +97,14 @@ + /* STM32 RTC driver time helpers */ + #define SEC_PER_DAY (24 * 60 * 60) + ++/* STM32 RTC pinctrl helpers */ ++#define STM32_RTC_PINMUX(_name, _action, ...) { \ ++ .name = (_name), \ ++ .action = (_action), \ ++ .groups = ((const char *[]){ __VA_ARGS__ }), \ ++ .num_groups = ARRAY_SIZE(((const char *[]){ __VA_ARGS__ })), \ ++} ++ + struct stm32_rtc; + + struct stm32_rtc_registers { +@@ -149,6 +160,106 @@ static void stm32_rtc_wpr_lock(struct st + writel_relaxed(RTC_WPR_WRONG_KEY, rtc->base + regs->wpr); + } + ++enum stm32_rtc_pin_name { ++ NONE, ++ OUT1, ++ OUT2, ++ OUT2_RMP ++}; ++ ++static const struct pinctrl_pin_desc stm32_rtc_pinctrl_pins[] = { ++ PINCTRL_PIN(OUT1, "out1"), ++ PINCTRL_PIN(OUT2, "out2"), ++ PINCTRL_PIN(OUT2_RMP, "out2_rmp"), ++}; ++ ++static int stm32_rtc_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) ++{ ++ return ARRAY_SIZE(stm32_rtc_pinctrl_pins); ++} ++ ++static const char *stm32_rtc_pinctrl_get_group_name(struct pinctrl_dev *pctldev, ++ unsigned int selector) ++{ ++ return stm32_rtc_pinctrl_pins[selector].name; ++} ++ ++static int stm32_rtc_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, ++ unsigned int selector, ++ const unsigned int **pins, ++ unsigned int *num_pins) ++{ ++ *pins = &stm32_rtc_pinctrl_pins[selector].number; ++ *num_pins = 1; ++ return 0; ++} ++ ++static const struct pinctrl_ops stm32_rtc_pinctrl_ops = { ++ .dt_node_to_map = pinconf_generic_dt_node_to_map_all, ++ .dt_free_map = pinconf_generic_dt_free_map, ++ .get_groups_count = stm32_rtc_pinctrl_get_groups_count, ++ .get_group_name = stm32_rtc_pinctrl_get_group_name, ++ .get_group_pins = stm32_rtc_pinctrl_get_group_pins, ++}; ++ ++struct stm32_rtc_pinmux_func { ++ const char *name; ++ const char * const *groups; ++ const unsigned int num_groups; ++ int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin); ++}; ++ ++static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] = { ++}; ++ ++static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctldev) ++{ ++ return ARRAY_SIZE(stm32_rtc_pinmux_functions); ++} ++ ++static const char *stm32_rtc_pinmux_get_fname(struct pinctrl_dev *pctldev, unsigned int selector) ++{ ++ return stm32_rtc_pinmux_functions[selector].name; ++} ++ ++static int stm32_rtc_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned int selector, ++ const char * const **groups, unsigned int * const num_groups) ++{ ++ *groups = stm32_rtc_pinmux_functions[selector].groups; ++ *num_groups = stm32_rtc_pinmux_functions[selector].num_groups; ++ return 0; ++} ++ ++static int stm32_rtc_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector, ++ unsigned int group) ++{ ++ struct stm32_rtc_pinmux_func selected_func = stm32_rtc_pinmux_functions[selector]; ++ struct pinctrl_pin_desc pin = stm32_rtc_pinctrl_pins[group]; ++ ++ /* Call action */ ++ if (selected_func.action) ++ return selected_func.action(pctldev, pin.number); ++ ++ return -EINVAL; ++} ++ ++static const struct pinmux_ops stm32_rtc_pinmux_ops = { ++ .get_functions_count = stm32_rtc_pinmux_get_functions_count, ++ .get_function_name = stm32_rtc_pinmux_get_fname, ++ .get_function_groups = stm32_rtc_pinmux_get_groups, ++ .set_mux = stm32_rtc_pinmux_set_mux, ++ .strict = true, ++}; ++ ++static struct pinctrl_desc stm32_rtc_pdesc = { ++ .name = DRIVER_NAME, ++ .pins = stm32_rtc_pinctrl_pins, ++ .npins = ARRAY_SIZE(stm32_rtc_pinctrl_pins), ++ .owner = THIS_MODULE, ++ .pctlops = &stm32_rtc_pinctrl_ops, ++ .pmxops = &stm32_rtc_pinmux_ops, ++}; ++ + static int stm32_rtc_enter_init_mode(struct stm32_rtc *rtc) + { + const struct stm32_rtc_registers *regs = &rtc->data->regs; +@@ -723,6 +834,7 @@ static int stm32_rtc_probe(struct platfo + { + struct stm32_rtc *rtc; + const struct stm32_rtc_registers *regs; ++ struct pinctrl_dev *pctl; + int ret; + + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); +@@ -834,6 +946,14 @@ static int stm32_rtc_probe(struct platfo + goto err; + } + ++ ret = devm_pinctrl_register_and_init(&pdev->dev, &stm32_rtc_pdesc, rtc, &pctl); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "pinctrl register failed"); ++ ++ ret = pinctrl_enable(pctl); ++ if (ret) ++ return dev_err_probe(&pdev->dev, ret, "pinctrl enable failed"); ++ + /* + * If INITS flag is reset (calendar year field set to 0x00), calendar + * must be initialized diff --git a/target/linux/stm32/patches-6.6/031-rtc-stm32-add-Low-Speed-Clock-Output-LSCO-support.patch b/target/linux/stm32/patches-6.6/031-rtc-stm32-add-Low-Speed-Clock-Output-LSCO-support.patch new file mode 100644 index 00000000000..1ac09745721 --- /dev/null +++ b/target/linux/stm32/patches-6.6/031-rtc-stm32-add-Low-Speed-Clock-Output-LSCO-support.patch @@ -0,0 +1,253 @@ +From 229476a4de2e237ebadddca8a82d20afa9298f71 Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Mon, 22 Jul 2024 18:00:21 +0200 +Subject: [PATCH] rtc: stm32: add Low Speed Clock Output (LSCO) support + +RTC is able to output on a pin the "LSE" internal clock. + +STM32 RTC is now registered as a clock provider. +It provides rtc_lsco clock, that means RTC_LSCO is output on either +RTC_OUT1 or RTC_OUT2_RMP, depending on pinmux DT property. +The clock is marked as CLK_IGNORE_UNUSED and CLK_IS_CRITICAL because +RTC_LSCO can be early required by devices needed it to init. + +Add LSCO in pinmux functions. + +Add "stm32_rtc_clean_outs" to disable LSCO. As RTC is part of "backup" +power domain, it is not reset during shutdown or reboot. So force LSCO +disable at probe. + +Co-developed-by: Amelie Delaunay +Signed-off-by: Amelie Delaunay +Signed-off-by: Valentin Caron +Link: https://lore.kernel.org/r/20240722160022.454226-4-valentin.caron@foss.st.com +Signed-off-by: Alexandre Belloni +--- + drivers/rtc/Kconfig | 1 + + drivers/rtc/rtc-stm32.c | 99 +++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 100 insertions(+) + +--- a/drivers/rtc/Kconfig ++++ b/drivers/rtc/Kconfig +@@ -1892,6 +1892,7 @@ config RTC_DRV_STM32 + select PINMUX + select PINCONF + select GENERIC_PINCONF ++ depends on COMMON_CLK + help + If you say yes here you get support for the STM32 On-Chip + Real Time Clock. +--- a/drivers/rtc/rtc-stm32.c ++++ b/drivers/rtc/rtc-stm32.c +@@ -6,6 +6,7 @@ + + #include + #include ++#include + #include + #include + #include +@@ -44,6 +45,10 @@ + #define STM32_RTC_CR_FMT BIT(6) + #define STM32_RTC_CR_ALRAE BIT(8) + #define STM32_RTC_CR_ALRAIE BIT(12) ++#define STM32_RTC_CR_OSEL GENMASK(22, 21) ++#define STM32_RTC_CR_COE BIT(23) ++#define STM32_RTC_CR_TAMPOE BIT(26) ++#define STM32_RTC_CR_OUT2EN BIT(31) + + /* STM32_RTC_ISR/STM32_RTC_ICSR bit fields */ + #define STM32_RTC_ISR_ALRAWF BIT(0) +@@ -80,6 +85,12 @@ + /* STM32_RTC_SR/_SCR bit fields */ + #define STM32_RTC_SR_ALRA BIT(0) + ++/* STM32_RTC_CFGR bit fields */ ++#define STM32_RTC_CFGR_OUT2_RMP BIT(0) ++#define STM32_RTC_CFGR_LSCOEN GENMASK(2, 1) ++#define STM32_RTC_CFGR_LSCOEN_OUT1 1 ++#define STM32_RTC_CFGR_LSCOEN_OUT2_RMP 2 ++ + /* STM32_RTC_VERR bit fields */ + #define STM32_RTC_VERR_MINREV_SHIFT 0 + #define STM32_RTC_VERR_MINREV GENMASK(3, 0) +@@ -117,6 +128,7 @@ struct stm32_rtc_registers { + u16 wpr; + u16 sr; + u16 scr; ++ u16 cfgr; + u16 verr; + }; + +@@ -131,6 +143,7 @@ struct stm32_rtc_data { + bool has_pclk; + bool need_dbp; + bool need_accuracy; ++ bool has_lsco; + }; + + struct stm32_rtc { +@@ -143,6 +156,7 @@ struct stm32_rtc { + struct clk *rtc_ck; + const struct stm32_rtc_data *data; + int irq_alarm; ++ struct clk *clk_lsco; + }; + + static void stm32_rtc_wpr_unlock(struct stm32_rtc *rtc) +@@ -209,7 +223,68 @@ struct stm32_rtc_pinmux_func { + int (*action)(struct pinctrl_dev *pctl_dev, unsigned int pin); + }; + ++static int stm32_rtc_pinmux_lsco_available(struct pinctrl_dev *pctldev, unsigned int pin) ++{ ++ struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); ++ struct stm32_rtc_registers regs = rtc->data->regs; ++ unsigned int cr = readl_relaxed(rtc->base + regs.cr); ++ unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); ++ unsigned int calib = STM32_RTC_CR_COE; ++ unsigned int tampalrm = STM32_RTC_CR_TAMPOE | STM32_RTC_CR_OSEL; ++ ++ switch (pin) { ++ case OUT1: ++ if ((!(cr & STM32_RTC_CR_OUT2EN) && ++ ((cr & calib) || cr & tampalrm)) || ++ ((cr & calib) && (cr & tampalrm))) ++ return -EBUSY; ++ break; ++ case OUT2_RMP: ++ if ((cr & STM32_RTC_CR_OUT2EN) && ++ (cfgr & STM32_RTC_CFGR_OUT2_RMP) && ++ ((cr & calib) || (cr & tampalrm))) ++ return -EBUSY; ++ break; ++ default: ++ return -EINVAL; ++ } ++ ++ if (clk_get_rate(rtc->rtc_ck) != 32768) ++ return -ERANGE; ++ ++ return 0; ++} ++ ++static int stm32_rtc_pinmux_action_lsco(struct pinctrl_dev *pctldev, unsigned int pin) ++{ ++ struct stm32_rtc *rtc = pinctrl_dev_get_drvdata(pctldev); ++ struct stm32_rtc_registers regs = rtc->data->regs; ++ struct device *dev = rtc->rtc_dev->dev.parent; ++ u8 lscoen; ++ int ret; ++ ++ if (!rtc->data->has_lsco) ++ return -EPERM; ++ ++ ret = stm32_rtc_pinmux_lsco_available(pctldev, pin); ++ if (ret) ++ return ret; ++ ++ lscoen = (pin == OUT1) ? STM32_RTC_CFGR_LSCOEN_OUT1 : STM32_RTC_CFGR_LSCOEN_OUT2_RMP; ++ ++ rtc->clk_lsco = clk_register_gate(dev, "rtc_lsco", __clk_get_name(rtc->rtc_ck), ++ CLK_IGNORE_UNUSED | CLK_IS_CRITICAL, ++ rtc->base + regs.cfgr, lscoen, 0, NULL); ++ if (IS_ERR(rtc->clk_lsco)) ++ return PTR_ERR(rtc->clk_lsco); ++ ++ of_clk_add_provider(dev->of_node, of_clk_src_simple_get, rtc->clk_lsco); ++ ++ return 0; ++} ++ + static const struct stm32_rtc_pinmux_func stm32_rtc_pinmux_functions[] = { ++ STM32_RTC_PINMUX("lsco", &stm32_rtc_pinmux_action_lsco, "out1", "out2_rmp"), + }; + + static int stm32_rtc_pinmux_get_functions_count(struct pinctrl_dev *pctldev) +@@ -664,6 +739,7 @@ static const struct stm32_rtc_data stm32 + .has_pclk = false, + .need_dbp = true, + .need_accuracy = false, ++ .has_lsco = false, + .regs = { + .tr = 0x00, + .dr = 0x04, +@@ -674,6 +750,7 @@ static const struct stm32_rtc_data stm32 + .wpr = 0x24, + .sr = 0x0C, /* set to ISR offset to ease alarm management */ + .scr = UNDEF_REG, ++ .cfgr = UNDEF_REG, + .verr = UNDEF_REG, + }, + .events = { +@@ -686,6 +763,7 @@ static const struct stm32_rtc_data stm32 + .has_pclk = true, + .need_dbp = true, + .need_accuracy = false, ++ .has_lsco = false, + .regs = { + .tr = 0x00, + .dr = 0x04, +@@ -696,6 +774,7 @@ static const struct stm32_rtc_data stm32 + .wpr = 0x24, + .sr = 0x0C, /* set to ISR offset to ease alarm management */ + .scr = UNDEF_REG, ++ .cfgr = UNDEF_REG, + .verr = UNDEF_REG, + }, + .events = { +@@ -717,6 +796,7 @@ static const struct stm32_rtc_data stm32 + .has_pclk = true, + .need_dbp = false, + .need_accuracy = true, ++ .has_lsco = true, + .regs = { + .tr = 0x00, + .dr = 0x04, +@@ -727,6 +807,7 @@ static const struct stm32_rtc_data stm32 + .wpr = 0x24, + .sr = 0x50, + .scr = 0x5C, ++ .cfgr = 0x60, + .verr = 0x3F4, + }, + .events = { +@@ -743,6 +824,19 @@ static const struct of_device_id stm32_r + }; + MODULE_DEVICE_TABLE(of, stm32_rtc_of_match); + ++static void stm32_rtc_clean_outs(struct stm32_rtc *rtc) ++{ ++ struct stm32_rtc_registers regs = rtc->data->regs; ++ ++ if (regs.cfgr != UNDEF_REG) { ++ unsigned int cfgr = readl_relaxed(rtc->base + regs.cfgr); ++ ++ cfgr &= ~STM32_RTC_CFGR_LSCOEN; ++ cfgr &= ~STM32_RTC_CFGR_OUT2_RMP; ++ writel_relaxed(cfgr, rtc->base + regs.cfgr); ++ } ++} ++ + static int stm32_rtc_init(struct platform_device *pdev, + struct stm32_rtc *rtc) + { +@@ -946,6 +1040,8 @@ static int stm32_rtc_probe(struct platfo + goto err; + } + ++ stm32_rtc_clean_outs(rtc); ++ + ret = devm_pinctrl_register_and_init(&pdev->dev, &stm32_rtc_pdesc, rtc, &pctl); + if (ret) + return dev_err_probe(&pdev->dev, ret, "pinctrl register failed"); +@@ -992,6 +1088,9 @@ static void stm32_rtc_remove(struct plat + const struct stm32_rtc_registers *regs = &rtc->data->regs; + unsigned int cr; + ++ if (!IS_ERR_OR_NULL(rtc->clk_lsco)) ++ clk_unregister_gate(rtc->clk_lsco); ++ + /* Disable interrupts */ + stm32_rtc_wpr_unlock(rtc); + cr = readl_relaxed(rtc->base + regs->cr); diff --git a/target/linux/stm32/patches-6.6/032-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch b/target/linux/stm32/patches-6.6/032-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch new file mode 100644 index 00000000000..1d5bedbad37 --- /dev/null +++ b/target/linux/stm32/patches-6.6/032-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch @@ -0,0 +1,31 @@ +From 92483a156238078562d187f527de6b358cb53a08 Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Tue, 27 Aug 2024 16:04:48 +0200 +Subject: [PATCH] ARM: dts: stm32: rtc, add pin to provide LSCO on + stm32mp13 + +Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin +for RTC OUT2_RMP, in stm32mp13-pinctrl.dtsi. + +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp13-pinctrl.dtsi +@@ -212,6 +212,13 @@ + }; + }; + ++ /omit-if-no-ref/ ++ rtc_rsvd_pins_a: rtc-rsvd-0 { ++ pins { ++ pinmux = ; /* RTC_OUT2_RMP */ ++ }; ++ }; ++ + sdmmc1_b4_pins_a: sdmmc1-b4-0 { + pins { + pinmux = , /* SDMMC1_D0 */ diff --git a/target/linux/stm32/patches-6.6/033-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch b/target/linux/stm32/patches-6.6/033-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch new file mode 100644 index 00000000000..ec6a086a7d0 --- /dev/null +++ b/target/linux/stm32/patches-6.6/033-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch @@ -0,0 +1,34 @@ +From d6e424f926397e682fc44a952d5b3a1e34b2cd73 Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Tue, 27 Aug 2024 16:04:50 +0200 +Subject: [PATCH] ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on + stm32mp135f-dk + +On stm32mp135f-dk board, WLAN/BT module LPO_IN pin is wired to +RTC OUT2_RMP pin. + +Provide a pinctrl configuration to enable LSCO on OUT2_RMP. + +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp135f-dk.dts | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts ++++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts +@@ -184,7 +184,14 @@ + }; + + &rtc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_rsvd_pins_a>; + status = "okay"; ++ ++ rtc_lsco_pins_a: rtc-lsco-0 { ++ pins = "out2_rmp"; ++ function = "lsco"; ++ }; + }; + + &scmi_regu { diff --git a/target/linux/stm32/patches-6.6/034-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp135f-.patch b/target/linux/stm32/patches-6.6/034-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp135f-.patch new file mode 100644 index 00000000000..e2b69ac8c77 --- /dev/null +++ b/target/linux/stm32/patches-6.6/034-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp135f-.patch @@ -0,0 +1,84 @@ +From 6b44fdef4c7ad112e17d7cbd64d7d522a426d6e4 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Tue, 27 Aug 2024 16:04:52 +0200 +Subject: [PATCH] ARM: dts: stm32: add support of WLAN/BT on stm32mp135f-dk + +Add support of WLAN/BT Murata Type 1DX module: +- usart2 is used for Bluetooth interface +- sdmmc2 is used for WLAN (sdio) interface + +Signed-off-by: Christophe Roullier +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp135f-dk.dts | 45 +++++++++++++++++++++++++ + 1 file changed, 45 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts ++++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts +@@ -67,6 +67,19 @@ + default-state = "off"; + }; + }; ++ ++ v3v3_ao: v3v3-ao { ++ compatible = "regulator-fixed"; ++ regulator-name = "v3v3_ao"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&mcp23017 11 GPIO_ACTIVE_LOW>; ++ }; + }; + + &adc_1 { +@@ -230,6 +243,30 @@ + status = "okay"; + }; + ++/* Wifi */ ++&sdmmc2 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_clk_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_clk_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; ++ non-removable; ++ cap-sdio-irq; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3_ao>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_lsco_pins_a>; ++ }; ++}; ++ + &spi5 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&spi5_pins_a>; +@@ -332,6 +369,14 @@ + pinctrl-2 = <&usart2_idle_pins_a>; + uart-has-rtscts; + status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&mcp23017 13 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3_ao>; ++ vddio-supply = <&v3v3_ao>; ++ }; + }; + + &usbh_ehci { diff --git a/target/linux/stm32/patches-6.6/035-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch b/target/linux/stm32/patches-6.6/035-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch new file mode 100644 index 00000000000..2e8d7010eeb --- /dev/null +++ b/target/linux/stm32/patches-6.6/035-ARM-dts-stm32-rtc-add-pin-to-provide-LSCO-on-stm32mp.patch @@ -0,0 +1,30 @@ +From d6b0d7a941c4fc9241d9cca66db5d8ff9d81cc8b Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Tue, 27 Aug 2024 16:04:47 +0200 +Subject: [PATCH] ARM: dts: stm32: rtc, add pin to provide LSCO on stm32mp15 + +Declare pin for LSCO in stm32-pinctrl provider node to reserve this pin +for RTC OUT2_RMP, in stm32mp15-pinctrl.dtsi. + +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 7 +++++++ + 1 file changed, 7 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +@@ -1467,6 +1467,13 @@ + }; + }; + ++ /omit-if-no-ref/ ++ rtc_rsvd_pins_a: rtc-rsvd-0 { ++ pins { ++ pinmux = ; /* RTC_OUT2_RMP */ ++ }; ++ }; ++ + sai2a_pins_a: sai2a-0 { + pins { + pinmux = , /* SAI2_SCK_A */ diff --git a/target/linux/stm32/patches-6.6/036-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch b/target/linux/stm32/patches-6.6/036-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch new file mode 100644 index 00000000000..338f61be0d6 --- /dev/null +++ b/target/linux/stm32/patches-6.6/036-ARM-dts-stm32-rtc-add-LSCO-to-WLAN-BT-module-on-stm3.patch @@ -0,0 +1,36 @@ +From c24e7ae60d3e97799998466a4220ef6ffa0e4c94 Mon Sep 17 00:00:00 2001 +From: Valentin Caron +Date: Tue, 27 Aug 2024 16:04:49 +0200 +Subject: [PATCH] ARM: dts: stm32: rtc, add LSCO to WLAN/BT module on + stm32mp157c-dk2 + +On stm32mp157c-dk2 board, WLAN/BT module LPO_IN pin is wired to +RTC OUT2_RMP pin. + +Provide a pinctrl configuration to enable LSCO on OUT2_RMP. + +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +@@ -84,6 +84,16 @@ + }; + }; + ++&rtc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_rsvd_pins_a>; ++ ++ rtc_lsco_pins_a: rtc-lsco-0 { ++ pins = "out2_rmp"; ++ function = "lsco"; ++ }; ++}; ++ + &usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; diff --git a/target/linux/stm32/patches-6.6/037-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp157c-.patch b/target/linux/stm32/patches-6.6/037-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp157c-.patch new file mode 100644 index 00000000000..50e2fbcae20 --- /dev/null +++ b/target/linux/stm32/patches-6.6/037-ARM-dts-stm32-add-support-of-WLAN-BT-on-stm32mp157c-.patch @@ -0,0 +1,76 @@ +From 315fe7667c03c1f853e1a7038c28f23621a44a3d Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Tue, 27 Aug 2024 16:04:51 +0200 +Subject: [PATCH] ARM: dts: stm32: add support of WLAN/BT on stm32mp157c-dk2 + +Add support of WLAN/BT Murata Type 1DX module: +- usart2 is used for Bluetooth interface +- sdmmc2 is used for WLAN (sdio) interface + +Signed-off-by: Christophe Roullier +Signed-off-by: Valentin Caron +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp157c-dk2.dts | 41 +++++++++++++++++++++++- + 1 file changed, 40 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/st/stm32mp157c-dk2.dts ++++ b/arch/arm/boot/dts/st/stm32mp157c-dk2.dts +@@ -24,6 +24,11 @@ + chosen { + stdout-path = "serial0:115200n8"; + }; ++ ++ wifi_pwrseq: wifi-pwrseq { ++ compatible = "mmc-pwrseq-simple"; ++ reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>; ++ }; + }; + + &cryp1 { +@@ -94,10 +99,44 @@ + }; + }; + ++/* Wifi */ ++&sdmmc2 { ++ pinctrl-names = "default", "opendrain", "sleep"; ++ pinctrl-0 = <&sdmmc2_b4_pins_a>; ++ pinctrl-1 = <&sdmmc2_b4_od_pins_a>; ++ pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>; ++ non-removable; ++ cap-sdio-irq; ++ st,neg-edge; ++ bus-width = <4>; ++ vmmc-supply = <&v3v3>; ++ mmc-pwrseq = <&wifi_pwrseq>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "okay"; ++ ++ brcmf: bcrmf@1 { ++ reg = <1>; ++ compatible = "brcm,bcm4329-fmac"; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&rtc_lsco_pins_a>; ++ }; ++}; ++ ++/* Bluetooth */ + &usart2 { + pinctrl-names = "default", "sleep", "idle"; + pinctrl-0 = <&usart2_pins_c>; + pinctrl-1 = <&usart2_sleep_pins_c>; + pinctrl-2 = <&usart2_idle_pins_c>; +- status = "disabled"; ++ uart-has-rtscts; ++ status = "okay"; ++ ++ bluetooth { ++ shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>; ++ compatible = "brcm,bcm43438-bt"; ++ max-speed = <3000000>; ++ vbat-supply = <&v3v3>; ++ vddio-supply = <&v3v3>; ++ }; + }; diff --git a/target/linux/stm32/patches-6.6/040-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch b/target/linux/stm32/patches-6.6/040-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch new file mode 100644 index 00000000000..543ca1a8e3f --- /dev/null +++ b/target/linux/stm32/patches-6.6/040-ARM-dts-stm32-add-ETZPC-as-a-system-bus-for-STM32MP1.patch @@ -0,0 +1,2974 @@ +From ad95b569993b0735a58b08c00cd4131fa5e83376 Mon Sep 17 00:00:00 2001 +From: Gatien Chevallier +Date: Fri, 5 Jan 2024 14:04:01 +0100 +Subject: [PATCH] ARM: dts: stm32: add ETZPC as a system bus for STM32MP15x + boards + +ETZPC is a firewall controller. Put all peripherals filtered by the +ETZPC as ETZPC subnodes and keep the "simple-bus" compatible for +backward compatibility. + +Signed-off-by: Gatien Chevallier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp151.dtsi | 2676 +++++++++++++------------ + arch/arm/boot/dts/st/stm32mp153.dtsi | 50 +- + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 18 +- + 3 files changed, 1375 insertions(+), 1369 deletions(-) + +--- a/arch/arm/boot/dts/st/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi +@@ -123,1541 +123,1549 @@ + interrupt-parent = <&intc>; + ranges; + +- timers2: timer@40000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40000000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM2_K>; +- clock-names = "int"; +- dmas = <&dmamux1 18 0x400 0x1>, +- <&dmamux1 19 0x400 0x1>, +- <&dmamux1 20 0x400 0x1>, +- <&dmamux1 21 0x400 0x1>, +- <&dmamux1 22 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up"; ++ ipcc: mailbox@4c001000 { ++ compatible = "st,stm32mp1-ipcc"; ++ #mbox-cells = <1>; ++ reg = <0x4c001000 0x400>; ++ st,proc-id = <0>; ++ interrupts-extended = ++ <&exti 61 IRQ_TYPE_LEVEL_HIGH>, ++ <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "rx", "tx"; ++ clocks = <&rcc IPCC>; ++ wakeup-source; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@1 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <1>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; + }; + +- timers3: timer@40001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40001000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM3_K>; +- clock-names = "int"; +- dmas = <&dmamux1 23 0x400 0x1>, +- <&dmamux1 24 0x400 0x1>, +- <&dmamux1 25 0x400 0x1>, +- <&dmamux1 26 0x400 0x1>, +- <&dmamux1 27 0x400 0x1>, +- <&dmamux1 28 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@2 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <2>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; ++ rcc: rcc@50000000 { ++ compatible = "st,stm32mp1-rcc", "syscon"; ++ reg = <0x50000000 0x1000>; ++ #clock-cells = <1>; ++ #reset-cells = <1>; + }; + +- timers4: timer@40002000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40002000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM4_K>; +- clock-names = "int"; +- dmas = <&dmamux1 29 0x400 0x1>, +- <&dmamux1 30 0x400 0x1>, +- <&dmamux1 31 0x400 0x1>, +- <&dmamux1 32 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4"; +- status = "disabled"; ++ pwr_regulators: pwr@50001000 { ++ compatible = "st,stm32mp1,pwr-reg"; ++ reg = <0x50001000 0x10>; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; ++ reg11: reg11 { ++ regulator-name = "reg11"; ++ regulator-min-microvolt = <1100000>; ++ regulator-max-microvolt = <1100000>; + }; + +- timer@3 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <3>; +- status = "disabled"; ++ reg18: reg18 { ++ regulator-name = "reg18"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; + }; + +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; ++ usb33: usb33 { ++ regulator-name = "usb33"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; + }; + }; + +- timers5: timer@40003000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40003000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM5_K>; +- clock-names = "int"; +- dmas = <&dmamux1 55 0x400 0x1>, +- <&dmamux1 56 0x400 0x1>, +- <&dmamux1 57 0x400 0x1>, +- <&dmamux1 58 0x400 0x1>, +- <&dmamux1 59 0x400 0x1>, +- <&dmamux1 60 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@4 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <4>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-timer-counter"; +- status = "disabled"; +- }; ++ pwr_mcu: pwr_mcu@50001014 { ++ compatible = "st,stm32mp151-pwr-mcu", "syscon"; ++ reg = <0x50001014 0x4>; + }; + +- timers6: timer@40004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40004000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM6_K>; +- clock-names = "int"; +- dmas = <&dmamux1 69 0x400 0x1>; +- dma-names = "up"; +- status = "disabled"; +- +- timer@5 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <5>; +- status = "disabled"; +- }; ++ exti: interrupt-controller@5000d000 { ++ compatible = "st,stm32mp1-exti", "syscon"; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ reg = <0x5000d000 0x400>; + }; + +- timers7: timer@40005000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40005000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM7_K>; +- clock-names = "int"; +- dmas = <&dmamux1 70 0x400 0x1>; +- dma-names = "up"; +- status = "disabled"; +- +- timer@6 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <6>; +- status = "disabled"; +- }; ++ syscfg: syscon@50020000 { ++ compatible = "st,stm32mp157-syscfg", "syscon"; ++ reg = <0x50020000 0x400>; ++ clocks = <&rcc SYSCFG>; + }; + +- timers12: timer@40006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40006000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM12_K>; +- clock-names = "int"; ++ dts: thermal@50028000 { ++ compatible = "st,stm32-thermal"; ++ reg = <0x50028000 0x100>; ++ interrupts = ; ++ clocks = <&rcc TMPSENS>; ++ clock-names = "pclk"; ++ #thermal-sensor-cells = <0>; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@11 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <11>; +- status = "disabled"; +- }; + }; + +- timers13: timer@40007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40007000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM13_K>; +- clock-names = "int"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@12 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <12>; +- status = "disabled"; +- }; ++ mdma1: dma-controller@58000000 { ++ compatible = "st,stm32h7-mdma"; ++ reg = <0x58000000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc MDMA>; ++ resets = <&rcc MDMA_R>; ++ #dma-cells = <5>; ++ dma-channels = <32>; ++ dma-requests = <48>; + }; + +- timers14: timer@40008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x40008000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM14_K>; +- clock-names = "int"; ++ sdmmc1: mmc@58005000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x00253180>; ++ reg = <0x58005000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc SDMMC1_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC1_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <120000000>; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- timer@13 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <13>; +- status = "disabled"; +- }; + }; + +- lptimer1: timer@40009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x40009000 0x400>; +- interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM1_K>; +- clock-names = "mux"; +- wakeup-source; ++ sdmmc2: mmc@58007000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x00253180>; ++ reg = <0x58007000 0x1000>; ++ interrupts = ; ++ clocks = <&rcc SDMMC2_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC2_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <120000000>; + status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- +- trigger@0 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <0>; +- status = "disabled"; +- }; +- +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; + }; + +- spi2: spi@4000b000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI2_K>; +- resets = <&rcc SPI2_R>; +- dmas = <&dmamux1 39 0x400 0x05>, +- <&dmamux1 40 0x400 0x05>; +- dma-names = "rx", "tx"; ++ crc1: crc@58009000 { ++ compatible = "st,stm32f7-crc"; ++ reg = <0x58009000 0x400>; ++ clocks = <&rcc CRC1>; + status = "disabled"; + }; + +- i2s2: audio-controller@4000b000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000b000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 39 0x400 0x01>, +- <&dmamux1 40 0x400 0x01>; +- dma-names = "rx", "tx"; ++ usbh_ohci: usb@5800c000 { ++ compatible = "generic-ohci"; ++ reg = <0x5800c000 0x1000>; ++ clocks = <&usbphyc>, <&rcc USBH>; ++ resets = <&rcc USBH_R>; ++ interrupts = ; + status = "disabled"; + }; + +- spi3: spi@4000c000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI3_K>; +- resets = <&rcc SPI3_R>; +- dmas = <&dmamux1 61 0x400 0x05>, +- <&dmamux1 62 0x400 0x05>; +- dma-names = "rx", "tx"; ++ usbh_ehci: usb@5800d000 { ++ compatible = "generic-ehci"; ++ reg = <0x5800d000 0x1000>; ++ clocks = <&usbphyc>, <&rcc USBH>; ++ resets = <&rcc USBH_R>; ++ interrupts = ; ++ companion = <&usbh_ohci>; + status = "disabled"; + }; + +- i2s3: audio-controller@4000c000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x4000c000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 61 0x400 0x01>, +- <&dmamux1 62 0x400 0x01>; +- dma-names = "rx", "tx"; ++ ltdc: display-controller@5a001000 { ++ compatible = "st,stm32-ltdc"; ++ reg = <0x5a001000 0x400>; ++ interrupts = , ++ ; ++ clocks = <&rcc LTDC_PX>; ++ clock-names = "lcd"; ++ resets = <&rcc LTDC_R>; + status = "disabled"; + }; + +- spdifrx: audio-controller@4000d000 { +- compatible = "st,stm32h7-spdifrx"; +- #sound-dai-cells = <0>; +- reg = <0x4000d000 0x400>; +- clocks = <&rcc SPDIF_K>; +- clock-names = "kclk"; +- interrupts = ; +- dmas = <&dmamux1 93 0x400 0x01>, +- <&dmamux1 94 0x400 0x01>; +- dma-names = "rx", "rx-ctrl"; ++ iwdg2: watchdog@5a002000 { ++ compatible = "st,stm32mp1-iwdg"; ++ reg = <0x5a002000 0x400>; ++ clocks = <&rcc IWDG2>, <&rcc CK_LSI>; ++ clock-names = "pclk", "lsi"; + status = "disabled"; + }; + +- usart2: serial@4000e000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4000e000 0x400>; +- interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART2_K>; +- wakeup-source; +- dmas = <&dmamux1 43 0x400 0x15>, +- <&dmamux1 44 0x400 0x11>; +- dma-names = "rx", "tx"; ++ usbphyc: usbphyc@5a006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ #clock-cells = <0>; ++ compatible = "st,stm32mp1-usbphyc"; ++ reg = <0x5a006000 0x1000>; ++ clocks = <&rcc USBPHY_K>; ++ resets = <&rcc USBPHY_R>; ++ vdda1v1-supply = <®11>; ++ vdda1v8-supply = <®18>; + status = "disabled"; +- }; + +- usart3: serial@4000f000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x4000f000 0x400>; +- interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART3_K>; +- wakeup-source; +- dmas = <&dmamux1 45 0x400 0x15>, +- <&dmamux1 46 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ usbphyc_port0: usb-phy@0 { ++ #phy-cells = <0>; ++ reg = <0>; ++ }; + +- uart4: serial@40010000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40010000 0x400>; +- interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART4_K>; +- wakeup-source; +- dmas = <&dmamux1 63 0x400 0x15>, +- <&dmamux1 64 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; ++ usbphyc_port1: usb-phy@1 { ++ #phy-cells = <1>; ++ reg = <1>; ++ }; + }; + +- uart5: serial@40011000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40011000 0x400>; +- interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART5_K>; +- wakeup-source; +- dmas = <&dmamux1 65 0x400 0x15>, +- <&dmamux1 66 0x400 0x11>; +- dma-names = "rx", "tx"; ++ rtc: rtc@5c004000 { ++ compatible = "st,stm32mp1-rtc"; ++ reg = <0x5c004000 0x400>; ++ clocks = <&rcc RTCAPB>, <&rcc RTC>; ++ clock-names = "pclk", "rtc_ck"; ++ interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + +- i2c1: i2c@40012000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40012000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C1_K>; +- resets = <&rcc I2C1_R>; ++ bsec: efuse@5c005000 { ++ compatible = "st,stm32mp15-bsec"; ++ reg = <0x5c005000 0x400>; + #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x1>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; ++ #size-cells = <1>; ++ part_number_otp: part-number-otp@4 { ++ reg = <0x4 0x1>; ++ }; ++ vrefint: vrefin-cal@52 { ++ reg = <0x52 0x2>; ++ }; ++ ts_cal1: calib@5c { ++ reg = <0x5c 0x2>; ++ }; ++ ts_cal2: calib@5e { ++ reg = <0x5e 0x2>; ++ }; + }; + +- i2c2: i2c@40013000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40013000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C2_K>; +- resets = <&rcc I2C2_R>; ++ etzpc: bus@5c007000 { ++ compatible = "simple-bus"; ++ reg = <0x5c007000 0x400>; + #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x2>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ #size-cells = <1>; ++ ranges; + +- i2c3: i2c@40014000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40014000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C3_K>; +- resets = <&rcc I2C3_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x4>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ timers2: timer@40000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40000000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM2_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 18 0x400 0x1>, ++ <&dmamux1 19 0x400 0x1>, ++ <&dmamux1 20 0x400 0x1>, ++ <&dmamux1 21 0x400 0x1>, ++ <&dmamux1 22 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", "up"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- i2c5: i2c@40015000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x40015000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C5_K>; +- resets = <&rcc I2C5_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x10>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ timer@1 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <1>; ++ status = "disabled"; ++ }; + +- cec: cec@40016000 { +- compatible = "st,stm32-cec"; +- reg = <0x40016000 0x400>; +- interrupts = ; +- clocks = <&rcc CEC_K>, <&rcc CEC>; +- clock-names = "cec", "hdmi-cec"; +- status = "disabled"; +- }; ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; ++ }; + +- dac: dac@40017000 { +- compatible = "st,stm32h7-dac-core"; +- reg = <0x40017000 0x400>; +- clocks = <&rcc DAC12>; +- clock-names = "pclk"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; ++ timers3: timer@40001000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40001000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM3_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 23 0x400 0x1>, ++ <&dmamux1 24 0x400 0x1>, ++ <&dmamux1 25 0x400 0x1>, ++ <&dmamux1 26 0x400 0x1>, ++ <&dmamux1 27 0x400 0x1>, ++ <&dmamux1 28 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- dac1: dac@1 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <1>; +- status = "disabled"; ++ timer@2 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; + +- dac2: dac@2 { +- compatible = "st,stm32-dac"; +- #io-channel-cells = <1>; +- reg = <2>; +- status = "disabled"; ++ timers4: timer@40002000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40002000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM4_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 29 0x400 0x1>, ++ <&dmamux1 30 0x400 0x1>, ++ <&dmamux1 31 0x400 0x1>, ++ <&dmamux1 32 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@3 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <3>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; +- }; + +- uart7: serial@40018000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40018000 0x400>; +- interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART7_K>; +- wakeup-source; +- dmas = <&dmamux1 79 0x400 0x15>, +- <&dmamux1 80 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ timers5: timer@40003000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40003000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM5_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 55 0x400 0x1>, ++ <&dmamux1 56 0x400 0x1>, ++ <&dmamux1 57 0x400 0x1>, ++ <&dmamux1 58 0x400 0x1>, ++ <&dmamux1 59 0x400 0x1>, ++ <&dmamux1 60 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- uart8: serial@40019000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x40019000 0x400>; +- interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc UART8_K>; +- wakeup-source; +- dmas = <&dmamux1 81 0x400 0x15>, +- <&dmamux1 82 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ timer@4 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <4>; ++ status = "disabled"; ++ }; + +- timers1: timer@44000000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44000000 0x400>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "brk", "up", "trg-com", "cc"; +- clocks = <&rcc TIM1_K>; +- clock-names = "int"; +- dmas = <&dmamux1 11 0x400 0x1>, +- <&dmamux1 12 0x400 0x1>, +- <&dmamux1 13 0x400 0x1>, +- <&dmamux1 14 0x400 0x1>, +- <&dmamux1 15 0x400 0x1>, +- <&dmamux1 16 0x400 0x1>, +- <&dmamux1 17 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", +- "up", "trig", "com"; +- status = "disabled"; ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; ++ }; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; ++ timers6: timer@40004000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40004000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM6_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 69 0x400 0x1>; ++ dma-names = "up"; + status = "disabled"; ++ ++ timer@5 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <5>; ++ status = "disabled"; ++ }; + }; + +- timer@0 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <0>; ++ timers7: timer@40005000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40005000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM7_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 70 0x400 0x1>; ++ dma-names = "up"; + status = "disabled"; ++ ++ timer@6 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <6>; ++ status = "disabled"; ++ }; + }; + +- counter { +- compatible = "st,stm32-timer-counter"; ++ timers12: timer@40006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40006000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM12_K>; ++ clock-names = "int"; + status = "disabled"; +- }; +- }; + +- timers8: timer@44001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44001000 0x400>; +- interrupts = , +- , +- , +- ; +- interrupt-names = "brk", "up", "trg-com", "cc"; +- clocks = <&rcc TIM8_K>; +- clock-names = "int"; +- dmas = <&dmamux1 47 0x400 0x1>, +- <&dmamux1 48 0x400 0x1>, +- <&dmamux1 49 0x400 0x1>, +- <&dmamux1 50 0x400 0x1>, +- <&dmamux1 51 0x400 0x1>, +- <&dmamux1 52 0x400 0x1>, +- <&dmamux1 53 0x400 0x1>; +- dma-names = "ch1", "ch2", "ch3", "ch4", +- "up", "trig", "com"; +- status = "disabled"; ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; ++ timer@11 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <11>; ++ status = "disabled"; ++ }; + }; + +- timer@7 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <7>; ++ timers13: timer@40007000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40007000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM13_K>; ++ clock-names = "int"; + status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@12 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <12>; ++ status = "disabled"; ++ }; + }; + +- counter { +- compatible = "st,stm32-timer-counter"; ++ timers14: timer@40008000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x40008000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM14_K>; ++ clock-names = "int"; + status = "disabled"; +- }; +- }; + +- usart6: serial@44003000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x44003000 0x400>; +- interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART6_K>; +- wakeup-source; +- dmas = <&dmamux1 71 0x400 0x15>, +- <&dmamux1 72 0x400 0x11>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- spi1: spi@44004000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44004000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI1_K>; +- resets = <&rcc SPI1_R>; +- dmas = <&dmamux1 37 0x400 0x05>, +- <&dmamux1 38 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ timer@13 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <13>; ++ status = "disabled"; ++ }; ++ }; + +- i2s1: audio-controller@44004000 { +- compatible = "st,stm32h7-i2s"; +- #sound-dai-cells = <0>; +- reg = <0x44004000 0x400>; +- interrupts = ; +- dmas = <&dmamux1 37 0x400 0x01>, +- <&dmamux1 38 0x400 0x01>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ lptimer1: timer@40009000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x40009000 0x400>; ++ interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM1_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; + +- spi4: spi@44005000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44005000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI4_K>; +- resets = <&rcc SPI4_R>; +- dmas = <&dmamux1 83 0x400 0x05>, +- <&dmamux1 84 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- timers15: timer@44006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44006000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM15_K>; +- clock-names = "int"; +- dmas = <&dmamux1 105 0x400 0x1>, +- <&dmamux1 106 0x400 0x1>, +- <&dmamux1 107 0x400 0x1>, +- <&dmamux1 108 0x400 0x1>; +- dma-names = "ch1", "up", "trig", "com"; +- status = "disabled"; ++ trigger@0 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <0>; ++ status = "disabled"; ++ }; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; ++ counter { ++ compatible = "st,stm32-lptimer-counter"; ++ status = "disabled"; ++ }; + }; + +- timer@14 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <14>; ++ i2s2: audio-controller@4000b000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x4000b000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 39 0x400 0x01>, ++ <&dmamux1 40 0x400 0x01>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; +- +- timers16: timer@44007000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44007000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM16_K>; +- clock-names = "int"; +- dmas = <&dmamux1 109 0x400 0x1>, +- <&dmamux1 110 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; + +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; +- status = "disabled"; +- }; +- timer@15 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <15>; ++ spi2: spi@4000b000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x4000b000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI2_K>; ++ resets = <&rcc SPI2_R>; ++ dmas = <&dmamux1 39 0x400 0x05>, ++ <&dmamux1 40 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- timers17: timer@44008000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-timers"; +- reg = <0x44008000 0x400>; +- interrupts = ; +- interrupt-names = "global"; +- clocks = <&rcc TIM17_K>; +- clock-names = "int"; +- dmas = <&dmamux1 111 0x400 0x1>, +- <&dmamux1 112 0x400 0x1>; +- dma-names = "ch1", "up"; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm"; +- #pwm-cells = <3>; ++ i2s3: audio-controller@4000c000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x4000c000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 61 0x400 0x01>, ++ <&dmamux1 62 0x400 0x01>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- timer@16 { +- compatible = "st,stm32h7-timer-trigger"; +- reg = <16>; ++ spi3: spi@4000c000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x4000c000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI3_K>; ++ resets = <&rcc SPI3_R>; ++ dmas = <&dmamux1 61 0x400 0x05>, ++ <&dmamux1 62 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- spi5: spi@44009000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x44009000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI5_K>; +- resets = <&rcc SPI5_R>; +- dmas = <&dmamux1 85 0x400 0x05>, +- <&dmamux1 86 0x400 0x05>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; +- +- sai1: sai@4400a000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400a000 0x400>; +- reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI1_R>; +- status = "disabled"; +- +- sai1a: audio-controller@4400a004 { ++ spdifrx: audio-controller@4000d000 { ++ compatible = "st,stm32h7-spdifrx"; + #sound-dai-cells = <0>; +- +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x20>; +- clocks = <&rcc SAI1_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 87 0x400 0x01>; ++ reg = <0x4000d000 0x400>; ++ clocks = <&rcc SPDIF_K>; ++ clock-names = "kclk"; ++ interrupts = ; ++ dmas = <&dmamux1 93 0x400 0x01>, ++ <&dmamux1 94 0x400 0x01>; ++ dma-names = "rx", "rx-ctrl"; ++ status = "disabled"; ++ }; ++ ++ usart2: serial@4000e000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x4000e000 0x400>; ++ interrupts-extended = <&exti 27 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART2_K>; ++ wakeup-source; ++ dmas = <&dmamux1 43 0x400 0x15>, ++ <&dmamux1 44 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ usart3: serial@4000f000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x4000f000 0x400>; ++ interrupts-extended = <&exti 28 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART3_K>; ++ wakeup-source; ++ dmas = <&dmamux1 45 0x400 0x15>, ++ <&dmamux1 46 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ uart4: serial@40010000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40010000 0x400>; ++ interrupts-extended = <&exti 30 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART4_K>; ++ wakeup-source; ++ dmas = <&dmamux1 63 0x400 0x15>, ++ <&dmamux1 64 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ uart5: serial@40011000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40011000 0x400>; ++ interrupts-extended = <&exti 31 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART5_K>; ++ wakeup-source; ++ dmas = <&dmamux1 65 0x400 0x15>, ++ <&dmamux1 66 0x400 0x11>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; ++ }; ++ ++ i2c1: i2c@40012000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40012000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C1_K>; ++ resets = <&rcc I2C1_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x1>; ++ wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +- sai1b: audio-controller@4400a024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI1_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 88 0x400 0x01>; ++ i2c2: i2c@40013000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40013000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C2_K>; ++ resets = <&rcc I2C2_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x2>; ++ wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; +- }; + +- sai2: sai@4400b000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400b000 0x400>; +- reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI2_R>; +- status = "disabled"; ++ i2c3: i2c@40014000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40014000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C3_K>; ++ resets = <&rcc I2C3_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x4>; ++ wakeup-source; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; + +- sai2a: audio-controller@4400b004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x4 0x20>; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 89 0x400 0x01>; ++ i2c5: i2c@40015000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x40015000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C5_K>; ++ resets = <&rcc I2C5_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x10>; ++ wakeup-source; ++ i2c-analog-filter; + status = "disabled"; + }; + +- sai2b: audio-controller@4400b024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI2_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 90 0x400 0x01>; ++ cec: cec@40016000 { ++ compatible = "st,stm32-cec"; ++ reg = <0x40016000 0x400>; ++ interrupts = ; ++ clocks = <&rcc CEC_K>, <&rcc CEC>; ++ clock-names = "cec", "hdmi-cec"; + status = "disabled"; + }; +- }; + +- sai3: sai@4400c000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x4400c000 0x400>; +- reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI3_R>; +- status = "disabled"; ++ dac: dac@40017000 { ++ compatible = "st,stm32h7-dac-core"; ++ reg = <0x40017000 0x400>; ++ clocks = <&rcc DAC12>; ++ clock-names = "pclk"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; + +- sai3a: audio-controller@4400c004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x20>; +- clocks = <&rcc SAI3_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 113 0x400 0x01>; ++ dac1: dac@1 { ++ compatible = "st,stm32-dac"; ++ #io-channel-cells = <1>; ++ reg = <1>; ++ status = "disabled"; ++ }; ++ ++ dac2: dac@2 { ++ compatible = "st,stm32-dac"; ++ #io-channel-cells = <1>; ++ reg = <2>; ++ status = "disabled"; ++ }; ++ }; ++ ++ uart7: serial@40018000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40018000 0x400>; ++ interrupts-extended = <&exti 32 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART7_K>; ++ wakeup-source; ++ dmas = <&dmamux1 79 0x400 0x15>, ++ <&dmamux1 80 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- sai3b: audio-controller@4400c024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI3_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 114 0x400 0x01>; ++ uart8: serial@40019000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x40019000 0x400>; ++ interrupts-extended = <&exti 33 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc UART8_K>; ++ wakeup-source; ++ dmas = <&dmamux1 81 0x400 0x15>, ++ <&dmamux1 82 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- dfsdm: dfsdm@4400d000 { +- compatible = "st,stm32mp1-dfsdm"; +- reg = <0x4400d000 0x800>; +- clocks = <&rcc DFSDM_K>; +- clock-names = "dfsdm"; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; ++ timers1: timer@44000000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44000000 0x400>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "brk", "up", "trg-com", "cc"; ++ clocks = <&rcc TIM1_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 11 0x400 0x1>, ++ <&dmamux1 12 0x400 0x1>, ++ <&dmamux1 13 0x400 0x1>, ++ <&dmamux1 14 0x400 0x1>, ++ <&dmamux1 15 0x400 0x1>, ++ <&dmamux1 16 0x400 0x1>, ++ <&dmamux1 17 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", ++ "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- dfsdm0: filter@0 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <0>; +- interrupts = ; +- dmas = <&dmamux1 101 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; ++ timer@0 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <0>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; + +- dfsdm1: filter@1 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <1>; +- interrupts = ; +- dmas = <&dmamux1 102 0x400 0x01>; +- dma-names = "rx"; +- status = "disabled"; ++ timers8: timer@44001000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44001000 0x400>; ++ interrupts = , ++ , ++ , ++ ; ++ interrupt-names = "brk", "up", "trg-com", "cc"; ++ clocks = <&rcc TIM8_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 47 0x400 0x1>, ++ <&dmamux1 48 0x400 0x1>, ++ <&dmamux1 49 0x400 0x1>, ++ <&dmamux1 50 0x400 0x1>, ++ <&dmamux1 51 0x400 0x1>, ++ <&dmamux1 52 0x400 0x1>, ++ <&dmamux1 53 0x400 0x1>; ++ dma-names = "ch1", "ch2", "ch3", "ch4", ++ "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@7 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <7>; ++ status = "disabled"; ++ }; ++ ++ counter { ++ compatible = "st,stm32-timer-counter"; ++ status = "disabled"; ++ }; + }; + +- dfsdm2: filter@2 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <2>; +- interrupts = ; +- dmas = <&dmamux1 103 0x400 0x01>; +- dma-names = "rx"; ++ usart6: serial@44003000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x44003000 0x400>; ++ interrupts-extended = <&exti 29 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART6_K>; ++ wakeup-source; ++ dmas = <&dmamux1 71 0x400 0x15>, ++ <&dmamux1 72 0x400 0x11>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- dfsdm3: filter@3 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <3>; +- interrupts = ; +- dmas = <&dmamux1 104 0x400 0x01>; +- dma-names = "rx"; ++ i2s1: audio-controller@44004000 { ++ compatible = "st,stm32h7-i2s"; ++ #sound-dai-cells = <0>; ++ reg = <0x44004000 0x400>; ++ interrupts = ; ++ dmas = <&dmamux1 37 0x400 0x01>, ++ <&dmamux1 38 0x400 0x01>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- dfsdm4: filter@4 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <4>; +- interrupts = ; +- dmas = <&dmamux1 91 0x400 0x01>; +- dma-names = "rx"; ++ spi1: spi@44004000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x44004000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI1_K>; ++ resets = <&rcc SPI1_R>; ++ dmas = <&dmamux1 37 0x400 0x05>, ++ <&dmamux1 38 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; + +- dfsdm5: filter@5 { +- compatible = "st,stm32-dfsdm-adc"; +- #io-channel-cells = <1>; +- reg = <5>; +- interrupts = ; +- dmas = <&dmamux1 92 0x400 0x01>; +- dma-names = "rx"; ++ spi4: spi@44005000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x44005000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI4_K>; ++ resets = <&rcc SPI4_R>; ++ dmas = <&dmamux1 83 0x400 0x05>, ++ <&dmamux1 84 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; + }; +- }; + +- dma1: dma-controller@48000000 { +- compatible = "st,stm32-dma"; +- reg = <0x48000000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&rcc DMA1>; +- resets = <&rcc DMA1_R>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- }; ++ timers15: timer@44006000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44006000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM15_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 105 0x400 0x1>, ++ <&dmamux1 106 0x400 0x1>, ++ <&dmamux1 107 0x400 0x1>, ++ <&dmamux1 108 0x400 0x1>; ++ dma-names = "ch1", "up", "trig", "com"; ++ status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- dma2: dma-controller@48001000 { +- compatible = "st,stm32-dma"; +- reg = <0x48001000 0x400>; +- interrupts = , +- , +- , +- , +- , +- , +- , +- ; +- clocks = <&rcc DMA2>; +- resets = <&rcc DMA2_R>; +- #dma-cells = <4>; +- st,mem2mem; +- dma-requests = <8>; +- }; ++ timer@14 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <14>; ++ status = "disabled"; ++ }; ++ }; + +- dmamux1: dma-router@48002000 { +- compatible = "st,stm32h7-dmamux"; +- reg = <0x48002000 0x40>; +- #dma-cells = <3>; +- dma-requests = <128>; +- dma-masters = <&dma1 &dma2>; +- dma-channels = <16>; +- clocks = <&rcc DMAMUX>; +- resets = <&rcc DMAMUX_R>; +- }; ++ timers16: timer@44007000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-timers"; ++ reg = <0x44007000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM16_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 109 0x400 0x1>, ++ <&dmamux1 110 0x400 0x1>; ++ dma-names = "ch1", "up"; ++ status = "disabled"; + +- adc: adc@48003000 { +- compatible = "st,stm32mp1-adc-core"; +- reg = <0x48003000 0x400>; +- interrupts = , +- ; +- clocks = <&rcc ADC12>, <&rcc ADC12_K>; +- clock-names = "bus", "adc"; +- interrupt-controller; +- st,syscfg = <&syscfg>; +- #interrupt-cells = <1>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ timer@15 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <15>; ++ status = "disabled"; ++ }; ++ }; + +- adc1: adc@0 { +- compatible = "st,stm32mp1-adc"; +- #io-channel-cells = <1>; ++ timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x0>; +- interrupt-parent = <&adc>; +- interrupts = <0>; +- dmas = <&dmamux1 9 0x400 0x01>; +- dma-names = "rx"; ++ compatible = "st,stm32-timers"; ++ reg = <0x44008000 0x400>; ++ interrupts = ; ++ interrupt-names = "global"; ++ clocks = <&rcc TIM17_K>; ++ clock-names = "int"; ++ dmas = <&dmamux1 111 0x400 0x1>, ++ <&dmamux1 112 0x400 0x1>; ++ dma-names = "ch1", "up"; + status = "disabled"; ++ ++ pwm { ++ compatible = "st,stm32-pwm"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ ++ timer@16 { ++ compatible = "st,stm32h7-timer-trigger"; ++ reg = <16>; ++ status = "disabled"; ++ }; + }; + +- adc2: adc@100 { +- compatible = "st,stm32mp1-adc"; +- #io-channel-cells = <1>; ++ spi5: spi@44009000 { + #address-cells = <1>; + #size-cells = <0>; +- reg = <0x100>; +- interrupt-parent = <&adc>; +- interrupts = <1>; +- dmas = <&dmamux1 10 0x400 0x01>; +- dma-names = "rx"; +- nvmem-cells = <&vrefint>; +- nvmem-cell-names = "vrefint"; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x44009000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI5_K>; ++ resets = <&rcc SPI5_R>; ++ dmas = <&dmamux1 85 0x400 0x05>, ++ <&dmamux1 86 0x400 0x05>; ++ dma-names = "rx", "tx"; + status = "disabled"; +- channel@13 { +- reg = <13>; +- label = "vrefint"; ++ }; ++ ++ sai1: sai@4400a000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x4400a000 0x400>; ++ reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI1_R>; ++ status = "disabled"; ++ ++ sai1a: audio-controller@4400a004 { ++ #sound-dai-cells = <0>; ++ ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x4 0x20>; ++ clocks = <&rcc SAI1_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 87 0x400 0x01>; ++ status = "disabled"; + }; +- channel@14 { +- reg = <14>; +- label = "vddcore"; ++ ++ sai1b: audio-controller@4400a024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI1_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 88 0x400 0x01>; ++ status = "disabled"; + }; + }; +- }; + +- sdmmc3: mmc@48004000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x48004000 0x400>; +- interrupts = ; +- clocks = <&rcc SDMMC3_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC3_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- usbotg_hs: usb-otg@49000000 { +- compatible = "st,stm32mp15-hsotg", "snps,dwc2"; +- reg = <0x49000000 0x10000>; +- clocks = <&rcc USBO_K>, <&usbphyc>; +- clock-names = "otg", "utmi"; +- resets = <&rcc USBO_R>; +- reset-names = "dwc2"; +- interrupts = ; +- g-rx-fifo-size = <512>; +- g-np-tx-fifo-size = <32>; +- g-tx-fifo-size = <256 16 16 16 16 16 16 16>; +- dr_mode = "otg"; +- otg-rev = <0x200>; +- usb33d-supply = <&usb33>; +- status = "disabled"; +- }; ++ sai2: sai@4400b000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x4400b000 0x400>; ++ reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI2_R>; ++ status = "disabled"; + +- ipcc: mailbox@4c001000 { +- compatible = "st,stm32mp1-ipcc"; +- #mbox-cells = <1>; +- reg = <0x4c001000 0x400>; +- st,proc-id = <0>; +- interrupts-extended = +- <&exti 61 IRQ_TYPE_LEVEL_HIGH>, +- <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "rx", "tx"; +- clocks = <&rcc IPCC>; +- wakeup-source; +- status = "disabled"; +- }; ++ sai2a: audio-controller@4400b004 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x4 0x20>; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 89 0x400 0x01>; ++ status = "disabled"; ++ }; + +- dcmi: dcmi@4c006000 { +- compatible = "st,stm32-dcmi"; +- reg = <0x4c006000 0x400>; +- interrupts = ; +- resets = <&rcc CAMITF_R>; +- clocks = <&rcc DCMI>; +- clock-names = "mclk"; +- dmas = <&dmamux1 75 0x400 0x01>; +- dma-names = "tx"; +- status = "disabled"; +- }; ++ sai2b: audio-controller@4400b024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI2_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 90 0x400 0x01>; ++ status = "disabled"; ++ }; ++ }; + +- rcc: rcc@50000000 { +- compatible = "st,stm32mp1-rcc", "syscon"; +- reg = <0x50000000 0x1000>; +- #clock-cells = <1>; +- #reset-cells = <1>; +- }; ++ sai3: sai@4400c000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x4400c000 0x400>; ++ reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI3_R>; ++ status = "disabled"; + +- pwr_regulators: pwr@50001000 { +- compatible = "st,stm32mp1,pwr-reg"; +- reg = <0x50001000 0x10>; ++ sai3a: audio-controller@4400c004 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x04 0x20>; ++ clocks = <&rcc SAI3_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 113 0x400 0x01>; ++ status = "disabled"; ++ }; + +- reg11: reg11 { +- regulator-name = "reg11"; +- regulator-min-microvolt = <1100000>; +- regulator-max-microvolt = <1100000>; ++ sai3b: audio-controller@4400c024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI3_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 114 0x400 0x01>; ++ status = "disabled"; ++ }; + }; + +- reg18: reg18 { +- regulator-name = "reg18"; +- regulator-min-microvolt = <1800000>; +- regulator-max-microvolt = <1800000>; +- }; ++ dfsdm: dfsdm@4400d000 { ++ compatible = "st,stm32mp1-dfsdm"; ++ reg = <0x4400d000 0x800>; ++ clocks = <&rcc DFSDM_K>; ++ clock-names = "dfsdm"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; + +- usb33: usb33 { +- regulator-name = "usb33"; +- regulator-min-microvolt = <3300000>; +- regulator-max-microvolt = <3300000>; +- }; +- }; ++ dfsdm0: filter@0 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <0>; ++ interrupts = ; ++ dmas = <&dmamux1 101 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- pwr_mcu: pwr_mcu@50001014 { +- compatible = "st,stm32mp151-pwr-mcu", "syscon"; +- reg = <0x50001014 0x4>; +- }; ++ dfsdm1: filter@1 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <1>; ++ interrupts = ; ++ dmas = <&dmamux1 102 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- exti: interrupt-controller@5000d000 { +- compatible = "st,stm32mp1-exti", "syscon"; +- interrupt-controller; +- #interrupt-cells = <2>; +- reg = <0x5000d000 0x400>; +- }; ++ dfsdm2: filter@2 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <2>; ++ interrupts = ; ++ dmas = <&dmamux1 103 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- syscfg: syscon@50020000 { +- compatible = "st,stm32mp157-syscfg", "syscon"; +- reg = <0x50020000 0x400>; +- clocks = <&rcc SYSCFG>; +- }; ++ dfsdm3: filter@3 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <3>; ++ interrupts = ; ++ dmas = <&dmamux1 104 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- lptimer2: timer@50021000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50021000 0x400>; +- interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM2_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; ++ dfsdm4: filter@4 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <4>; ++ interrupts = ; ++ dmas = <&dmamux1 91 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; +- status = "disabled"; ++ dfsdm5: filter@5 { ++ compatible = "st,stm32-dfsdm-adc"; ++ #io-channel-cells = <1>; ++ reg = <5>; ++ interrupts = ; ++ dmas = <&dmamux1 92 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + }; + +- trigger@1 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <1>; ++ dma1: dma-controller@48000000 { ++ compatible = "st,stm32-dma"; ++ reg = <0x48000000 0x400>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ clocks = <&rcc DMA1>; ++ resets = <&rcc DMA1_R>; ++ #dma-cells = <4>; ++ st,mem2mem; ++ dma-requests = <8>; ++ }; ++ ++ dma2: dma-controller@48001000 { ++ compatible = "st,stm32-dma"; ++ reg = <0x48001000 0x400>; ++ interrupts = , ++ , ++ , ++ , ++ , ++ , ++ , ++ ; ++ clocks = <&rcc DMA2>; ++ resets = <&rcc DMA2_R>; ++ #dma-cells = <4>; ++ st,mem2mem; ++ dma-requests = <8>; ++ }; ++ ++ dmamux1: dma-router@48002000 { ++ compatible = "st,stm32h7-dmamux"; ++ reg = <0x48002000 0x40>; ++ #dma-cells = <3>; ++ dma-requests = <128>; ++ dma-masters = <&dma1 &dma2>; ++ dma-channels = <16>; ++ clocks = <&rcc DMAMUX>; ++ resets = <&rcc DMAMUX_R>; ++ }; ++ ++ adc: adc@48003000 { ++ compatible = "st,stm32mp1-adc-core"; ++ reg = <0x48003000 0x400>; ++ interrupts = , ++ ; ++ clocks = <&rcc ADC12>, <&rcc ADC12_K>; ++ clock-names = "bus", "adc"; ++ interrupt-controller; ++ st,syscfg = <&syscfg>; ++ #interrupt-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; + status = "disabled"; +- }; + +- counter { +- compatible = "st,stm32-lptimer-counter"; +- status = "disabled"; +- }; +- }; ++ adc1: adc@0 { ++ compatible = "st,stm32mp1-adc"; ++ #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0>; ++ interrupt-parent = <&adc>; ++ interrupts = <0>; ++ dmas = <&dmamux1 9 0x400 0x01>; ++ dma-names = "rx"; ++ status = "disabled"; ++ }; + +- lptimer3: timer@50022000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32-lptimer"; +- reg = <0x50022000 0x400>; +- interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM3_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; ++ adc2: adc@100 { ++ compatible = "st,stm32mp1-adc"; ++ #io-channel-cells = <1>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x100>; ++ interrupt-parent = <&adc>; ++ interrupts = <1>; ++ dmas = <&dmamux1 10 0x400 0x01>; ++ dma-names = "rx"; ++ nvmem-cells = <&vrefint>; ++ nvmem-cell-names = "vrefint"; ++ status = "disabled"; ++ channel@13 { ++ reg = <13>; ++ label = "vrefint"; ++ }; ++ channel@14 { ++ reg = <14>; ++ label = "vddcore"; ++ }; ++ }; ++ }; + +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; ++ sdmmc3: mmc@48004000 { ++ compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; ++ arm,primecell-periphid = <0x00253180>; ++ reg = <0x48004000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SDMMC3_K>; ++ clock-names = "apb_pclk"; ++ resets = <&rcc SDMMC3_R>; ++ cap-sd-highspeed; ++ cap-mmc-highspeed; ++ max-frequency = <120000000>; + status = "disabled"; + }; + +- trigger@2 { +- compatible = "st,stm32-lptimer-trigger"; +- reg = <2>; ++ usbotg_hs: usb-otg@49000000 { ++ compatible = "st,stm32mp15-hsotg", "snps,dwc2"; ++ reg = <0x49000000 0x10000>; ++ clocks = <&rcc USBO_K>, <&usbphyc>; ++ clock-names = "otg", "utmi"; ++ resets = <&rcc USBO_R>; ++ reset-names = "dwc2"; ++ interrupts = ; ++ g-rx-fifo-size = <512>; ++ g-np-tx-fifo-size = <32>; ++ g-tx-fifo-size = <256 16 16 16 16 16 16 16>; ++ dr_mode = "otg"; ++ otg-rev = <0x200>; ++ usb33d-supply = <&usb33>; + status = "disabled"; + }; +- }; + +- lptimer4: timer@50023000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x50023000 0x400>; +- interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM4_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; ++ dcmi: dcmi@4c006000 { ++ compatible = "st,stm32-dcmi"; ++ reg = <0x4c006000 0x400>; ++ interrupts = ; ++ resets = <&rcc CAMITF_R>; ++ clocks = <&rcc DCMI>; ++ clock-names = "mclk"; ++ dmas = <&dmamux1 75 0x400 0x01>; ++ dma-names = "tx"; + status = "disabled"; + }; +- }; + +- lptimer5: timer@50024000 { +- compatible = "st,stm32-lptimer"; +- reg = <0x50024000 0x400>; +- interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc LPTIM5_K>; +- clock-names = "mux"; +- wakeup-source; +- status = "disabled"; +- +- pwm { +- compatible = "st,stm32-pwm-lp"; +- #pwm-cells = <3>; ++ lptimer2: timer@50021000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50021000 0x400>; ++ interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM2_K>; ++ clock-names = "mux"; ++ wakeup-source; + status = "disabled"; +- }; +- }; + +- vrefbuf: vrefbuf@50025000 { +- compatible = "st,stm32-vrefbuf"; +- reg = <0x50025000 0x8>; +- regulator-min-microvolt = <1500000>; +- regulator-max-microvolt = <2500000>; +- clocks = <&rcc VREF>; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- sai4: sai@50027000 { +- compatible = "st,stm32h7-sai"; +- #address-cells = <1>; +- #size-cells = <1>; +- ranges = <0 0x50027000 0x400>; +- reg = <0x50027000 0x4>, <0x500273f0 0x10>; +- interrupts = ; +- resets = <&rcc SAI4_R>; +- status = "disabled"; ++ trigger@1 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <1>; ++ status = "disabled"; ++ }; + +- sai4a: audio-controller@50027004 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-a"; +- reg = <0x04 0x20>; +- clocks = <&rcc SAI4_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 99 0x400 0x01>; +- status = "disabled"; ++ counter { ++ compatible = "st,stm32-lptimer-counter"; ++ status = "disabled"; ++ }; + }; + +- sai4b: audio-controller@50027024 { +- #sound-dai-cells = <0>; +- compatible = "st,stm32-sai-sub-b"; +- reg = <0x24 0x20>; +- clocks = <&rcc SAI4_K>; +- clock-names = "sai_ck"; +- dmas = <&dmamux1 100 0x400 0x01>; ++ lptimer3: timer@50022000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50022000 0x400>; ++ interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM3_K>; ++ clock-names = "mux"; ++ wakeup-source; + status = "disabled"; +- }; +- }; +- +- dts: thermal@50028000 { +- compatible = "st,stm32-thermal"; +- reg = <0x50028000 0x100>; +- interrupts = ; +- clocks = <&rcc TMPSENS>; +- clock-names = "pclk"; +- #thermal-sensor-cells = <0>; +- status = "disabled"; +- }; +- +- hash1: hash@54002000 { +- compatible = "st,stm32f756-hash"; +- reg = <0x54002000 0x400>; +- interrupts = ; +- clocks = <&rcc HASH1>; +- resets = <&rcc HASH1_R>; +- dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; +- dma-names = "in"; +- dma-maxburst = <2>; +- status = "disabled"; +- }; +- +- rng1: rng@54003000 { +- compatible = "st,stm32-rng"; +- reg = <0x54003000 0x400>; +- clocks = <&rcc RNG1_K>; +- resets = <&rcc RNG1_R>; +- status = "disabled"; +- }; +- +- mdma1: dma-controller@58000000 { +- compatible = "st,stm32h7-mdma"; +- reg = <0x58000000 0x1000>; +- interrupts = ; +- clocks = <&rcc MDMA>; +- resets = <&rcc MDMA_R>; +- #dma-cells = <5>; +- dma-channels = <32>; +- dma-requests = <48>; +- }; + +- fmc: memory-controller@58002000 { +- #address-cells = <2>; +- #size-cells = <1>; +- compatible = "st,stm32mp1-fmc2-ebi"; +- reg = <0x58002000 0x1000>; +- clocks = <&rcc FMC_K>; +- resets = <&rcc FMC_R>; +- status = "disabled"; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + +- ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ +- <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ +- <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ +- <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ +- <4 0 0x80000000 0x10000000>; /* NAND */ +- +- nand-controller@4,0 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32mp1-fmc2-nfc"; +- reg = <4 0x00000000 0x1000>, +- <4 0x08010000 0x1000>, +- <4 0x08020000 0x1000>, +- <4 0x01000000 0x1000>, +- <4 0x09010000 0x1000>, +- <4 0x09020000 0x1000>; +- interrupts = ; +- dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, +- <&mdma1 20 0x2 0x12000a08 0x0 0x0>, +- <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; +- dma-names = "tx", "rx", "ecc"; +- status = "disabled"; ++ trigger@2 { ++ compatible = "st,stm32-lptimer-trigger"; ++ reg = <2>; ++ status = "disabled"; ++ }; + }; +- }; +- +- qspi: spi@58003000 { +- compatible = "st,stm32f469-qspi"; +- reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; +- reg-names = "qspi", "qspi_mm"; +- interrupts = ; +- dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, +- <&mdma1 22 0x2 0x10100008 0x0 0x0>; +- dma-names = "tx", "rx"; +- clocks = <&rcc QSPI_K>; +- resets = <&rcc QSPI_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- status = "disabled"; +- }; + +- sdmmc1: mmc@58005000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x58005000 0x1000>; +- interrupts = ; +- clocks = <&rcc SDMMC1_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC1_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- sdmmc2: mmc@58007000 { +- compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; +- arm,primecell-periphid = <0x00253180>; +- reg = <0x58007000 0x1000>; +- interrupts = ; +- clocks = <&rcc SDMMC2_K>; +- clock-names = "apb_pclk"; +- resets = <&rcc SDMMC2_R>; +- cap-sd-highspeed; +- cap-mmc-highspeed; +- max-frequency = <120000000>; +- status = "disabled"; +- }; +- +- crc1: crc@58009000 { +- compatible = "st,stm32f7-crc"; +- reg = <0x58009000 0x400>; +- clocks = <&rcc CRC1>; +- status = "disabled"; +- }; +- +- ethernet0: ethernet@5800a000 { +- compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; +- reg = <0x5800a000 0x2000>; +- reg-names = "stmmaceth"; +- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; +- clock-names = "stmmaceth", +- "mac-clk-tx", +- "mac-clk-rx", +- "eth-ck", +- "ptp_ref", +- "ethstp"; +- clocks = <&rcc ETHMAC>, +- <&rcc ETHTX>, +- <&rcc ETHRX>, +- <&rcc ETHCK_K>, +- <&rcc ETHPTP_K>, +- <&rcc ETHSTP>; +- st,syscon = <&syscfg 0x4>; +- snps,mixed-burst; +- snps,pbl = <2>; +- snps,en-tx-lpi-clockgating; +- snps,axi-config = <&stmmac_axi_config_0>; +- snps,tso; +- status = "disabled"; ++ lptimer4: timer@50023000 { ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50023000 0x400>; ++ interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM4_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; + +- stmmac_axi_config_0: stmmac-axi-config { +- snps,wr_osr_lmt = <0x7>; +- snps,rd_osr_lmt = <0x7>; +- snps,blen = <0 0 0 0 16 8 4>; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; + }; +- }; + +- usbh_ohci: usb@5800c000 { +- compatible = "generic-ohci"; +- reg = <0x5800c000 0x1000>; +- clocks = <&usbphyc>, <&rcc USBH>; +- resets = <&rcc USBH_R>; +- interrupts = ; +- status = "disabled"; +- }; ++ lptimer5: timer@50024000 { ++ compatible = "st,stm32-lptimer"; ++ reg = <0x50024000 0x400>; ++ interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc LPTIM5_K>; ++ clock-names = "mux"; ++ wakeup-source; ++ status = "disabled"; + +- usbh_ehci: usb@5800d000 { +- compatible = "generic-ehci"; +- reg = <0x5800d000 0x1000>; +- clocks = <&usbphyc>, <&rcc USBH>; +- resets = <&rcc USBH_R>; +- interrupts = ; +- companion = <&usbh_ohci>; +- status = "disabled"; +- }; ++ pwm { ++ compatible = "st,stm32-pwm-lp"; ++ #pwm-cells = <3>; ++ status = "disabled"; ++ }; ++ }; + +- ltdc: display-controller@5a001000 { +- compatible = "st,stm32-ltdc"; +- reg = <0x5a001000 0x400>; +- interrupts = , +- ; +- clocks = <&rcc LTDC_PX>; +- clock-names = "lcd"; +- resets = <&rcc LTDC_R>; +- status = "disabled"; +- }; ++ vrefbuf: vrefbuf@50025000 { ++ compatible = "st,stm32-vrefbuf"; ++ reg = <0x50025000 0x8>; ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <2500000>; ++ clocks = <&rcc VREF>; ++ status = "disabled"; ++ }; + +- iwdg2: watchdog@5a002000 { +- compatible = "st,stm32mp1-iwdg"; +- reg = <0x5a002000 0x400>; +- clocks = <&rcc IWDG2>, <&rcc CK_LSI>; +- clock-names = "pclk", "lsi"; +- status = "disabled"; +- }; ++ sai4: sai@50027000 { ++ compatible = "st,stm32h7-sai"; ++ #address-cells = <1>; ++ #size-cells = <1>; ++ ranges = <0 0x50027000 0x400>; ++ reg = <0x50027000 0x4>, <0x500273f0 0x10>; ++ interrupts = ; ++ resets = <&rcc SAI4_R>; ++ status = "disabled"; + +- usbphyc: usbphyc@5a006000 { +- #address-cells = <1>; +- #size-cells = <0>; +- #clock-cells = <0>; +- compatible = "st,stm32mp1-usbphyc"; +- reg = <0x5a006000 0x1000>; +- clocks = <&rcc USBPHY_K>; +- resets = <&rcc USBPHY_R>; +- vdda1v1-supply = <®11>; +- vdda1v8-supply = <®18>; +- status = "disabled"; ++ sai4a: audio-controller@50027004 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-a"; ++ reg = <0x04 0x20>; ++ clocks = <&rcc SAI4_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 99 0x400 0x01>; ++ status = "disabled"; ++ }; + +- usbphyc_port0: usb-phy@0 { +- #phy-cells = <0>; +- reg = <0>; ++ sai4b: audio-controller@50027024 { ++ #sound-dai-cells = <0>; ++ compatible = "st,stm32-sai-sub-b"; ++ reg = <0x24 0x20>; ++ clocks = <&rcc SAI4_K>; ++ clock-names = "sai_ck"; ++ dmas = <&dmamux1 100 0x400 0x01>; ++ status = "disabled"; ++ }; + }; + +- usbphyc_port1: usb-phy@1 { +- #phy-cells = <1>; +- reg = <1>; ++ hash1: hash@54002000 { ++ compatible = "st,stm32f756-hash"; ++ reg = <0x54002000 0x400>; ++ interrupts = ; ++ clocks = <&rcc HASH1>; ++ resets = <&rcc HASH1_R>; ++ dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; ++ dma-names = "in"; ++ dma-maxburst = <2>; ++ status = "disabled"; + }; +- }; +- +- usart1: serial@5c000000 { +- compatible = "st,stm32h7-uart"; +- reg = <0x5c000000 0x400>; +- interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; +- clocks = <&rcc USART1_K>; +- wakeup-source; +- status = "disabled"; +- }; + +- spi6: spi@5c001000 { +- #address-cells = <1>; +- #size-cells = <0>; +- compatible = "st,stm32h7-spi"; +- reg = <0x5c001000 0x400>; +- interrupts = ; +- clocks = <&rcc SPI6_K>; +- resets = <&rcc SPI6_R>; +- dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, +- <&mdma1 35 0x0 0x40002 0x0 0x0>; +- dma-names = "rx", "tx"; +- status = "disabled"; +- }; ++ rng1: rng@54003000 { ++ compatible = "st,stm32-rng"; ++ reg = <0x54003000 0x400>; ++ clocks = <&rcc RNG1_K>; ++ resets = <&rcc RNG1_R>; ++ status = "disabled"; ++ }; + +- i2c4: i2c@5c002000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x5c002000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C4_K>; +- resets = <&rcc I2C4_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x8>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; +- }; ++ fmc: memory-controller@58002000 { ++ #address-cells = <2>; ++ #size-cells = <1>; ++ compatible = "st,stm32mp1-fmc2-ebi"; ++ reg = <0x58002000 0x1000>; ++ clocks = <&rcc FMC_K>; ++ resets = <&rcc FMC_R>; ++ status = "disabled"; ++ ++ ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ ++ <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ ++ <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ ++ <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ ++ <4 0 0x80000000 0x10000000>; /* NAND */ ++ ++ nand-controller@4,0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32mp1-fmc2-nfc"; ++ reg = <4 0x00000000 0x1000>, ++ <4 0x08010000 0x1000>, ++ <4 0x08020000 0x1000>, ++ <4 0x01000000 0x1000>, ++ <4 0x09010000 0x1000>, ++ <4 0x09020000 0x1000>; ++ interrupts = ; ++ dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, ++ <&mdma1 20 0x2 0x12000a08 0x0 0x0>, ++ <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; ++ dma-names = "tx", "rx", "ecc"; ++ status = "disabled"; ++ }; ++ }; + +- rtc: rtc@5c004000 { +- compatible = "st,stm32mp1-rtc"; +- reg = <0x5c004000 0x400>; +- clocks = <&rcc RTCAPB>, <&rcc RTC>; +- clock-names = "pclk", "rtc_ck"; +- interrupts-extended = <&exti 19 IRQ_TYPE_LEVEL_HIGH>; +- status = "disabled"; +- }; ++ qspi: spi@58003000 { ++ compatible = "st,stm32f469-qspi"; ++ reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; ++ reg-names = "qspi", "qspi_mm"; ++ interrupts = ; ++ dmas = <&mdma1 22 0x2 0x10100002 0x0 0x0>, ++ <&mdma1 22 0x2 0x10100008 0x0 0x0>; ++ dma-names = "tx", "rx"; ++ clocks = <&rcc QSPI_K>; ++ resets = <&rcc QSPI_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ status = "disabled"; ++ }; + +- bsec: efuse@5c005000 { +- compatible = "st,stm32mp15-bsec"; +- reg = <0x5c005000 0x400>; +- #address-cells = <1>; +- #size-cells = <1>; +- part_number_otp: part-number-otp@4 { +- reg = <0x4 0x1>; ++ ethernet0: ethernet@5800a000 { ++ compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; ++ reg = <0x5800a000 0x2000>; ++ reg-names = "stmmaceth"; ++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq"; ++ clock-names = "stmmaceth", ++ "mac-clk-tx", ++ "mac-clk-rx", ++ "eth-ck", ++ "ptp_ref", ++ "ethstp"; ++ clocks = <&rcc ETHMAC>, ++ <&rcc ETHTX>, ++ <&rcc ETHRX>, ++ <&rcc ETHCK_K>, ++ <&rcc ETHPTP_K>, ++ <&rcc ETHSTP>; ++ st,syscon = <&syscfg 0x4>; ++ snps,mixed-burst; ++ snps,pbl = <2>; ++ snps,en-tx-lpi-clockgating; ++ snps,axi-config = <&stmmac_axi_config_0>; ++ snps,tso; ++ status = "disabled"; ++ ++ stmmac_axi_config_0: stmmac-axi-config { ++ snps,wr_osr_lmt = <0x7>; ++ snps,rd_osr_lmt = <0x7>; ++ snps,blen = <0 0 0 0 16 8 4>; ++ }; + }; +- vrefint: vrefin-cal@52 { +- reg = <0x52 0x2>; ++ ++ usart1: serial@5c000000 { ++ compatible = "st,stm32h7-uart"; ++ reg = <0x5c000000 0x400>; ++ interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; ++ clocks = <&rcc USART1_K>; ++ wakeup-source; ++ status = "disabled"; + }; +- ts_cal1: calib@5c { +- reg = <0x5c 0x2>; ++ ++ spi6: spi@5c001000 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "st,stm32h7-spi"; ++ reg = <0x5c001000 0x400>; ++ interrupts = ; ++ clocks = <&rcc SPI6_K>; ++ resets = <&rcc SPI6_R>; ++ dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, ++ <&mdma1 35 0x0 0x40002 0x0 0x0>; ++ dma-names = "rx", "tx"; ++ status = "disabled"; + }; +- ts_cal2: calib@5e { +- reg = <0x5e 0x2>; ++ ++ i2c4: i2c@5c002000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x5c002000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C4_K>; ++ resets = <&rcc I2C4_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x8>; ++ wakeup-source; ++ i2c-analog-filter; ++ status = "disabled"; + }; +- }; + +- i2c6: i2c@5c009000 { +- compatible = "st,stm32mp15-i2c"; +- reg = <0x5c009000 0x400>; +- interrupt-names = "event", "error"; +- interrupts = , +- ; +- clocks = <&rcc I2C6_K>; +- resets = <&rcc I2C6_R>; +- #address-cells = <1>; +- #size-cells = <0>; +- st,syscfg-fmp = <&syscfg 0x4 0x20>; +- wakeup-source; +- i2c-analog-filter; +- status = "disabled"; ++ i2c6: i2c@5c009000 { ++ compatible = "st,stm32mp15-i2c"; ++ reg = <0x5c009000 0x400>; ++ interrupt-names = "event", "error"; ++ interrupts = , ++ ; ++ clocks = <&rcc I2C6_K>; ++ resets = <&rcc I2C6_R>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ st,syscfg-fmp = <&syscfg 0x4 0x20>; ++ wakeup-source; ++ i2c-analog-filter; ++ status = "disabled"; ++ }; + }; + + tamp: tamp@5c00a000 { +--- a/arch/arm/boot/dts/st/stm32mp153.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp153.dtsi +@@ -28,32 +28,32 @@ + , + ; + }; ++}; + +- soc { +- m_can1: can@4400e000 { +- compatible = "bosch,m_can"; +- reg = <0x4400e000 0x400>, <0x44011000 0x1400>; +- reg-names = "m_can", "message_ram"; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; +- status = "disabled"; +- }; ++&etzpc { ++ m_can1: can@4400e000 { ++ compatible = "bosch,m_can"; ++ reg = <0x4400e000 0x400>, <0x44011000 0x1400>; ++ reg-names = "m_can", "message_ram"; ++ interrupts = , ++ ; ++ interrupt-names = "int0", "int1"; ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ clock-names = "hclk", "cclk"; ++ bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; ++ status = "disabled"; ++ }; + +- m_can2: can@4400f000 { +- compatible = "bosch,m_can"; +- reg = <0x4400f000 0x400>, <0x44011000 0x2800>; +- reg-names = "m_can", "message_ram"; +- interrupts = , +- ; +- interrupt-names = "int0", "int1"; +- clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; +- clock-names = "hclk", "cclk"; +- bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; +- status = "disabled"; +- }; ++ m_can2: can@4400f000 { ++ compatible = "bosch,m_can"; ++ reg = <0x4400f000 0x400>, <0x44011000 0x2800>; ++ reg-names = "m_can", "message_ram"; ++ interrupts = , ++ ; ++ interrupt-names = "int0", "int1"; ++ clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; ++ clock-names = "hclk", "cclk"; ++ bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; ++ status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi +@@ -4,15 +4,13 @@ + * Author: Alexandre Torgue for STMicroelectronics. + */ + +-/ { +- soc { +- cryp1: cryp@54001000 { +- compatible = "st,stm32mp1-cryp"; +- reg = <0x54001000 0x400>; +- interrupts = ; +- clocks = <&rcc CRYP1>; +- resets = <&rcc CRYP1_R>; +- status = "disabled"; +- }; ++&etzpc { ++ cryp1: cryp@54001000 { ++ compatible = "st,stm32mp1-cryp"; ++ reg = <0x54001000 0x400>; ++ interrupts = ; ++ clocks = <&rcc CRYP1>; ++ resets = <&rcc CRYP1_R>; ++ status = "disabled"; + }; + }; diff --git a/target/linux/stm32/patches-6.6/041-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch b/target/linux/stm32/patches-6.6/041-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch new file mode 100644 index 00000000000..9e28274b7a4 --- /dev/null +++ b/target/linux/stm32/patches-6.6/041-ARM-dts-stm32-put-ETZPC-as-an-access-controller-for-.patch @@ -0,0 +1,566 @@ +From 91ddf8509d0308e297f1876a024645cc3478e358 Mon Sep 17 00:00:00 2001 +From: Gatien Chevallier +Date: Fri, 5 Jan 2024 14:04:02 +0100 +Subject: [PATCH] ARM: dts: stm32: put ETZPC as an access controller for + STM32MP15x boards + +Reference ETZPC as an access-control-provider. + +For more information on which peripheral is securable or supports MCU +isolation, please read the STM32MP15 reference manual + +Signed-off-by: Gatien Chevallier +Signed-off-by: Alexandre Torgue +--- + arch/arm/boot/dts/st/stm32mp151.dtsi | 66 ++++++++++++++++++++++++++- + arch/arm/boot/dts/st/stm32mp153.dtsi | 2 + + arch/arm/boot/dts/st/stm32mp15xc.dtsi | 1 + + 3 files changed, 68 insertions(+), 1 deletion(-) + +--- a/arch/arm/boot/dts/st/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi +@@ -331,10 +331,11 @@ + }; + + etzpc: bus@5c007000 { +- compatible = "simple-bus"; ++ compatible = "st,stm32-etzpc", "simple-bus"; + reg = <0x5c007000 0x400>; + #address-cells = <1>; + #size-cells = <1>; ++ #access-controller-cells = <1>; + ranges; + + timers2: timer@40000000 { +@@ -352,6 +353,7 @@ + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; ++ access-controllers = <&etzpc 16>; + status = "disabled"; + + pwm { +@@ -388,6 +390,7 @@ + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ access-controllers = <&etzpc 17>; + status = "disabled"; + + pwm { +@@ -422,6 +425,7 @@ + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4"; ++ access-controllers = <&etzpc 18>; + status = "disabled"; + + pwm { +@@ -458,6 +462,7 @@ + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; ++ access-controllers = <&etzpc 19>; + status = "disabled"; + + pwm { +@@ -489,6 +494,7 @@ + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; ++ access-controllers = <&etzpc 20>; + status = "disabled"; + + timer@5 { +@@ -509,6 +515,7 @@ + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; ++ access-controllers = <&etzpc 21>; + status = "disabled"; + + timer@6 { +@@ -527,6 +534,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 22>; + status = "disabled"; + + pwm { +@@ -551,6 +559,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 23>; + status = "disabled"; + + pwm { +@@ -575,6 +584,7 @@ + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; ++ access-controllers = <&etzpc 24>; + status = "disabled"; + + pwm { +@@ -599,6 +609,7 @@ + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 25>; + status = "disabled"; + + pwm { +@@ -627,6 +638,7 @@ + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 27>; + status = "disabled"; + }; + +@@ -641,6 +653,7 @@ + dmas = <&dmamux1 39 0x400 0x05>, + <&dmamux1 40 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 27>; + status = "disabled"; + }; + +@@ -652,6 +665,7 @@ + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 28>; + status = "disabled"; + }; + +@@ -666,6 +680,7 @@ + dmas = <&dmamux1 61 0x400 0x05>, + <&dmamux1 62 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 28>; + status = "disabled"; + }; + +@@ -679,6 +694,7 @@ + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; ++ access-controllers = <&etzpc 29>; + status = "disabled"; + }; + +@@ -691,6 +707,7 @@ + dmas = <&dmamux1 43 0x400 0x15>, + <&dmamux1 44 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 30>; + status = "disabled"; + }; + +@@ -703,6 +720,7 @@ + dmas = <&dmamux1 45 0x400 0x15>, + <&dmamux1 46 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 31>; + status = "disabled"; + }; + +@@ -715,6 +733,7 @@ + dmas = <&dmamux1 63 0x400 0x15>, + <&dmamux1 64 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 32>; + status = "disabled"; + }; + +@@ -727,6 +746,7 @@ + dmas = <&dmamux1 65 0x400 0x15>, + <&dmamux1 66 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 33>; + status = "disabled"; + }; + +@@ -743,6 +763,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x1>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 34>; + status = "disabled"; + }; + +@@ -759,6 +780,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x2>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 35>; + status = "disabled"; + }; + +@@ -775,6 +797,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x4>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 36>; + status = "disabled"; + }; + +@@ -791,6 +814,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x10>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 37>; + status = "disabled"; + }; + +@@ -800,6 +824,7 @@ + interrupts = ; + clocks = <&rcc CEC_K>, <&rcc CEC>; + clock-names = "cec", "hdmi-cec"; ++ access-controllers = <&etzpc 38>; + status = "disabled"; + }; + +@@ -810,6 +835,7 @@ + clock-names = "pclk"; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 39>; + status = "disabled"; + + dac1: dac@1 { +@@ -836,6 +862,7 @@ + dmas = <&dmamux1 79 0x400 0x15>, + <&dmamux1 80 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 40>; + status = "disabled"; + }; + +@@ -848,6 +875,7 @@ + dmas = <&dmamux1 81 0x400 0x15>, + <&dmamux1 82 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 41>; + status = "disabled"; + }; + +@@ -872,6 +900,7 @@ + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; ++ access-controllers = <&etzpc 48>; + status = "disabled"; + + pwm { +@@ -913,6 +942,7 @@ + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; ++ access-controllers = <&etzpc 49>; + status = "disabled"; + + pwm { +@@ -942,6 +972,7 @@ + dmas = <&dmamux1 71 0x400 0x15>, + <&dmamux1 72 0x400 0x11>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 51>; + status = "disabled"; + }; + +@@ -953,6 +984,7 @@ + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 52>; + status = "disabled"; + }; + +@@ -967,6 +999,7 @@ + dmas = <&dmamux1 37 0x400 0x05>, + <&dmamux1 38 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 52>; + status = "disabled"; + }; + +@@ -981,6 +1014,7 @@ + dmas = <&dmamux1 83 0x400 0x05>, + <&dmamux1 84 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 53>; + status = "disabled"; + }; + +@@ -998,6 +1032,7 @@ + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; ++ access-controllers = <&etzpc 54>; + status = "disabled"; + + pwm { +@@ -1025,6 +1060,7 @@ + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; ++ access-controllers = <&etzpc 55>; + status = "disabled"; + + pwm { +@@ -1051,6 +1087,7 @@ + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; ++ access-controllers = <&etzpc 56>; + status = "disabled"; + + pwm { +@@ -1077,6 +1114,7 @@ + dmas = <&dmamux1 85 0x400 0x05>, + <&dmamux1 86 0x400 0x05>; + dma-names = "rx", "tx"; ++ access-controllers = <&etzpc 57>; + status = "disabled"; + }; + +@@ -1088,6 +1126,7 @@ + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + interrupts = ; + resets = <&rcc SAI1_R>; ++ access-controllers = <&etzpc 58>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { +@@ -1120,6 +1159,7 @@ + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + interrupts = ; + resets = <&rcc SAI2_R>; ++ access-controllers = <&etzpc 59>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { +@@ -1151,6 +1191,7 @@ + reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>; + interrupts = ; + resets = <&rcc SAI3_R>; ++ access-controllers = <&etzpc 60>; + status = "disabled"; + + sai3a: audio-controller@4400c004 { +@@ -1181,6 +1222,7 @@ + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 61>; + status = "disabled"; + + dfsdm0: filter@0 { +@@ -1260,6 +1302,7 @@ + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; ++ access-controllers = <&etzpc 88>; + }; + + dma2: dma-controller@48001000 { +@@ -1278,6 +1321,7 @@ + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; ++ access-controllers = <&etzpc 89>; + }; + + dmamux1: dma-router@48002000 { +@@ -1289,6 +1333,7 @@ + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + resets = <&rcc DMAMUX_R>; ++ access-controllers = <&etzpc 90>; + }; + + adc: adc@48003000 { +@@ -1303,6 +1348,7 @@ + #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 72>; + status = "disabled"; + + adc1: adc@0 { +@@ -1353,6 +1399,7 @@ + cap-sd-highspeed; + cap-mmc-highspeed; + max-frequency = <120000000>; ++ access-controllers = <&etzpc 86>; + status = "disabled"; + }; + +@@ -1370,6 +1417,7 @@ + dr_mode = "otg"; + otg-rev = <0x200>; + usb33d-supply = <&usb33>; ++ access-controllers = <&etzpc 85>; + status = "disabled"; + }; + +@@ -1382,6 +1430,7 @@ + clock-names = "mclk"; + dmas = <&dmamux1 75 0x400 0x01>; + dma-names = "tx"; ++ access-controllers = <&etzpc 70>; + status = "disabled"; + }; + +@@ -1394,6 +1443,7 @@ + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 64>; + status = "disabled"; + + pwm { +@@ -1423,6 +1473,7 @@ + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 65>; + status = "disabled"; + + pwm { +@@ -1445,6 +1496,7 @@ + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 66>; + status = "disabled"; + + pwm { +@@ -1461,6 +1513,7 @@ + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; ++ access-controllers = <&etzpc 67>; + status = "disabled"; + + pwm { +@@ -1476,6 +1529,7 @@ + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; ++ access-controllers = <&etzpc 69>; + status = "disabled"; + }; + +@@ -1487,6 +1541,7 @@ + reg = <0x50027000 0x4>, <0x500273f0 0x10>; + interrupts = ; + resets = <&rcc SAI4_R>; ++ access-controllers = <&etzpc 68>; + status = "disabled"; + + sai4a: audio-controller@50027004 { +@@ -1519,6 +1574,7 @@ + dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; + dma-names = "in"; + dma-maxburst = <2>; ++ access-controllers = <&etzpc 8>; + status = "disabled"; + }; + +@@ -1527,6 +1583,7 @@ + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; ++ access-controllers = <&etzpc 7>; + status = "disabled"; + }; + +@@ -1537,6 +1594,7 @@ + reg = <0x58002000 0x1000>; + clocks = <&rcc FMC_K>; + resets = <&rcc FMC_R>; ++ access-controllers = <&etzpc 91>; + status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ +@@ -1576,6 +1634,7 @@ + resets = <&rcc QSPI_R>; + #address-cells = <1>; + #size-cells = <0>; ++ access-controllers = <&etzpc 92>; + status = "disabled"; + }; + +@@ -1603,6 +1662,7 @@ + snps,en-tx-lpi-clockgating; + snps,axi-config = <&stmmac_axi_config_0>; + snps,tso; ++ access-controllers = <&etzpc 94>; + status = "disabled"; + + stmmac_axi_config_0: stmmac-axi-config { +@@ -1618,6 +1678,7 @@ + interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc USART1_K>; + wakeup-source; ++ access-controllers = <&etzpc 3>; + status = "disabled"; + }; + +@@ -1631,6 +1692,7 @@ + resets = <&rcc SPI6_R>; + dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, + <&mdma1 35 0x0 0x40002 0x0 0x0>; ++ access-controllers = <&etzpc 4>; + dma-names = "rx", "tx"; + status = "disabled"; + }; +@@ -1648,6 +1710,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x8>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 5>; + status = "disabled"; + }; + +@@ -1664,6 +1727,7 @@ + st,syscfg-fmp = <&syscfg 0x4 0x20>; + wakeup-source; + i2c-analog-filter; ++ access-controllers = <&etzpc 12>; + status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp153.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp153.dtsi +@@ -41,6 +41,7 @@ + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; ++ access-controllers = <&etzpc 62>; + status = "disabled"; + }; + +@@ -54,6 +55,7 @@ + clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; ++ access-controllers = <&etzpc 62>; + status = "disabled"; + }; + }; +--- a/arch/arm/boot/dts/st/stm32mp15xc.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp15xc.dtsi +@@ -11,6 +11,7 @@ + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; ++ access-controllers = <&etzpc 9>; + status = "disabled"; + }; + }; diff --git a/target/linux/stm32/patches-6.6/050-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch b/target/linux/stm32/patches-6.6/050-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch new file mode 100644 index 00000000000..235efb57168 --- /dev/null +++ b/target/linux/stm32/patches-6.6/050-mmc-mmci-stm32-add-SDIO-in-band-interrupt-mode.patch @@ -0,0 +1,166 @@ +From 1bcfbfd7c9aa716f61a01682345a1b329f6a6e66 Mon Sep 17 00:00:00 2001 +From: Christophe Kerello +Date: Wed, 8 Nov 2023 15:16:37 +0100 +Subject: [PATCH] mmc: mmci: stm32: add SDIO in-band interrupt mode + +Add the support of SDIO in-band interrupt mode for STM32 and Ux500 +variants. +It allows the SD I/O card to interrupt the host on SDMMC_D1 data line. +It is not enabled by default on Ux500 variant as this is unstable and +Ux500 users should use out-of-band IRQs. + +Signed-off-by: Christophe Kerello +Signed-off-by: Yann Gautier +Reviewed-by: Linus Walleij +Link: https://lore.kernel.org/r/20231108141637.119497-1-yann.gautier@foss.st.com +Signed-off-by: Ulf Hansson +--- + drivers/mmc/host/mmci.c | 69 +++++++++++++++++++++++++++++++++++++++-- + drivers/mmc/host/mmci.h | 2 ++ + 2 files changed, 69 insertions(+), 2 deletions(-) + +--- a/drivers/mmc/host/mmci.c ++++ b/drivers/mmc/host/mmci.c +@@ -272,6 +272,7 @@ static struct variant_data variant_stm32 + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .stm32_idmabsize_mask = GENMASK(12, 5), + .stm32_idmabsize_align = BIT(5), ++ .supports_sdio_irq = true, + .busy_timeout = true, + .busy_detect = true, + .busy_detect_flag = MCI_STM32_BUSYD0, +@@ -299,6 +300,7 @@ static struct variant_data variant_stm32 + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .stm32_idmabsize_mask = GENMASK(16, 5), + .stm32_idmabsize_align = BIT(5), ++ .supports_sdio_irq = true, + .dma_lli = true, + .busy_timeout = true, + .busy_detect = true, +@@ -327,6 +329,7 @@ static struct variant_data variant_stm32 + .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN, + .stm32_idmabsize_mask = GENMASK(16, 6), + .stm32_idmabsize_align = BIT(6), ++ .supports_sdio_irq = true, + .dma_lli = true, + .busy_timeout = true, + .busy_detect = true, +@@ -420,8 +423,9 @@ void mmci_write_pwrreg(struct mmci_host + */ + static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl) + { +- /* Keep busy mode in DPSM if enabled */ +- datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag; ++ /* Keep busy mode in DPSM and SDIO mask if enabled */ ++ datactrl |= host->datactrl_reg & (host->variant->busy_dpsm_flag | ++ host->variant->datactrl_mask_sdio); + + if (host->datactrl_reg != datactrl) { + host->datactrl_reg = datactrl; +@@ -1761,6 +1765,25 @@ static irqreturn_t mmci_pio_irq(int irq, + return IRQ_HANDLED; + } + ++static void mmci_write_sdio_irq_bit(struct mmci_host *host, int enable) ++{ ++ void __iomem *base = host->base; ++ u32 mask = readl_relaxed(base + MMCIMASK0); ++ ++ if (enable) ++ writel_relaxed(mask | MCI_ST_SDIOITMASK, base + MMCIMASK0); ++ else ++ writel_relaxed(mask & ~MCI_ST_SDIOITMASK, base + MMCIMASK0); ++} ++ ++static void mmci_signal_sdio_irq(struct mmci_host *host, u32 status) ++{ ++ if (status & MCI_ST_SDIOIT) { ++ mmci_write_sdio_irq_bit(host, 0); ++ sdio_signal_irq(host->mmc); ++ } ++} ++ + /* + * Handle completion of command and data transfers. + */ +@@ -1805,6 +1828,9 @@ static irqreturn_t mmci_irq(int irq, voi + mmci_data_irq(host, host->data, status); + } + ++ if (host->variant->supports_sdio_irq) ++ mmci_signal_sdio_irq(host, status); ++ + /* + * Busy detection has been handled by mmci_cmd_irq() above. + * Clear the status bit to prevent polling in IRQ context. +@@ -2041,6 +2067,35 @@ static int mmci_sig_volt_switch(struct m + return ret; + } + ++static void mmci_enable_sdio_irq(struct mmc_host *mmc, int enable) ++{ ++ struct mmci_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ if (enable) ++ /* Keep the SDIO mode bit if SDIO irqs are enabled */ ++ pm_runtime_get_sync(mmc_dev(mmc)); ++ ++ spin_lock_irqsave(&host->lock, flags); ++ mmci_write_sdio_irq_bit(host, enable); ++ spin_unlock_irqrestore(&host->lock, flags); ++ ++ if (!enable) { ++ pm_runtime_mark_last_busy(mmc_dev(mmc)); ++ pm_runtime_put_autosuspend(mmc_dev(mmc)); ++ } ++} ++ ++static void mmci_ack_sdio_irq(struct mmc_host *mmc) ++{ ++ struct mmci_host *host = mmc_priv(mmc); ++ unsigned long flags; ++ ++ spin_lock_irqsave(&host->lock, flags); ++ mmci_write_sdio_irq_bit(host, 1); ++ spin_unlock_irqrestore(&host->lock, flags); ++} ++ + static struct mmc_host_ops mmci_ops = { + .request = mmci_request, + .pre_req = mmci_pre_request, +@@ -2316,6 +2371,16 @@ static int mmci_probe(struct amba_device + mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; + } + ++ if (variant->supports_sdio_irq && host->mmc->caps & MMC_CAP_SDIO_IRQ) { ++ mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; ++ ++ mmci_ops.enable_sdio_irq = mmci_enable_sdio_irq; ++ mmci_ops.ack_sdio_irq = mmci_ack_sdio_irq; ++ ++ mmci_write_datactrlreg(host, ++ host->variant->datactrl_mask_sdio); ++ } ++ + /* Variants with mandatory busy timeout in HW needs R1B responses. */ + if (variant->busy_timeout) + mmc->caps |= MMC_CAP_NEED_RSP_BUSY; +--- a/drivers/mmc/host/mmci.h ++++ b/drivers/mmc/host/mmci.h +@@ -331,6 +331,7 @@ enum mmci_busy_state { + * register. + * @opendrain: bitmask identifying the OPENDRAIN bit inside MMCIPOWER register + * @dma_lli: true if variant has dma link list feature. ++ * @supports_sdio_irq: allow SD I/O card to interrupt the host + * @stm32_idmabsize_mask: stm32 sdmmc idma buffer size. + */ + struct variant_data { +@@ -376,6 +377,7 @@ struct variant_data { + u32 start_err; + u32 opendrain; + u8 dma_lli:1; ++ bool supports_sdio_irq; + u32 stm32_idmabsize_mask; + u32 stm32_idmabsize_align; + void (*init)(struct mmci_host *host); diff --git a/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch b/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch new file mode 100644 index 00000000000..b3758a54d90 --- /dev/null +++ b/target/linux/stm32/patches-6.6/700-net-stmmac-dwmac-stm32-add-support-of-phy-supply-pro.patch @@ -0,0 +1,106 @@ +From 7bfe3404a02923ca3858abf56b18a098b4be33b2 Mon Sep 17 00:00:00 2001 +From: Christophe Roullier +Date: Wed, 10 Nov 2021 17:39:40 +0100 +Subject: [PATCH] net: ethernet: stmmac: stm32: support the phy-supply + regulator binding + +Configure the phy regulator if defined by the "phy-supply" DT phandle. + +Signed-off-by: Christophe Roullier +--- + .../net/ethernet/stmicro/stmmac/dwmac-stm32.c | 51 ++++++++++++++++++- + 1 file changed, 50 insertions(+), 1 deletion(-) + +--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c ++++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c +@@ -14,6 +14,7 @@ + #include + #include + #include ++#include + #include + #include + #include +@@ -92,6 +93,7 @@ struct stm32_dwmac { + u32 mode_reg; /* MAC glue-logic mode register */ + u32 mode_mask; + struct regmap *regmap; ++ struct regulator *regulator; + u32 speed; + const struct stm32_ops *ops; + struct device *dev; +@@ -379,6 +381,16 @@ static int stm32_dwmac_parse_data(struct + } + } + ++ dwmac->regulator = devm_regulator_get_optional(dev, "phy"); ++ if (IS_ERR(dwmac->regulator)) { ++ if (PTR_ERR(dwmac->regulator) == -EPROBE_DEFER) { ++ dev_dbg(dev, "phy regulator is not available yet, deferred probing\n"); ++ return -EPROBE_DEFER; ++ } ++ dev_dbg(dev, "no regulator found\n"); ++ dwmac->regulator = NULL; ++ } ++ + return err; + } + +@@ -444,6 +456,28 @@ static int stm32mp1_parse_data(struct st + return err; + } + ++static int phy_power_on(struct stm32_dwmac *bsp_priv, bool enable) ++{ ++ int ret; ++ struct device *dev = bsp_priv->dev; ++ ++ if (!bsp_priv->regulator) ++ return 0; ++ ++ if (enable) { ++ ret = regulator_enable(bsp_priv->regulator); ++ if (ret) ++ dev_err(dev, "fail to enable phy-supply\n"); ++ } else { ++ ret = regulator_disable(bsp_priv->regulator); ++ if (ret) ++ dev_err(dev, "fail to disable phy-supply\n"); ++ } ++ ++ return 0; ++} ++ ++ + static int stm32_dwmac_probe(struct platform_device *pdev) + { + struct plat_stmmacenet_data *plat_dat; +@@ -485,12 +519,18 @@ static int stm32_dwmac_probe(struct plat + if (ret) + return ret; + +- ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ ret = phy_power_on(plat_dat->bsp_priv, true); + if (ret) + goto err_clk_disable; + ++ ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); ++ if (ret) ++ goto err_gmac_powerdown; ++ + return 0; + ++err_gmac_powerdown: ++ phy_power_on(plat_dat->bsp_priv, false); + err_clk_disable: + stm32_dwmac_clk_disable(dwmac, false); + +@@ -511,6 +551,8 @@ static void stm32_dwmac_remove(struct pl + dev_pm_clear_wake_irq(&pdev->dev); + device_init_wakeup(&pdev->dev, false); + } ++ ++ phy_power_on(priv->plat->bsp_priv, false); + } + + static int stm32mp1_suspend(struct stm32_dwmac *dwmac) diff --git a/target/linux/stm32/patches-6.6/900-ARM-dts-stm32-add-ethernet2-for-STM32MP135F-DK-board.patch b/target/linux/stm32/patches-6.6/900-ARM-dts-stm32-add-ethernet2-for-STM32MP135F-DK-board.patch new file mode 100644 index 00000000000..48fa446bd86 --- /dev/null +++ b/target/linux/stm32/patches-6.6/900-ARM-dts-stm32-add-ethernet2-for-STM32MP135F-DK-board.patch @@ -0,0 +1,53 @@ +From 63c84f846ec5b794a6c90a1c5813cdb0ae75daf6 Mon Sep 17 00:00:00 2001 +From: Thomas Richard +Date: Thu, 26 Sep 2024 16:48:52 +0200 +Subject: [PATCH] ARM: dts: stm32: add ethernet2 for STM32MP135F-DK board + +This patch is based on the stm32mp135f-dk devicetree from 6.6 ST kernel. + +Signed-off-by: Thomas Richard +--- + arch/arm/boot/dts/st/stm32mp135f-dk.dts | 25 +++++++++++++++++++++++++ + 1 file changed, 25 insertions(+) + +--- a/arch/arm/boot/dts/st/stm32mp135f-dk.dts ++++ b/arch/arm/boot/dts/st/stm32mp135f-dk.dts +@@ -20,6 +20,7 @@ + + aliases { + ethernet0 = ðernet1; ++ ethernet1 = ðernet2; + serial0 = &uart4; + serial1 = &usart1; + serial2 = &uart8; +@@ -129,6 +130,30 @@ + }; + }; + ++ðernet2 { ++ status = "okay"; ++ pinctrl-0 = <ð2_rmii_pins_a>; ++ pinctrl-1 = <ð2_rmii_sleep_pins_a>; ++ pinctrl-names = "default", "sleep"; ++ phy-mode = "rmii"; ++ phy-handle = <&phy0_eth2>; ++ st,ext-phyclk; ++ phy-supply = <&scmi_v3v3_sw>; ++ ++ mdio1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ compatible = "snps,dwmac-mdio"; ++ phy0_eth2: ethernet-phy@0 { ++ compatible = "ethernet-phy-id0007.c131"; ++ reset-gpios = <&mcp23017 10 GPIO_ACTIVE_LOW>; ++ reg = <0>; ++ }; ++ }; ++}; ++ ++ ++ + &i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; diff --git a/target/linux/stm32/patches-6.6/910-ARM-dts-stm32-add-missing-eth_wake_irq-interrupt-for.patch b/target/linux/stm32/patches-6.6/910-ARM-dts-stm32-add-missing-eth_wake_irq-interrupt-for.patch new file mode 100644 index 00000000000..cb1bc91ce8e --- /dev/null +++ b/target/linux/stm32/patches-6.6/910-ARM-dts-stm32-add-missing-eth_wake_irq-interrupt-for.patch @@ -0,0 +1,26 @@ +From 6e10eb83e20e3a31bef8580bb4197240b0a28888 Mon Sep 17 00:00:00 2001 +From: Thomas Richard +Date: Thu, 17 Oct 2024 19:51:32 +0200 +Subject: [PATCH] ARM: dts: stm32: add missing eth_wake_irq interrupt for the + ethernet on STM32MP157 + +Signed-off-by: Thomas Richard +--- + arch/arm/boot/dts/st/stm32mp151.dtsi | 6 ++++-- + 1 file changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/arm/boot/dts/st/stm32mp151.dtsi ++++ b/arch/arm/boot/dts/st/stm32mp151.dtsi +@@ -1642,8 +1642,10 @@ + compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; + reg = <0x5800a000 0x2000>; + reg-names = "stmmaceth"; +- interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; +- interrupt-names = "macirq"; ++ interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>, ++ <&exti 70 IRQ_TYPE_LEVEL_HIGH>; ++ interrupt-names = "macirq", ++ "eth_wake_irq"; + clock-names = "stmmaceth", + "mac-clk-tx", + "mac-clk-rx", diff --git a/target/linux/stm32/stm32mp1/config-6.6 b/target/linux/stm32/stm32mp1/config-6.6 new file mode 100644 index 00000000000..b677322a25e --- /dev/null +++ b/target/linux/stm32/stm32mp1/config-6.6 @@ -0,0 +1,491 @@ +CONFIG_ALIGNMENT_TRAP=y +CONFIG_ARCH_32BIT_OFF_T=y +CONFIG_ARCH_FORCE_MAX_ORDER=12 +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_KEEP_MEMBLOCK=y +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_ARCH_MULTIPLATFORM=y +CONFIG_ARCH_MULTI_V6_V7=y +CONFIG_ARCH_MULTI_V7=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX=y +CONFIG_ARCH_OPTIONAL_KERNEL_RWX_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_ARCH_STM32=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARM=y +CONFIG_ARM_AMBA=y +CONFIG_ARM_APPENDED_DTB=y +CONFIG_ARM_ARCH_TIMER=y +CONFIG_ARM_ARCH_TIMER_EVTSTREAM=y +CONFIG_ARM_ATAG_DTB_COMPAT=y +CONFIG_ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER=y +CONFIG_ARM_CPU_SUSPEND=y +CONFIG_ARM_ERRATA_430973=y +CONFIG_ARM_ERRATA_643719=y +CONFIG_ARM_ERRATA_720789=y +CONFIG_ARM_ERRATA_754322=y +CONFIG_ARM_ERRATA_754327=y +CONFIG_ARM_ERRATA_764369=y +CONFIG_ARM_ERRATA_775420=y +CONFIG_ARM_ERRATA_798181=y +CONFIG_ARM_ERRATA_814220=y +CONFIG_ARM_GIC=y +CONFIG_ARM_HAS_GROUP_RELOCS=y +# CONFIG_ARM_HIGHBANK_CPUIDLE is not set +CONFIG_ARM_L1_CACHE_SHIFT=6 +CONFIG_ARM_L1_CACHE_SHIFT_6=y +CONFIG_ARM_PATCH_IDIV=y +CONFIG_ARM_PATCH_PHYS_VIRT=y +# CONFIG_ARM_PL172_MPMC is not set +CONFIG_ARM_PSCI=y +CONFIG_ARM_PSCI_CPUIDLE=y +CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y +CONFIG_ARM_PSCI_FW=y +CONFIG_ARM_SCMI_CPUFREQ=y +# CONFIG_ARM_SCMI_DEBUG_COUNTERS is not set +CONFIG_ARM_SCMI_HAVE_MSG=y +CONFIG_ARM_SCMI_HAVE_SHMEM=y +CONFIG_ARM_SCMI_HAVE_TRANSPORT=y +# CONFIG_ARM_SCMI_POWER_CONTROL is not set +CONFIG_ARM_SCMI_POWER_DOMAIN=y +CONFIG_ARM_SCMI_PROTOCOL=y +# CONFIG_ARM_SCMI_RAW_MODE_SUPPORT is not set +CONFIG_ARM_SCMI_TRANSPORT_OPTEE=y +CONFIG_ARM_SCMI_TRANSPORT_SMC=y +# CONFIG_ARM_SCMI_TRANSPORT_SMC_ATOMIC_ENABLE is not set +CONFIG_ARM_SMCCC_SOC_ID=y +CONFIG_ARM_SMC_WATCHDOG=y +# CONFIG_ARM_SMMU is not set +CONFIG_ARM_THUMB=y +CONFIG_ARM_THUMBEE=y +CONFIG_ARM_UNWIND=y +CONFIG_ARM_VIRT_EXT=y +CONFIG_AUTO_ZRELADDR=y +CONFIG_BINFMT_FLAT_ARGVP_ENVP_ON_STACK=y +# CONFIG_BLK_DEV_INITRD is not set +CONFIG_BLK_DEV_SD=y +CONFIG_BLK_PM=y +CONFIG_BOUNCE=y +CONFIG_BUFFER_HEAD=y +# CONFIG_CACHE_L2X0 is not set +CONFIG_CC_HAVE_STACKPROTECTOR_TLS=y +CONFIG_CHR_DEV_SG=y +CONFIG_CLKSRC_MMIO=y +CONFIG_CLKSRC_STM32=y +CONFIG_CLK_ICST=y +CONFIG_CLONE_BACKWARDS=y +CONFIG_CMA=y +CONFIG_CMA_ALIGNMENT=8 +CONFIG_CMA_AREAS=7 +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_SIZE_MBYTES=64 +# CONFIG_CMA_SIZE_SEL_MAX is not set +CONFIG_CMA_SIZE_SEL_MBYTES=y +# CONFIG_CMA_SIZE_SEL_MIN is not set +# CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set +# CONFIG_CMA_SYSFS is not set +CONFIG_CMDLINE_PARTITION=y +CONFIG_COMMON_CLK=y +CONFIG_COMMON_CLK_SCMI=y +CONFIG_COMMON_CLK_STM32MP135=y +CONFIG_COMMON_CLK_STM32MP157=y +CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1 +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_CONTEXT_TRACKING=y +CONFIG_CONTEXT_TRACKING_IDLE=y +CONFIG_CONTIG_ALLOC=y +CONFIG_COREDUMP=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_CPUFREQ_DT=y +CONFIG_CPUFREQ_DT_PLATDEV=y +CONFIG_CPU_32v6K=y +CONFIG_CPU_32v7=y +CONFIG_CPU_ABRT_EV7=y +CONFIG_CPU_CACHE_V7=y +CONFIG_CPU_CACHE_VIPT=y +CONFIG_CPU_COPY_V6=y +CONFIG_CPU_CP15=y +CONFIG_CPU_CP15_MMU=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_HAS_ASID=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_MENU=y +CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y +CONFIG_CPU_ISOLATION=y +CONFIG_CPU_LITTLE_ENDIAN=y +CONFIG_CPU_MITIGATIONS=y +CONFIG_CPU_PABRT_V7=y +CONFIG_CPU_PM=y +CONFIG_CPU_RMAP=y +CONFIG_CPU_SPECTRE=y +CONFIG_CPU_THUMB_CAPABLE=y +CONFIG_CPU_TLB_V7=y +CONFIG_CPU_V7=y +CONFIG_CRC16=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_CRYPTO_CRC32C=y +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y +CONFIG_CRYPTO_LIB_GF128MUL=y +CONFIG_CRYPTO_LIB_SHA1=y +CONFIG_CRYPTO_LIB_UTILS=y +CONFIG_CRYPTO_SHA1=y +CONFIG_CURRENT_POINTER_IN_TPIDRURO=y +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_DEBUG_ALIGN_RODATA=y +CONFIG_DEBUG_INFO=y +CONFIG_DEBUG_LL_INCLUDE="mach/debug-macro.S" +CONFIG_DEVFREQ_GOV_PASSIVE=y +# CONFIG_DEVFREQ_GOV_PERFORMANCE is not set +# CONFIG_DEVFREQ_GOV_POWERSAVE is not set +CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y +# CONFIG_DEVFREQ_GOV_USERSPACE is not set +CONFIG_DMADEVICES=y +CONFIG_DMA_CMA=y +CONFIG_DMA_ENGINE=y +CONFIG_DMA_OF=y +CONFIG_DMA_OPS=y +CONFIG_DMA_SHARED_BUFFER=y +CONFIG_DMA_VIRTUAL_CHANNELS=y +CONFIG_DNOTIFY=y +CONFIG_DTC=y +CONFIG_DT_IDLE_GENPD=y +CONFIG_DT_IDLE_STATES=y +CONFIG_DUMMY_CONSOLE=y +CONFIG_DWMAC_DWC_QOS_ETH=y +CONFIG_DWMAC_GENERIC=y +CONFIG_DWMAC_STM32=y +CONFIG_DW_DMAC=y +CONFIG_DW_DMAC_CORE=y +CONFIG_EDAC=y +CONFIG_EDAC_ATOMIC_SCRUB=y +# CONFIG_EDAC_DEBUG is not set +CONFIG_EDAC_LEGACY_SYSFS=y +CONFIG_EDAC_SUPPORT=y +CONFIG_ELF_CORE=y +CONFIG_EXCLUSIVE_SYSTEM_RAM=y +CONFIG_EXT4_FS=y +CONFIG_FIXED_PHY=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_FREEZER=y +CONFIG_FS_IOMAP=y +CONFIG_FS_MBCACHE=y +CONFIG_FUNCTION_ALIGNMENT=0 +CONFIG_FWNODE_MDIO=y +CONFIG_FW_CACHE=y +# CONFIG_FW_LOADER_USER_HELPER is not set +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_GENERIC_ARCH_TOPOLOGY=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_GENERIC_EARLY_IOREMAP=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_IDLE_POLL_SETUP=y +CONFIG_GENERIC_IRQ_CHIP=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_GENERIC_IRQ_MULTI_HANDLER=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_SHOW_LEVEL=y +CONFIG_GENERIC_LIB_DEVMEM_IS_ALLOWED=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_PHY=y +CONFIG_GENERIC_PINCONF=y +CONFIG_GENERIC_PINCTRL_GROUPS=y +CONFIG_GENERIC_PINMUX_FUNCTIONS=y +CONFIG_GENERIC_SCHED_CLOCK=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_VDSO_32=y +CONFIG_GLOB=y +CONFIG_GPIOLIB_IRQCHIP=y +CONFIG_GPIO_CDEV=y +CONFIG_GPIO_GENERIC=y +CONFIG_GPIO_GENERIC_PLATFORM=y +CONFIG_GPIO_SYSCON=y +# CONFIG_GPIO_SYSFS is not set +CONFIG_HARDEN_BRANCH_PREDICTOR=y +CONFIG_HARDIRQS_SW_RESEND=y +CONFIG_HAS_DMA=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAVE_SMP=y +CONFIG_HIGHMEM=y +CONFIG_HIGHPTE=y +CONFIG_HOTPLUG_CORE_SYNC=y +CONFIG_HOTPLUG_CORE_SYNC_DEAD=y +CONFIG_HOTPLUG_CPU=y +CONFIG_HW_CONSOLE=y +CONFIG_HW_RANDOM=y +CONFIG_HW_RANDOM_OPTEE=y +CONFIG_HW_RANDOM_STM32=y +CONFIG_HZ_FIXED=0 +CONFIG_I2C=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_COMPAT=y +CONFIG_I2C_DEMUX_PINCTRL=y +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_GPIO=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_MUX_PINCTRL=y +CONFIG_I2C_SLAVE=y +# CONFIG_I2C_SLAVE_TESTUNIT is not set +CONFIG_I2C_SMBUS=y +# CONFIG_I2C_STM32F4 is not set +CONFIG_I2C_STM32F7=y +CONFIG_INPUT=y +# CONFIG_INPUT_STPMIC1_ONKEY is not set +# CONFIG_IOMMUFD is not set +# CONFIG_IOMMU_DEBUGFS is not set +CONFIG_IOMMU_IO_PGTABLE=y +# CONFIG_IOMMU_IO_PGTABLE_ARMV7S is not set +CONFIG_IOMMU_IO_PGTABLE_LPAE=y +# CONFIG_IOMMU_IO_PGTABLE_LPAE_SELFTEST is not set +CONFIG_IOMMU_SUPPORT=y +CONFIG_IRQCHIP=y +CONFIG_IRQSTACKS=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_IRQ_WORK=y +CONFIG_JBD2=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_XZ is not set +CONFIG_KMAP_LOCAL=y +CONFIG_KMAP_LOCAL_NON_LINEAR_PTE_ARRAY=y +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LIBFDT=y +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_LOG_BUF_SHIFT=16 +# CONFIG_LRU_GEN is not set +CONFIG_LZO_DECOMPRESS=y +CONFIG_MACH_STM32MP13=y +CONFIG_MACH_STM32MP157=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MDIO_BITBANG=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_GPIO is not set +CONFIG_MEMORY=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_MFD_CORE=y +# CONFIG_MFD_STM32_LPTIMER is not set +# CONFIG_MFD_STM32_TIMERS is not set +CONFIG_MFD_STPMIC1=y +CONFIG_MFD_SYSCON=y +CONFIG_MIGHT_HAVE_CACHE_L2X0=y +CONFIG_MIGRATION=y +CONFIG_MMC=y +CONFIG_MMC_ARMMMCI=y +CONFIG_MMC_BLOCK=y +CONFIG_MMC_BLOCK_MINORS=16 +CONFIG_MMC_STM32_SDMMC=y +CONFIG_MMU_LAZY_TLB_REFCOUNT=y +CONFIG_MODULES_USE_ELF_REL=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_NEED_SRCU_NMI_SAFE=y +CONFIG_NEON=y +CONFIG_NET_EGRESS=y +CONFIG_NET_FLOW_LIMIT=y +CONFIG_NET_INGRESS=y +CONFIG_NET_PTP_CLASSIFY=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_XGRESS=y +CONFIG_NO_HZ_COMMON=y +CONFIG_NO_HZ_IDLE=y +CONFIG_NR_CPUS=2 +CONFIG_OF=y +CONFIG_OF_ADDRESS=y +CONFIG_OF_DYNAMIC=y +CONFIG_OF_EARLY_FLATTREE=y +CONFIG_OF_FLATTREE=y +CONFIG_OF_GPIO=y +CONFIG_OF_IRQ=y +CONFIG_OF_KOBJ=y +CONFIG_OF_MDIO=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_RESOLVE=y +CONFIG_OLD_SIGACTION=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_OPTEE=y +CONFIG_PADATA=y +CONFIG_PAGE_OFFSET=0xC0000000 +CONFIG_PAGE_POOL=y +CONFIG_PAGE_POOL_STATS=y +CONFIG_PAGE_SIZE_LESS_THAN_256KB=y +CONFIG_PAGE_SIZE_LESS_THAN_64KB=y +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_PCS_XPCS=y +CONFIG_PERF_USE_VMALLOC=y +CONFIG_PGTABLE_LEVELS=2 +CONFIG_PHYLIB=y +CONFIG_PHYLIB_LEDS=y +CONFIG_PHYLINK=y +# CONFIG_PHY_STM32_USBPHYC is not set +CONFIG_PINCTRL=y +CONFIG_PINCTRL_MCP23S08=y +CONFIG_PINCTRL_MCP23S08_I2C=y +CONFIG_PINCTRL_STM32=y +CONFIG_PINCTRL_STM32MP135=y +CONFIG_PINCTRL_STM32MP157=y +# CONFIG_PL353_SMC is not set +CONFIG_PM=y +CONFIG_PM_CLK=y +CONFIG_PM_DEVFREQ=y +CONFIG_PM_DEVFREQ_EVENT=y +CONFIG_PM_GENERIC_DOMAINS=y +CONFIG_PM_GENERIC_DOMAINS_OF=y +CONFIG_PM_GENERIC_DOMAINS_SLEEP=y +CONFIG_PM_OPP=y +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO=y +CONFIG_POWER_RESET_GPIO_RESTART=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_POWER_RESET_SYSCON_POWEROFF=y +CONFIG_POWER_SUPPLY=y +CONFIG_PPS=y +CONFIG_PREEMPT_NONE_BUILD=y +CONFIG_PRINTK_TIME=y +CONFIG_PTP_1588_CLOCK=y +CONFIG_PTP_1588_CLOCK_OPTIONAL=y +CONFIG_RANDSTRUCT_NONE=y +CONFIG_RAS=y +CONFIG_RATIONAL=y +# CONFIG_RAVE_SP_CORE is not set +CONFIG_REALTEK_PHY=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_REGMAP_IRQ=y +CONFIG_REGMAP_MMIO=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_ARM_SCMI=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_REGULATOR_STM32_BOOSTER is not set +CONFIG_REGULATOR_STM32_PWR=y +# CONFIG_REGULATOR_STM32_VREFBUF is not set +CONFIG_REGULATOR_STPMIC1=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_SCMI=y +CONFIG_RESET_SIMPLE=y +CONFIG_RFS_ACCEL=y +CONFIG_RPS=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_DRV_CMOS is not set +# CONFIG_RTC_DRV_OPTEE is not set +CONFIG_RTC_DRV_STM32=y +CONFIG_RTC_I2C_AND_SPI=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_SCSI=y +CONFIG_SCSI_COMMON=y +# CONFIG_SERIAL_8250 is not set +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +CONFIG_SERIAL_DEV_CTRL_TTYPORT=y +CONFIG_SERIAL_MCTRL_GPIO=y +CONFIG_SERIAL_STM32=y +CONFIG_SERIAL_STM32_CONSOLE=y +CONFIG_SERIO=y +CONFIG_SERIO_LIBPS2=y +CONFIG_SERIO_SERPORT=y +CONFIG_SGL_ALLOC=y +CONFIG_SG_POOL=y +CONFIG_SMP=y +CONFIG_SMP_ON_UP=y +CONFIG_SMSC_PHY=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y +CONFIG_SOC_BUS=y +CONFIG_SOFTIRQ_ON_OWN_STACK=y +CONFIG_SPARSE_IRQ=y +CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y +# CONFIG_SQUASHFS_EMBEDDED is not set +CONFIG_SQUASHFS_FILE_CACHE=y +# CONFIG_SQUASHFS_FILE_DIRECT is not set +CONFIG_SQUASHFS_LZO=y +CONFIG_SQUASHFS_ZLIB=y +CONFIG_STM32_DMA=y +CONFIG_STM32_DMAMUX=y +CONFIG_STM32_EXTI=y +# CONFIG_STM32_FMC2_EBI is not set +CONFIG_STM32_MDMA=y +CONFIG_STM32_WATCHDOG=y +CONFIG_STMMAC_ETH=y +CONFIG_STMMAC_PLATFORM=y +# CONFIG_STPMIC1_WATCHDOG is not set +# CONFIG_STRIP_ASM_SYMS is not set +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +CONFIG_SWPHY=y +CONFIG_SWP_EMULATE=y +CONFIG_SYS_SUPPORTS_APM_EMULATION=y +CONFIG_TEE=y +CONFIG_THREAD_INFO_IN_TASK=y +CONFIG_TICK_CPU_ACCOUNTING=y +CONFIG_TIMER_OF=y +CONFIG_TIMER_PROBE=y +CONFIG_TREE_RCU=y +CONFIG_TREE_SRCU=y +CONFIG_TRUSTED_FOUNDATIONS=y +# CONFIG_UCLAMP_TASK is not set +# CONFIG_UEVENT_HELPER is not set +CONFIG_UNCOMPRESS_INCLUDE="debug/uncompress.h" +CONFIG_UNWINDER_ARM=y +CONFIG_USB_SUPPORT=y +CONFIG_USELIB=y +CONFIG_USE_OF=y +CONFIG_VFP=y +CONFIG_VFPv3=y +CONFIG_VMAP_STACK=y +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_VT=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_WATCHDOG_CORE=y +# CONFIG_WQ_POWER_EFFICIENT_DEFAULT is not set +CONFIG_XPS=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_BCJ=y +CONFIG_ZBOOT_ROM_BSS=0x0 +CONFIG_ZBOOT_ROM_TEXT=0x0 +CONFIG_ZLIB_DEFLATE=y +CONFIG_ZLIB_INFLATE=y