From: Julian Seward <jseward@acm.org>
Date: Thu, 20 Aug 2015 16:17:11 +0000 (+0000)
Subject: Implement reading from PMUSERENR_EL0, making it return zero.
X-Git-Tag: svn/VALGRIND_3_11_0^2~12
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=250508031a594eaaa65890421cafd2d5205cf958;p=thirdparty%2Fvalgrind.git

Implement reading from PMUSERENR_EL0, making it return zero.
Fixes (for some definition of "fix") #345984.


git-svn-id: svn://svn.valgrind.org/vex/trunk@3179
---

diff --git a/VEX/priv/guest_arm_toIR.c b/VEX/priv/guest_arm_toIR.c
index d05276408f..91a9d4bfb0 100644
--- a/VEX/priv/guest_arm_toIR.c
+++ b/VEX/priv/guest_arm_toIR.c
@@ -17218,7 +17218,7 @@ DisResult disInstr_ARM_WRK (
    /* ----------------------------------------------------------- */
 
    /* -------------- read CP15 TPIDRURO register ------------- */
-   /* mrc     p15, 0, r0, c13, c0, 3  up to
+   /* mrc     p15, 0, r0,  c13, c0, 3  up to
       mrc     p15, 0, r14, c13, c0, 3
    */
    /* I don't know whether this is really v7-only.  But anyway, we
@@ -17236,6 +17236,25 @@ DisResult disInstr_ARM_WRK (
       /* fall through */
    }
 
+   /* -------------- read CP15 PMUSRENR register ------------- */
+   /* mrc     p15, 0, r0,  c9, c14, 0  up to
+      mrc     p15, 0, r14, c9, c14, 0
+   */
+   /* A program reading this register is really asking "which
+      performance monitoring registes are available in user space?
+      The simple answer here is to return zero, meaning "none".  See
+      #345984. */
+   if (0x0E190F1E == (insn & 0x0FFF0FFF)) {
+      UInt rD = INSN(15,12);
+      if (rD <= 14) {
+         /* skip r15, that's too stupid to handle */
+         putIRegA(rD, mkU32(0), condT, Ijk_Boring);
+         DIP("mrc%s p15,0, r%u, c9, c14, 0\n", nCC(INSN_COND), rD);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+
    /* Handle various kinds of barriers.  This is rather indiscriminate
       in the sense that they are all turned into an IR Fence, which
       means we don't know which they are, so the back end has to
@@ -21615,6 +21634,22 @@ DisResult disInstr_THUMB_WRK (
       /* fall through */
    }
 
+   /* -------------- read CP15 PMUSRENR register ------------- */
+   /* mrc     p15, 0, r0,  c9, c14, 0  up to
+      mrc     p15, 0, r14, c9, c14, 0
+      See comment on the ARM equivalent of this (above) for details.
+   */
+   if ((INSN0(15,0) == 0xEE19) && (INSN1(11,0) == 0x0F1E)) {
+      /* FIXME: should this be unconditional? */
+      UInt rD = INSN1(15,12);
+      if (!isBadRegT(rD)) {
+         putIRegT(rD, mkU32(0), IRTemp_INVALID);
+         DIP("mrc p15,0, r%u, c9, c14, 0\n", rD);
+         goto decode_success;
+      }
+      /* fall through */
+   }
+
    /* ------------------- CLREX ------------------ */
    if (INSN0(15,0) == 0xF3BF && INSN1(15,0) == 0x8F2F) {
       /* AFAICS, this simply cancels a (all?) reservations made by a