From: Joern Rennecke <joern.rennecke@embecosm.com>
Date: Fri, 19 May 2023 22:18:42 +0000 (-0600)
Subject: RISC-V: Remove masking third operand of rotate instructions
X-Git-Tag: basepoints/gcc-15~9136
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=259b4b7d349dd3fd560144bd4617f526458b45dc;p=thirdparty%2Fgcc.git

RISC-V: Remove masking third operand of rotate instructions

Sorry, I forgot the ChangeLog entry for my patch and missed the [v2]
part of the subject.

2023-05-18  Joern Rennecke  <joern.rennecke@embecosm.com>

gcc/ChangeLog:
	* config/riscv/constraints.md (DsS, DsD): Restore agreement
	with shiftm1 mode attribute.
---

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index c448e6b37e93..44525b2da491 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -65,13 +65,13 @@
   "@internal
    31 immediate"
   (and (match_code "const_int")
-       (match_test "ival == 31")))
+       (match_test "(ival & 31) == 31")))
 
 (define_constraint "DsD"
   "@internal
    63 immediate"
   (and (match_code "const_int")
-       (match_test "ival == 63")))
+       (match_test "(ival & 63) == 63")))
 
 (define_constraint "DbS"
   "@internal"