From: Greg Kroah-Hartman Date: Thu, 18 Dec 2025 12:02:34 +0000 (+0100) Subject: 5.15-stable patches X-Git-Tag: v6.12.63~4 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=263a7382ac1a604c565e70827a983902b41e3100;p=thirdparty%2Fkernel%2Fstable-queue.git 5.15-stable patches added patches: asoc-fsl_xcvr-get-channel-status-data-when-phy-is-not-exists.patch coresight-etm4x-correct-polling-idle-bit.patch netfilter-nf_conncount-garbage-collection-is-not-skipped-when-jiffies-wrap-around.patch nfs-fix-missing-unlock-in-nfs_unlink.patch spi-tegra210-quad-fix-validate-combined-sequence.patch spi-tegra210-quad-fix-x1_x2_x4-encoding-and-support-x4-transfers.patch --- diff --git a/queue-5.15/asoc-fsl_xcvr-get-channel-status-data-when-phy-is-not-exists.patch b/queue-5.15/asoc-fsl_xcvr-get-channel-status-data-when-phy-is-not-exists.patch new file mode 100644 index 0000000000..49ca1d22ef --- /dev/null +++ b/queue-5.15/asoc-fsl_xcvr-get-channel-status-data-when-phy-is-not-exists.patch @@ -0,0 +1,51 @@ +From ca592e20659e0304ebd8f4dabb273da4f9385848 Mon Sep 17 00:00:00 2001 +From: Shengjiu Wang +Date: Thu, 10 Jul 2025 11:04:04 +0800 +Subject: ASoC: fsl_xcvr: get channel status data when PHY is not exists + +From: Shengjiu Wang + +commit ca592e20659e0304ebd8f4dabb273da4f9385848 upstream. + +There is no PHY for the XCVR module on i.MX93, the channel status needs +to be obtained from FSL_XCVR_RX_CS_DATA_* registers. And channel status +acknowledge (CSA) bit should be set once channel status is processed. + +Fixes: e240b9329a30 ("ASoC: fsl_xcvr: Add support for i.MX93 platform") +Signed-off-by: Shengjiu Wang +Link: https://patch.msgid.link/20250710030405.3370671-2-shengjiu.wang@nxp.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + sound/soc/fsl/fsl_xcvr.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +--- a/sound/soc/fsl/fsl_xcvr.c ++++ b/sound/soc/fsl/fsl_xcvr.c +@@ -1165,6 +1165,26 @@ static irqreturn_t irq0_isr(int irq, voi + /* clear CS control register */ + writel_relaxed(0, reg_ctrl); + } ++ } else { ++ regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_0, ++ (u32 *)&xcvr->rx_iec958.status[0]); ++ regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_1, ++ (u32 *)&xcvr->rx_iec958.status[4]); ++ regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_2, ++ (u32 *)&xcvr->rx_iec958.status[8]); ++ regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_3, ++ (u32 *)&xcvr->rx_iec958.status[12]); ++ regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_4, ++ (u32 *)&xcvr->rx_iec958.status[16]); ++ regmap_read(xcvr->regmap, FSL_XCVR_RX_CS_DATA_5, ++ (u32 *)&xcvr->rx_iec958.status[20]); ++ for (i = 0; i < 6; i++) { ++ val = *(u32 *)(xcvr->rx_iec958.status + i * 4); ++ *(u32 *)(xcvr->rx_iec958.status + i * 4) = ++ bitrev32(val); ++ } ++ regmap_set_bits(xcvr->regmap, FSL_XCVR_RX_DPTH_CTRL, ++ FSL_XCVR_RX_DPTH_CTRL_CSA); + } + } + if (isr & FSL_XCVR_IRQ_NEW_UD) { diff --git a/queue-5.15/coresight-etm4x-correct-polling-idle-bit.patch b/queue-5.15/coresight-etm4x-correct-polling-idle-bit.patch new file mode 100644 index 0000000000..3c46c3d7d9 --- /dev/null +++ b/queue-5.15/coresight-etm4x-correct-polling-idle-bit.patch @@ -0,0 +1,38 @@ +From 4dc4e22f9536341255f5de6047977a80ff47eaef Mon Sep 17 00:00:00 2001 +From: Leo Yan +Date: Tue, 11 Nov 2025 18:58:38 +0000 +Subject: coresight: etm4x: Correct polling IDLE bit + +From: Leo Yan + +commit 4dc4e22f9536341255f5de6047977a80ff47eaef upstream. + +Since commit 4ff6039ffb79 ("coresight-etm4x: add isb() before reading +the TRCSTATR"), the code has incorrectly been polling the PMSTABLE bit +instead of the IDLE bit. + +This commit corrects the typo. + +Fixes: 4ff6039ffb79 ("coresight-etm4x: add isb() before reading the TRCSTATR") +Reviewed-by: Yeoreum Yun +Reviewed-by: Mike Leach +Tested-by: James Clark +Signed-off-by: Leo Yan +Signed-off-by: Suzuki K Poulose +Link: https://lore.kernel.org/r/20251111-arm_coresight_power_management_fix-v6-4-f55553b6c8b3@arm.com +Signed-off-by: Greg Kroah-Hartman +--- + drivers/hwtracing/coresight/coresight-etm4x-core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c ++++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c +@@ -1761,7 +1761,7 @@ static int __etm4_cpu_save(struct etmv4_ + state->trcpdcr = etm4x_read32(csa, TRCPDCR); + + /* wait for TRCSTATR.IDLE to go up */ +- if (etm4x_wait_status(csa, TRCSTATR_PMSTABLE_BIT, 1)) { ++ if (etm4x_wait_status(csa, TRCSTATR_IDLE_BIT, 1)) { + dev_err(etm_dev, + "timeout while waiting for Idle Trace Status\n"); + etm4_os_unlock(drvdata); diff --git a/queue-5.15/netfilter-nf_conncount-garbage-collection-is-not-skipped-when-jiffies-wrap-around.patch b/queue-5.15/netfilter-nf_conncount-garbage-collection-is-not-skipped-when-jiffies-wrap-around.patch new file mode 100644 index 0000000000..68e12ad2f7 --- /dev/null +++ b/queue-5.15/netfilter-nf_conncount-garbage-collection-is-not-skipped-when-jiffies-wrap-around.patch @@ -0,0 +1,49 @@ +From df08c94baafb001de6cf44bb7098bb557f36c335 Mon Sep 17 00:00:00 2001 +From: Nicklas Bo Jensen +Date: Thu, 27 Feb 2025 13:32:34 +0000 +Subject: netfilter: nf_conncount: garbage collection is not skipped when jiffies wrap around + +From: Nicklas Bo Jensen + +commit df08c94baafb001de6cf44bb7098bb557f36c335 upstream. + +nf_conncount is supposed to skip garbage collection if it has already +run garbage collection in the same jiffy. Unfortunately, this is broken +when jiffies wrap around which this patch fixes. + +The problem is that last_gc in the nf_conncount_list struct is an u32, +but jiffies is an unsigned long which is 8 bytes on my systems. When +those two are compared it only works until last_gc wraps around. + +See bug report: https://bugzilla.netfilter.org/show_bug.cgi?id=1778 +for more details. + +Fixes: d265929930e2 ("netfilter: nf_conncount: reduce unnecessary GC") +Signed-off-by: Nicklas Bo Jensen +Reviewed-by: Florian Westphal +Signed-off-by: Pablo Neira Ayuso +Signed-off-by: Greg Kroah-Hartman +--- + net/netfilter/nf_conncount.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/net/netfilter/nf_conncount.c ++++ b/net/netfilter/nf_conncount.c +@@ -182,7 +182,7 @@ static int __nf_conncount_add(struct net + return -EEXIST; + } + +- if (time_is_after_eq_jiffies((unsigned long)list->last_gc)) ++ if ((u32)jiffies == list->last_gc) + goto add_new_node; + + /* check the saved connections */ +@@ -288,7 +288,7 @@ bool nf_conncount_gc_list(struct net *ne + bool ret = false; + + /* don't bother if we just did GC */ +- if (time_is_after_eq_jiffies((unsigned long)READ_ONCE(list->last_gc))) ++ if ((u32)jiffies == READ_ONCE(list->last_gc)) + return false; + + /* don't bother if other cpu is already doing GC */ diff --git a/queue-5.15/nfs-fix-missing-unlock-in-nfs_unlink.patch b/queue-5.15/nfs-fix-missing-unlock-in-nfs_unlink.patch new file mode 100644 index 0000000000..4e793a1644 --- /dev/null +++ b/queue-5.15/nfs-fix-missing-unlock-in-nfs_unlink.patch @@ -0,0 +1,33 @@ +From 2067231a9e2cbbcae0a4aca6ac36ff2dd6a7b701 Mon Sep 17 00:00:00 2001 +From: Sun Ke +Date: Fri, 12 Aug 2022 09:14:40 +0800 +Subject: NFS: Fix missing unlock in nfs_unlink() + +From: Sun Ke + +commit 2067231a9e2cbbcae0a4aca6ac36ff2dd6a7b701 upstream. + +Add the missing unlock before goto. + +Fixes: 3c59366c207e ("NFS: don't unhash dentry during unlink/rename") +Signed-off-by: Sun Ke +Signed-off-by: Trond Myklebust +Signed-off-by: Greg Kroah-Hartman +--- + fs/nfs/dir.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/fs/nfs/dir.c ++++ b/fs/nfs/dir.c +@@ -2331,8 +2331,10 @@ int nfs_unlink(struct inode *dir, struct + */ + error = -ETXTBSY; + if (WARN_ON(dentry->d_flags & DCACHE_NFSFS_RENAMED) || +- WARN_ON(dentry->d_fsdata == NFS_FSDATA_BLOCKED)) ++ WARN_ON(dentry->d_fsdata == NFS_FSDATA_BLOCKED)) { ++ spin_unlock(&dentry->d_lock); + goto out; ++ } + if (dentry->d_fsdata) + /* old devname */ + kfree(dentry->d_fsdata); diff --git a/queue-5.15/series b/queue-5.15/series index f528476557..3fee4b05e3 100644 --- a/queue-5.15/series +++ b/queue-5.15/series @@ -198,3 +198,9 @@ ocfs2-fix-memory-leak-in-ocfs2_merge_rec_left.patch usb-gadget-tegra-xudc-always-reinitialize-data-toggle-when-clear-halt.patch usb-phy-initialize-struct-usb_phy-list_head.patch alsa-dice-fix-buffer-overflow-in-detect_stream_formats.patch +asoc-fsl_xcvr-get-channel-status-data-when-phy-is-not-exists.patch +nfs-fix-missing-unlock-in-nfs_unlink.patch +netfilter-nf_conncount-garbage-collection-is-not-skipped-when-jiffies-wrap-around.patch +coresight-etm4x-correct-polling-idle-bit.patch +spi-tegra210-quad-fix-validate-combined-sequence.patch +spi-tegra210-quad-fix-x1_x2_x4-encoding-and-support-x4-transfers.patch diff --git a/queue-5.15/spi-tegra210-quad-fix-validate-combined-sequence.patch b/queue-5.15/spi-tegra210-quad-fix-validate-combined-sequence.patch new file mode 100644 index 0000000000..ce5f8d296c --- /dev/null +++ b/queue-5.15/spi-tegra210-quad-fix-validate-combined-sequence.patch @@ -0,0 +1,33 @@ +From 047ee71ae4f412d8819e39e4b08c588fa299cfc2 Mon Sep 17 00:00:00 2001 +From: Krishna Yarlagadda +Date: Fri, 24 Feb 2023 22:10:34 +0530 +Subject: spi: tegra210-quad: Fix validate combined sequence + +From: Krishna Yarlagadda + +commit 047ee71ae4f412d8819e39e4b08c588fa299cfc2 upstream. + +Check for non dma transfers that do not fit in FIFO has issue and skips +combined sequence for Tegra234 & Tegra241 which does not have GPCDMA. + +Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") + +Signed-off-by: Krishna Yarlagadda +Link: https://lore.kernel.org/r/20230224164034.56933-1-kyarlagadda@nvidia.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + drivers/spi/spi-tegra210-quad.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/spi/spi-tegra210-quad.c ++++ b/drivers/spi/spi-tegra210-quad.c +@@ -1290,7 +1290,7 @@ static bool tegra_qspi_validate_cmb_seq( + if (xfer->len > 4 || xfer->len < 3) + return false; + xfer = list_next_entry(xfer, transfer_list); +- if (!tqspi->soc_data->has_dma || xfer->len > (QSPI_FIFO_DEPTH << 2)) ++ if (!tqspi->soc_data->has_dma && xfer->len > (QSPI_FIFO_DEPTH << 2)) + return false; + + return true; diff --git a/queue-5.15/spi-tegra210-quad-fix-x1_x2_x4-encoding-and-support-x4-transfers.patch b/queue-5.15/spi-tegra210-quad-fix-x1_x2_x4-encoding-and-support-x4-transfers.patch new file mode 100644 index 0000000000..e7442ef03a --- /dev/null +++ b/queue-5.15/spi-tegra210-quad-fix-x1_x2_x4-encoding-and-support-x4-transfers.patch @@ -0,0 +1,80 @@ +From dcb06c638a1174008a985849fa30fc0da7d08904 Mon Sep 17 00:00:00 2001 +From: Vishwaroop A +Date: Wed, 16 Apr 2025 11:06:01 +0000 +Subject: spi: tegra210-quad: Fix X1_X2_X4 encoding and support x4 transfers + +From: Vishwaroop A + +commit dcb06c638a1174008a985849fa30fc0da7d08904 upstream. + +This patch corrects the QSPI_COMMAND_X1_X2_X4 and QSPI_ADDRESS_X1_X2_X4 +macros to properly encode the bus width for x1, x2, and x4 transfers. +Although these macros were previously incorrect, they were not being +used in the driver, so no functionality was affected. + +The patch updates tegra_qspi_cmd_config() and tegra_qspi_addr_config() +function calls to use the actual bus width from the transfer, instead of +hardcoding it to 0 (which implied x1 mode). This change enables proper +support for x1, x2, and x4 data transfers by correctly configuring the +interface width for commands and addresses. + +These modifications improve the QSPI driver's flexibility and prepare it +for future use cases that may require different bus widths for commands +and addresses. + +Fixes: 1b8342cc4a38 ("spi: tegra210-quad: combined sequence mode") +Signed-off-by: Vishwaroop A +Link: https://patch.msgid.link/20250416110606.2737315-2-va@nvidia.com +Signed-off-by: Mark Brown +Signed-off-by: Greg Kroah-Hartman +--- + drivers/spi/spi-tegra210-quad.c | 12 ++++-------- + 1 file changed, 4 insertions(+), 8 deletions(-) + +--- a/drivers/spi/spi-tegra210-quad.c ++++ b/drivers/spi/spi-tegra210-quad.c +@@ -123,7 +123,7 @@ + #define QSPI_COMMAND_VALUE_SET(X) (((x) & 0xFF) << 0) + + #define QSPI_CMB_SEQ_CMD_CFG 0x1a0 +-#define QSPI_COMMAND_X1_X2_X4(x) (((x) & 0x3) << 13) ++#define QSPI_COMMAND_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13) + #define QSPI_COMMAND_X1_X2_X4_MASK (0x03 << 13) + #define QSPI_COMMAND_SDR_DDR BIT(12) + #define QSPI_COMMAND_SIZE_SET(x) (((x) & 0xFF) << 0) +@@ -135,7 +135,7 @@ + #define QSPI_ADDRESS_VALUE_SET(X) (((x) & 0xFFFF) << 0) + + #define QSPI_CMB_SEQ_ADDR_CFG 0x1ac +-#define QSPI_ADDRESS_X1_X2_X4(x) (((x) & 0x3) << 13) ++#define QSPI_ADDRESS_X1_X2_X4(x) ((((x) >> 1) & 0x3) << 13) + #define QSPI_ADDRESS_X1_X2_X4_MASK (0x03 << 13) + #define QSPI_ADDRESS_SDR_DDR BIT(12) + #define QSPI_ADDRESS_SIZE_SET(x) (((x) & 0xFF) << 0) +@@ -1023,10 +1023,6 @@ static u32 tegra_qspi_addr_config(bool i + { + u32 addr_config = 0; + +- /* Extract Address configuration and value */ +- is_ddr = 0; //Only SDR mode supported +- bus_width = 0; //X1 mode +- + if (is_ddr) + addr_config |= QSPI_ADDRESS_SDR_DDR; + else +@@ -1060,13 +1056,13 @@ static int tegra_qspi_combined_seq_xfer( + switch (transfer_phase) { + case CMD_TRANSFER: + /* X1 SDR mode */ +- cmd_config = tegra_qspi_cmd_config(false, 0, ++ cmd_config = tegra_qspi_cmd_config(false, xfer->tx_nbits, + xfer->len); + cmd_value = *((const u8 *)(xfer->tx_buf)); + break; + case ADDR_TRANSFER: + /* X1 SDR mode */ +- addr_config = tegra_qspi_addr_config(false, 0, ++ addr_config = tegra_qspi_addr_config(false, xfer->tx_nbits, + xfer->len); + address_value = *((const u32 *)(xfer->tx_buf)); + break;