From: Jakub Kicinski Date: Sun, 14 Sep 2025 18:33:51 +0000 (-0700) Subject: Merge branch 'add-gmac-support-for-renesas-rz-t2h-n2h-socs' X-Git-Tag: v6.18-rc1~132^2~188 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=278289bcec901663868048497e36c92560bd1b14;p=thirdparty%2Flinux.git Merge branch 'add-gmac-support-for-renesas-rz-t2h-n2h-socs' Lad Prabhakar says: ==================== Add GMAC support for Renesas RZ/{T2H, N2H} SoCs This series adds support for the Ethernet MAC (GMAC) IP present on the Renesas RZ/T2H and RZ/N2H SoCs. While these SoCs use the same Synopsys DesignWare MAC IP (version 5.20) as the existing RZ/V2H(P), the hardware is synthesized with different options that require driver and binding updates: - 8 RX/TX queue pairs instead of 4 (requiring 19 interrupts vs 11) - Different clock requirements (3 clocks vs 7) - Different reset handling (2 named resets vs 1 unnamed) - Split header feature enabled - GMAC connected through a MIIC PCS on RZ/T2H The series first updates the generic dwmac binding to accommodate the higher interrupt count, then extends the Renesas-specific binding with a to document both SoCs. The driver changes prepare for multi-SoC support by introducing OF match data for per-SoC configuration, then add RZ/T2H support including PCS integration through the existing RZN1 MIIC driver. Note this patch series is dependent on the PCS driver [0] (not a build dependency). [0] https://lore.kernel.org/all/20250904114204.4148520-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ ==================== Link: https://patch.msgid.link/20250908105901.3198975-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski --- 278289bcec901663868048497e36c92560bd1b14