From: Andreas Krebbel <krebbel1@de.ibm.com>
Date: Tue, 26 Aug 2003 14:53:53 +0000 (+0000)
Subject: s390.md ("*llgt_sisi", [...]): New insns.
X-Git-Tag: releases/gcc-3.4.0~4060
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=288e517f6680f153e850413825d89bbb46f45e33;p=thirdparty%2Fgcc.git

s390.md ("*llgt_sisi", [...]): New insns.

	* config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
	"*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.

From-SVN: r70812
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 481a92659b6d..8fb59454caac 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2003-08-26  Andreas Krebbel <krebbel1@de.ibm.com>
+
+	* config/s390/s390.md ("*llgt_sisi", "*llgt_sisi_split", "*llgt_didi",
+	"*llgt_didi_split", "*llgt_sidi", "*llgt_sidi_split"): New insns.
+
 2003-08-26  Andreas Krebbel <krebbel1@de.ibm.com>
 
 	* config/s390/s390.md ("*fmadddf", "*fmsubdf", 
diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md
index d9e65439af06..fa7203df47ab 100644
--- a/gcc/config/s390/s390.md
+++ b/gcc/config/s390/s390.md
@@ -2439,6 +2439,77 @@
   "llgh\t%0,%1"
   [(set_attr "op_type" "RXY")])
 
+;
+; LLGT-type instructions (zero-extend from 31 bit to 64 bit).
+;
+
+(define_insn "*llgt_sisi"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+		(const_int 2147483647)))]
+  "TARGET_64BIT"
+  "@
+   llgtr\t%0,%1
+   llgt\t%0,%1"
+  [(set_attr "op_type"  "RRE,RXE")])
+
+(define_insn_and_split "*llgt_sisi_split"
+  [(set (match_operand:SI 0 "register_operand" "=d,d")
+        (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,m")
+		(const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:SI (match_dup 1)
+		(const_int 2147483647)))]
+  "")
+
+(define_insn "*llgt_didi"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+                (const_int 2147483647)))]
+  "TARGET_64BIT"
+  "@
+   llgtr\t%0,%1
+   llgt\t%0,%N1"
+  [(set_attr "op_type"  "RRE,RXE")])
+
+(define_insn_and_split "*llgt_didi_split"
+  [(set (match_operand:DI 0 "register_operand" "=d,d")
+        (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o")
+                (const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:DI (match_dup 1)
+                (const_int 2147483647)))]
+  "")
+
+(define_insn "*llgt_sidi"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0)
+		(const_int 2147483647)))]
+  "TARGET_64BIT"
+  "llgt\t%0,%1"
+  [(set_attr "op_type"  "RXE")])
+
+(define_insn_and_split "*llgt_sidi_split"
+  [(set (match_operand:DI 0 "register_operand" "=d")
+        (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "m") 0) 
+		(const_int 2147483647)))
+   (clobber (reg:CC 33))]
+  "TARGET_64BIT"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+        (and:DI (subreg:DI (match_dup 1) 0) 
+		(const_int 2147483647)))]
+  "")
+
 ;
 ; zero_extendqidi2 instruction pattern(s)
 ;