From: Julian Seward <jseward@acm.org>
Date: Wed, 18 Sep 2013 19:41:43 +0000 (+0000)
Subject: Add support for the Intel TM "xbegin" instruction, by jumping directly
X-Git-Tag: svn/VALGRIND_3_9_0^2~26
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=28fcbe6c38c52a3c9dfdd723cfcf964a47b10688;p=thirdparty%2Fvalgrind.git

Add support for the Intel TM "xbegin" instruction, by jumping directly
to the failure address.  Currently disabled pending finding hardware
that can actually execute xbegin, for testing purposes.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2769
---

diff --git a/VEX/priv/guest_amd64_toIR.c b/VEX/priv/guest_amd64_toIR.c
index 4fa83f9bcb..271f0fb928 100644
--- a/VEX/priv/guest_amd64_toIR.c
+++ b/VEX/priv/guest_amd64_toIR.c
@@ -20065,6 +20065,26 @@ Long dis_ESC_NONE (
          }
          return delta;
       }
+      /* BEGIN HACKY SUPPORT FOR xbegin */
+      if (0/*CURRENTLY DISABLED*/ &&
+          modrm == 0xF8 && !haveF2orF3(pfx) && sz == 4) {
+         delta++; /* mod/rm byte */
+         d64 = getSDisp(4,delta); 
+         delta += 4;
+         guest_RIP_next_mustcheck = True;
+         guest_RIP_next_assumed   = guest_RIP_bbstart + delta;
+         Addr64 failAddr = guest_RIP_bbstart + delta + d64;
+         /* EAX contains the failure status code.  Bit 3 is "Set if an
+            internal buffer overflowed", which seems like the
+            least-bogus choice we can make here. */
+         putIRegRAX(4, mkU32(1<<3));
+         /* And jump to the fail address. */
+         jmp_lit(dres, Ijk_Boring, failAddr);
+         vassert(dres->whatNext == Dis_StopHere);
+         DIP("xbeginq 0x%llx\n", failAddr);
+         return delta;
+      }
+      /* END HACKY SUPPORT FOR xbegin */
       goto decode_failure;
 
    case 0xC8: /* ENTER */