From: Jonathan Cameron Date: Sun, 8 May 2022 17:56:55 +0000 (+0100) Subject: iio: gyro: fxas210002c: Fix alignment for DMA safety X-Git-Tag: v5.18.18~438 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=29ff044557cc0096d960f05cd7db1766088d4c3e;p=thirdparty%2Fkernel%2Fstable.git iio: gyro: fxas210002c: Fix alignment for DMA safety [ Upstream commit 3aafe923987cb4a15e16f03c6185ed4b6a78ca00 ] ____cacheline_aligned is an insufficient guarantee for non-coherent DMA on platforms with 128 byte cachelines above L1. Switch to the updated IIO_DMA_MINALIGN definition. Updated the comment to 'may' require. Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c") Signed-off-by: Jonathan Cameron Reviewed-by: Rui Miguel Silva Acked-by: Nuno Sá Link: https://lore.kernel.org/r/20220508175712.647246-76-jic23@kernel.org Signed-off-by: Sasha Levin --- diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c index 410e5e9f2672e..7a459a823f6e1 100644 --- a/drivers/iio/gyro/fxas21002c_core.c +++ b/drivers/iio/gyro/fxas21002c_core.c @@ -150,10 +150,10 @@ struct fxas21002c_data { struct regulator *vddio; /* - * DMA (thus cache coherency maintenance) requires the - * transfer buffers to live in their own cache lines. + * DMA (thus cache coherency maintenance) may require the + * transfer buffers live in their own cache lines. */ - s16 buffer[8] ____cacheline_aligned; + s16 buffer[8] __aligned(IIO_DMA_MINALIGN); }; enum fxas21002c_channel_index {