From: Lad Prabhakar Date: Wed, 25 Jun 2025 14:17:03 +0000 (+0100) Subject: dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2a76193f7cc03de5b2745d069926ebc431dd5ba4;p=thirdparty%2Flinux.git dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock ID Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as a core clock for the SDHI IP and operates at 800MHz. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h index f6e5f62b07c4a..7ecc4f0b235aa 100644 --- a/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h @@ -24,5 +24,6 @@ #define R9A09G077_CLK_PCLKH 12 #define R9A09G077_CLK_PCLKM 13 #define R9A09G077_CLK_PCLKL 14 +#define R9A09G077_SDHI_CLKHS 15 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */ diff --git a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h index f28166d6015f4..925e57703925d 100644 --- a/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h +++ b/include/dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h @@ -24,5 +24,6 @@ #define R9A09G087_CLK_PCLKH 12 #define R9A09G087_CLK_PCLKM 13 #define R9A09G087_CLK_PCLKL 14 +#define R9A09G087_SDHI_CLKHS 15 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */