From: Juzhe-Zhong Date: Fri, 13 Oct 2023 05:45:19 +0000 (+0800) Subject: RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV X-Git-Tag: basepoints/gcc-15~5530 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2a89656a03282c0fe80c5467c6891c067ae0007a;p=thirdparty%2Fgcc.git RISC-V Regression: Fix FAIL of bb-slp-pr69907.c for RVV Like ARM SVE and GCN, add RVV. gcc/testsuite/ChangeLog: * gcc.dg/vect/bb-slp-pr69907.c: Add RVV. --- diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c index b348526b62f0..f63b42a271af 100644 --- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c +++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c @@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2) /* Disable for SVE because for long or variable-length vectors we don't get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD, because there we can vectorize the epilogue using mixed vector sizes. - Likewise for AMD GCN. */ -/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-* } } } } } */ + Likewise for AMD GCN and RVV. */ +/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { ! amdgcn*-*-* } && { ! riscv_v } } } } } } */