From: Tom Rini <trini@konsulko.com>
Date: Fri, 19 Dec 2025 16:30:53 +0000 (-0600)
Subject: Merge tag 'xilinx-for-v2026.04-rc1' of https://source.denx.de/u-boot/custodians/u... 
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2aeaa3c4f53b11b97e2797eb3a0a7b603f60dc72;p=thirdparty%2Fu-boot.git

Merge tag 'xilinx-for-v2026.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-microblaze into next

AMD/Xilinx/FPGA changes for v2026.04-rc1

xilinx:
- Sync ESRT with detected GUID
- DT cleanups
- Add logic for FRU information multiple times
- Enable more drivers pca9541, usb5744
- Enable more commands
- Cleanup firmware DT bindings

firmware:
- Add enhancement SMC format support

clk/versal:
- Various cleanups
- Add support for Versal Gen 2

i2c:
- cdns: Add timeout for RXDV status bit polling

spi:
- cadence: Remove cdns,is-dma DT property
- cadence: Remove duplicated return
- cadence_versal: Update flash reset delay

memtop:
- Update max memory reserved spaces to 64

Versal Gen 2:
- Aligned addresses with default memory map
- Add support for reading multiboot value

MB-V:
- Make SPL smaller
- Add support for SPI
- Move SPL to run out of BRAM

ZynqMP:
- Change default load address for BL32
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2aeaa3c4f53b11b97e2797eb3a0a7b603f60dc72