From: Alexander Ivchenko Date: Fri, 11 Oct 2013 12:53:24 +0000 (+0000) Subject: sse.md (_movnt): Update constraint to "v". X-Git-Tag: releases/gcc-4.9.0~3583 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2b1ebb0cfe7d39b18e44d583e57cfed5f2773f0d;p=thirdparty%2Fgcc.git sse.md (_movnt): Update constraint to "v". * config/i386/sse.md (_movnt): Update constraint to "v". (_comi): Ditto. (_ucomi): Ditto. (sse_cvtss2siq_2): Ditto. (sse2_cvtsd2si): Ditto. (sse2_cvtsd2siq): Ditto. (sse2_cvttsd2si): Ditto. (sse2_cvttsd2siq): Ditto. (3): Ditto. (sse2_cvtsi2sdq): Update constraint and prefix. (sse_cvtsi2ss): Update prefix. (sse_cvtsi2ssq): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin Co-Authored-By: Sergey Lega From-SVN: r203428 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 12753c600a69..168b1dbb29f9 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,26 @@ +2013-10-11 Alexander Ivchenko + Maxim Kuznetsov + Sergey Lega + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md (_movnt): Update constraint to "v". + (_comi): Ditto. + (_ucomi): Ditto. + (sse_cvtss2siq_2): Ditto. + (sse2_cvtsd2si): Ditto. + (sse2_cvtsd2siq): Ditto. + (sse2_cvttsd2si): Ditto. + (sse2_cvttsd2siq): Ditto. + (3): Ditto. + (sse2_cvtsi2sdq): Update constraint and prefix. + (sse_cvtsi2ss): Update prefix. + (sse_cvtsi2ssq): Ditto. + 2013-10-11 Jakub Jelinek * tree-vrp.c (infer_nonnull_range): Use is_gimple_call, diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 10637cc22e8b..2f2fb38f4285 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -880,7 +880,7 @@ (define_insn "_movnt" [(set (match_operand:VI8 0 "memory_operand" "=m") - (unspec:VI8 [(match_operand:VI8 1 "register_operand" "x")] + (unspec:VI8 [(match_operand:VI8 1 "register_operand" "v")] UNSPEC_MOVNT))] "TARGET_SSE2" "%vmovntdq\t{%1, %0|%0, %1}" @@ -1764,10 +1764,10 @@ [(set (reg:CCFP FLAGS_REG) (compare:CCFP (vec_select:MODEF - (match_operand: 0 "register_operand" "x") + (match_operand: 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand: 1 "nonimmediate_operand" "xm") + (match_operand: 1 "nonimmediate_operand" "vm") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (mode)" "%vcomi\t{%1, %0|%0, %1}" @@ -1784,10 +1784,10 @@ [(set (reg:CCFPU FLAGS_REG) (compare:CCFPU (vec_select:MODEF - (match_operand: 0 "register_operand" "x") + (match_operand: 0 "register_operand" "v") (parallel [(const_int 0)])) (vec_select:MODEF - (match_operand: 1 "nonimmediate_operand" "xm") + (match_operand: 1 "nonimmediate_operand" "vm") (parallel [(const_int 0)]))))] "SSE_FLOAT_MODE_P (mode)" "%vucomi\t{%1, %0|%0, %1}" @@ -2594,7 +2594,7 @@ (set_attr "amdfam10_decode" "vector,double,*") (set_attr "bdver1_decode" "double,direct,*") (set_attr "btver2_decode" "double,double,double") - (set_attr "prefix" "orig,orig,vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "SF")]) (define_insn "sse_cvtsi2ssq" @@ -2617,7 +2617,7 @@ (set_attr "btver2_decode" "double,double,double") (set_attr "length_vex" "*,*,4") (set_attr "prefix_rex" "1,1,*") - (set_attr "prefix" "orig,orig,vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "SF")]) (define_insn "sse_cvtss2si" @@ -2668,7 +2668,7 @@ (define_insn "sse_cvtss2siq_2" [(set (match_operand:DI 0 "register_operand" "=r,r") - (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")] + (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "v,m")] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE && TARGET_64BIT" "%vcvtss2si{q}\t{%1, %0|%0, %k1}" @@ -2860,11 +2860,11 @@ (set_attr "mode" "DF")]) (define_insn "sse2_cvtsi2sdq" - [(set (match_operand:V2DF 0 "register_operand" "=x,x,x") + [(set (match_operand:V2DF 0 "register_operand" "=x,x,v") (vec_merge:V2DF (vec_duplicate:V2DF (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m,rm"))) - (match_operand:V2DF 1 "register_operand" "0,0,x") + (match_operand:V2DF 1 "register_operand" "0,0,v") (const_int 1)))] "TARGET_SSE2 && TARGET_64BIT" "@ @@ -2878,14 +2878,14 @@ (set_attr "bdver1_decode" "double,direct,*") (set_attr "length_vex" "*,*,4") (set_attr "prefix_rex" "1,1,*") - (set_attr "prefix" "orig,orig,vex") + (set_attr "prefix" "orig,orig,maybe_evex") (set_attr "mode" "DF")]) (define_insn "sse2_cvtsd2si" [(set (match_operand:SI 0 "register_operand" "=r,r") (unspec:SI [(vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "x,m") + (match_operand:V2DF 1 "nonimmediate_operand" "v,m") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2" @@ -2916,7 +2916,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (unspec:DI [(vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "x,m") + (match_operand:V2DF 1 "nonimmediate_operand" "v,m") (parallel [(const_int 0)]))] UNSPEC_FIX_NOTRUNC))] "TARGET_SSE2 && TARGET_64BIT" @@ -2946,7 +2946,7 @@ [(set (match_operand:SI 0 "register_operand" "=r,r") (fix:SI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "x,m") + (match_operand:V2DF 1 "nonimmediate_operand" "v,m") (parallel [(const_int 0)]))))] "TARGET_SSE2" "%vcvttsd2si\t{%1, %0|%0, %q1}" @@ -2963,7 +2963,7 @@ [(set (match_operand:DI 0 "register_operand" "=r,r") (fix:DI (vec_select:DF - (match_operand:V2DF 1 "nonimmediate_operand" "x,m") + (match_operand:V2DF 1 "nonimmediate_operand" "v,m") (parallel [(const_int 0)]))))] "TARGET_SSE2 && TARGET_64BIT" "%vcvttsd2si{q}\t{%1, %0|%0, %q1}" @@ -5913,9 +5913,9 @@ (set_attr "mode" "")]) (define_insn "3" - [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,v") + [(set (match_operand:VI248_AVX2 0 "register_operand" "=x,x") (any_lshift:VI248_AVX2 - (match_operand:VI248_AVX2 1 "register_operand" "0,v") + (match_operand:VI248_AVX2 1 "register_operand" "0,x") (match_operand:SI 2 "nonmemory_operand" "xN,xN")))] "TARGET_SSE2" "@