From: Tim Harvey <tharvey@gateworks.com>
Date: Mon, 14 Jul 2025 17:23:03 +0000 (-0700)
Subject: venice: lpddr4_timing_imx8mm: update ddr phy config for mscale_v3.10
X-Git-Tag: v2025.10-rc1~53^2~1
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2c692bff83172b114329b2204b2fc8996e01ee7e;p=thirdparty%2Fu-boot.git

venice: lpddr4_timing_imx8mm: update ddr phy config for mscale_v3.10

Update the ddr phy config values to those created by the mscale_v3.10
tool. The original values were obtained using mscale_v3.10. The v3.10
tool removed ddr phy register values of 0x0.

This has no functional change but makes comparing and patching ddr
configuration easier in addition to slightly shrinking the DRAM config
size.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
---

diff --git a/board/gateworks/venice/lpddr4_timing_imx8mm.c b/board/gateworks/venice/lpddr4_timing_imx8mm.c
index a6025322e78..896a5c66eb6 100644
--- a/board/gateworks/venice/lpddr4_timing_imx8mm.c
+++ b/board/gateworks/venice/lpddr4_timing_imx8mm.c
@@ -2164,56 +2164,26 @@ static struct dram_cfg_param lpddr4_ddrphy_cfg_1gb[] = {
 /* P0 message block paremeter for training firmware */
 static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xbb8 },
 	{ 0x54004, 0x2 },
 	{ 0x54005, 0x2228 },
 	{ 0x54006, 0x11 },
-	{ 0x54007, 0x0 },
 	{ 0x54008, 0x131f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x110 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
 	{ 0x5401c, 0x4d00 },
-	{ 0x5401d, 0x0 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
 	{ 0x54022, 0x4d00 },
-	{ 0x54023, 0x0 },
 	{ 0x54024, 0x16 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
 	{ 0x54034, 0x6600 },
@@ -2226,69 +2196,33 @@ static struct dram_cfg_param lpddr4_fsp0_cfg_1gb[] = {
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
 	{ 0xd0000, 0x1 },
 };
 
 /* P1 message block paremeter for training firmware */
 static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x101 },
 	{ 0x54003, 0x190 },
 	{ 0x54004, 0x2 },
 	{ 0x54005, 0x2228 },
 	{ 0x54006, 0x11 },
-	{ 0x54007, 0x0 },
 	{ 0x54008, 0x121f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x110 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
 	{ 0x5401c, 0x4d00 },
-	{ 0x5401d, 0x0 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
 	{ 0x54022, 0x4d00 },
-	{ 0x54023, 0x0 },
 	{ 0x54024, 0x16 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
 	{ 0x54034, 0x6600 },
@@ -2301,69 +2235,33 @@ static struct dram_cfg_param lpddr4_fsp1_cfg_1gb[] = {
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
 	{ 0xd0000, 0x1 },
 };
 
 /* P2 message block paremeter for training firmware */
 static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
 	{ 0x54002, 0x102 },
 	{ 0x54003, 0x64 },
 	{ 0x54004, 0x2 },
 	{ 0x54005, 0x2228 },
 	{ 0x54006, 0x11 },
-	{ 0x54007, 0x0 },
 	{ 0x54008, 0x121f },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
-	{ 0x5400d, 0x0 },
-	{ 0x5400e, 0x0 },
-	{ 0x5400f, 0x0 },
-	{ 0x54010, 0x0 },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x110 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x84 },
 	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
 	{ 0x5401c, 0x4d00 },
-	{ 0x5401d, 0x0 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x84 },
 	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
 	{ 0x54022, 0x4d00 },
-	{ 0x54023, 0x0 },
 	{ 0x54024, 0x16 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0x8400 },
 	{ 0x54033, 0x3100 },
 	{ 0x54034, 0x6600 },
@@ -2376,69 +2274,35 @@ static struct dram_cfg_param lpddr4_fsp2_cfg_1gb[] = {
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
 	{ 0xd0000, 0x1 },
 };
 
 /* P0 2D message block paremeter for training firmware */
 static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
 	{ 0xd0000, 0x0 },
-	{ 0x54000, 0x0 },
-	{ 0x54001, 0x0 },
-	{ 0x54002, 0x0 },
 	{ 0x54003, 0xbb8 },
 	{ 0x54004, 0x2 },
 	{ 0x54005, 0x2228 },
 	{ 0x54006, 0x11 },
-	{ 0x54007, 0x0 },
 	{ 0x54008, 0x61 },
 	{ 0x54009, 0xc8 },
-	{ 0x5400a, 0x0 },
 	{ 0x5400b, 0x2 },
-	{ 0x5400c, 0x0 },
 	{ 0x5400d, 0x100 },
-	{ 0x5400e, 0x0 },
 	{ 0x5400f, 0x100 },
 	{ 0x54010, 0x1f7f },
-	{ 0x54011, 0x0 },
 	{ 0x54012, 0x110 },
-	{ 0x54013, 0x0 },
-	{ 0x54014, 0x0 },
-	{ 0x54015, 0x0 },
-	{ 0x54016, 0x0 },
-	{ 0x54017, 0x0 },
-	{ 0x54018, 0x0 },
 	{ 0x54019, 0x2dd4 },
 	{ 0x5401a, 0x31 },
 	{ 0x5401b, 0x4d66 },
 	{ 0x5401c, 0x4d00 },
-	{ 0x5401d, 0x0 },
 	{ 0x5401e, 0x16 },
 	{ 0x5401f, 0x2dd4 },
 	{ 0x54020, 0x31 },
 	{ 0x54021, 0x4d66 },
 	{ 0x54022, 0x4d00 },
-	{ 0x54023, 0x0 },
 	{ 0x54024, 0x16 },
-	{ 0x54025, 0x0 },
-	{ 0x54026, 0x0 },
-	{ 0x54027, 0x0 },
-	{ 0x54028, 0x0 },
-	{ 0x54029, 0x0 },
-	{ 0x5402a, 0x0 },
 	{ 0x5402b, 0x1000 },
 	{ 0x5402c, 0x1 },
-	{ 0x5402d, 0x0 },
-	{ 0x5402e, 0x0 },
-	{ 0x5402f, 0x0 },
-	{ 0x54030, 0x0 },
-	{ 0x54031, 0x0 },
 	{ 0x54032, 0xd400 },
 	{ 0x54033, 0x312d },
 	{ 0x54034, 0x6600 },
@@ -2451,13 +2315,6 @@ static struct dram_cfg_param lpddr4_fsp0_2d_cfg_1gb[] = {
 	{ 0x5403b, 0x4d },
 	{ 0x5403c, 0x4d },
 	{ 0x5403d, 0x1600 },
-	{ 0x5403e, 0x0 },
-	{ 0x5403f, 0x0 },
-	{ 0x54040, 0x0 },
-	{ 0x54041, 0x0 },
-	{ 0x54042, 0x0 },
-	{ 0x54043, 0x0 },
-	{ 0x54044, 0x0 },
 	{ 0xd0000, 0x1 },
 };