From: Tamar Christina <tamar.christina@arm.com>
Date: Mon, 25 Oct 2021 14:14:04 +0000 (+0100)
Subject: AArch64 testsuite: Force shrn-combine-*.c to use NEON.
X-Git-Tag: basepoints/gcc-13~3650
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2cbfaba60661ebbdfcffe725ab55fbb323e2a187;p=thirdparty%2Fgcc.git

AArch64 testsuite: Force shrn-combine-*.c to use NEON.

These tests are testing Advanced SIMD codegen, so if the compiler or the
testsuite is forcing SVE they will fail.

This adds +nosve so that we always generate Advanced SIMD codegen.

gcc/testsuite/ChangeLog:

	PR target/102907
	* gcc.target/aarch64/shrn-combine-1.c: Disable SVE.
	* gcc.target/aarch64/shrn-combine-2.c: Likewise.
	* gcc.target/aarch64/shrn-combine-3.c: Likewise.
	* gcc.target/aarch64/shrn-combine-4.c: Likewise.
	* gcc.target/aarch64/shrn-combine-5.c: Likewise.
	* gcc.target/aarch64/shrn-combine-6.c: Likewise.
	* gcc.target/aarch64/shrn-combine-7.c: Likewise.
---

diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
index a28524662edc..334e94aa76e0 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-1.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE char
 
 void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
index 012135b424f9..c90de72e9c39 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-2.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE short
 
 void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
index 8b5b360de623..a05ecbb373a5 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-3.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE int
 
 void foo (unsigned long long * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
index fedca7621e2a..36ebab7b742a 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-4.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE long long
 
 void foo (unsigned TYPE * restrict a, TYPE * restrict d, int n)
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
index 408e85535788..973e577e9381 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-5.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE1 char
 #define TYPE2 short
 #define SHIFT 8
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
index 6211ba3e41c1..db36a9c42181 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-6.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE1 short
 #define TYPE2 int
 #define SHIFT 16
diff --git a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
index 56cbeacc6de5..e7caf3c7587a 100644
--- a/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
+++ b/gcc/testsuite/gcc.target/aarch64/shrn-combine-7.c
@@ -1,6 +1,8 @@
 /* { dg-do assemble } */
 /* { dg-options "-O3 --save-temps --param=vect-epilogues-nomask=0" } */
 
+#pragma GCC target "+nosve"
+
 #define TYPE1 int
 #define TYPE2 long long
 #define SHIFT 32