From: Nicholas Nethercote Date: Thu, 20 Apr 2023 23:33:04 +0000 (+1000) Subject: Tweak printing of `I refs` and `D refs` lines. X-Git-Tag: VALGRIND_3_21_0~33 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2cccba7cae9f77aa6c2a498bc30a42bdb1ed8829;p=thirdparty%2Fvalgrind.git Tweak printing of `I refs` and `D refs` lines. Because `--cache-sim=no` is the default now, and `I refs:` looks weird by itself. --- diff --git a/cachegrind/cg_main.c b/cachegrind/cg_main.c index c17ab975b0..1ef7ce4f93 100644 --- a/cachegrind/cg_main.c +++ b/cachegrind/cg_main.c @@ -1589,7 +1589,7 @@ static void cg_fini(Int exitcode) VG_(sprintf)(fmt, "%%s %%,%dllu\n", l1); /* Always print this */ - VG_(umsg)(fmt, "I refs: ", Ir_total.a); + VG_(umsg)(fmt, "I refs: ", Ir_total.a); /* If cache profiling is enabled, show D access numbers and all miss numbers */ @@ -1614,7 +1614,7 @@ static void cg_fini(Int exitcode) VG_(sprintf)(fmt, "%%s %%,%dllu (%%,%dllu rd + %%,%dllu wr)\n", l1, l2, l3); - VG_(umsg)(fmt, "D refs: ", + VG_(umsg)(fmt, "D refs: ", D_total.a, Dr_total.a, Dw_total.a); VG_(umsg)(fmt, "D1 misses: ", D_total.m1, Dr_total.m1, Dw_total.m1); diff --git a/cachegrind/tests/ann-diff1.stderr.exp b/cachegrind/tests/ann-diff1.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann-diff1.stderr.exp +++ b/cachegrind/tests/ann-diff1.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann-diff2.stderr.exp b/cachegrind/tests/ann-diff2.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann-diff2.stderr.exp +++ b/cachegrind/tests/ann-diff2.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann-diff3.stderr.exp b/cachegrind/tests/ann-diff3.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann-diff3.stderr.exp +++ b/cachegrind/tests/ann-diff3.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann-diff4.stderr.exp b/cachegrind/tests/ann-diff4.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann-diff4.stderr.exp +++ b/cachegrind/tests/ann-diff4.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann-merge1.stderr.exp b/cachegrind/tests/ann-merge1.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann-merge1.stderr.exp +++ b/cachegrind/tests/ann-merge1.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann-merge2.stderr.exp b/cachegrind/tests/ann-merge2.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann-merge2.stderr.exp +++ b/cachegrind/tests/ann-merge2.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann1a.stderr.exp b/cachegrind/tests/ann1a.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann1a.stderr.exp +++ b/cachegrind/tests/ann1a.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann1b.stderr.exp b/cachegrind/tests/ann1b.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann1b.stderr.exp +++ b/cachegrind/tests/ann1b.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/ann2.stderr.exp b/cachegrind/tests/ann2.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/ann2.stderr.exp +++ b/cachegrind/tests/ann2.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/chdir.stderr.exp b/cachegrind/tests/chdir.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/chdir.stderr.exp +++ b/cachegrind/tests/chdir.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/dlclose.stderr.exp b/cachegrind/tests/dlclose.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/dlclose.stderr.exp +++ b/cachegrind/tests/dlclose.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/notpower2.stderr.exp b/cachegrind/tests/notpower2.stderr.exp index e8084c12c3..6960e51afb 100644 --- a/cachegrind/tests/notpower2.stderr.exp +++ b/cachegrind/tests/notpower2.stderr.exp @@ -1,12 +1,12 @@ -I refs: +I refs: I1 misses: LLi misses: I1 miss rate: LLi miss rate: -D refs: +D refs: D1 misses: LLd misses: D1 miss rate: diff --git a/cachegrind/tests/wrap5.stderr.exp b/cachegrind/tests/wrap5.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/wrap5.stderr.exp +++ b/cachegrind/tests/wrap5.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: diff --git a/cachegrind/tests/x86/fpu-28-108.stderr.exp b/cachegrind/tests/x86/fpu-28-108.stderr.exp index ec68407b27..28cb02fa84 100644 --- a/cachegrind/tests/x86/fpu-28-108.stderr.exp +++ b/cachegrind/tests/x86/fpu-28-108.stderr.exp @@ -1,3 +1,3 @@ -I refs: +I refs: