From: Gowtham Suresh Kumar Date: Tue, 14 Oct 2025 17:03:36 +0000 (+0000) Subject: Enable ARMV8_UNROLL12_EOR3 optimization for Neoverse N2/N3 X-Git-Tag: 4.0-PRE-CLANG-FORMAT-WEBKIT~212 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2d0c43b9ec2198b7a2cf33ab5fd778d523666869;p=thirdparty%2Fopenssl.git Enable ARMV8_UNROLL12_EOR3 optimization for Neoverse N2/N3 Unlike Neoverse N1, the Neoverse N2 and Neoverse N3 cores support the EOR3 instruction. Enabling ARMV8_UNROLL12_EOR3 on these cores gives performance uplift of 9-10% for AES-CTR 128/192/256 ciphers at larger block sizes. Signed-off-by: Gowtham Suresh Kumar Reviewed-by: Tom Cosgrove Reviewed-by: Tomas Mraz (Merged from https://github.com/openssl/openssl/pull/29044) --- diff --git a/crypto/armcap.c b/crypto/armcap.c index 9831162244a..afbfb377dd8 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -429,6 +429,8 @@ void OPENSSL_cpuid_setup(void) MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V3_AE) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V3) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N2) || + MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N3) || MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE) && (OPENSSL_armcap_P & ARMV8_SHA3)) OPENSSL_armcap_P |= ARMV8_UNROLL12_EOR3;