From: Kenneth Kasilag <kenneth@kasilag.me>
Date: Thu, 2 Jul 2026 11:26:43 +0000 (+0000)
Subject: qualcommbe: ipq9574: describe remaining uniphy resets
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2d35c376d8ef7a49674b6862ab42aa420978b6ae;p=thirdparty%2Fopenwrt.git

qualcommbe: ipq9574: describe remaining uniphy resets

Each uniphy has, besides the XPCS reset, a system reset in the GCC and
a soft reset in the NSSCC. The vendor driver pulses both on every
interface mode change as part of the uniphy bring-up. Describe them,
and name the resets while at it, so the PCS driver can pick them up.

Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
Link: https://github.com/openwrt/openwrt/pull/24033
Signed-off-by: Robert Marko <robimarko@gmail.com>
---

diff --git a/target/linux/qualcommbe/patches-6.18/0356-arm64-dts-qcom-ipq9574-describe-remaining-uniphy-resets.patch b/target/linux/qualcommbe/patches-6.18/0356-arm64-dts-qcom-ipq9574-describe-remaining-uniphy-resets.patch
new file mode 100644
index 00000000000..cb370691901
--- /dev/null
+++ b/target/linux/qualcommbe/patches-6.18/0356-arm64-dts-qcom-ipq9574-describe-remaining-uniphy-resets.patch
@@ -0,0 +1,58 @@
+From: Kenneth Kasilag <kenneth@kasilag.me>
+Date: Thu, 02 Jul 2026 00:00:00 +0000
+Subject: [PATCH] arm64: dts: qcom: ipq9574: describe remaining uniphy resets
+
+Each uniphy has, besides the XPCS reset, a system reset in the GCC and
+a soft reset in the NSSCC. The vendor driver pulses both on every
+interface mode change as part of the uniphy bring-up. Describe them,
+and name the resets while at it, so the PCS driver can pick them up.
+
+Signed-off-by: Kenneth Kasilag <kenneth@kasilag.me>
+---
+ arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++---
+ 1 file changed, 18 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+@@ -1493,7 +1493,12 @@
+ 				 <&gcc GCC_UNIPHY0_AHB_CLK>;
+ 			clock-names = "sys",
+ 				      "ahb";
+-			resets = <&gcc GCC_UNIPHY0_XPCS_RESET>;
++			resets = <&gcc GCC_UNIPHY0_XPCS_RESET>,
++				 <&gcc GCC_UNIPHY0_SYS_RESET>,
++				 <&nsscc UNIPHY0_SOFT_RESET>;
++			reset-names = "xpcs",
++				      "sys",
++				      "soft";
+ 			#clock-cells = <1>;
+ 
+ 			pcs0_ch0: pcs-mii@0 {
+@@ -1538,7 +1543,12 @@
+ 				 <&gcc GCC_UNIPHY1_AHB_CLK>;
+ 			clock-names = "sys",
+ 				      "ahb";
+-			resets = <&gcc GCC_UNIPHY1_XPCS_RESET>;
++			resets = <&gcc GCC_UNIPHY1_XPCS_RESET>,
++				 <&gcc GCC_UNIPHY1_SYS_RESET>,
++				 <&nsscc UNIPHY1_SOFT_RESET>;
++			reset-names = "xpcs",
++				      "sys",
++				      "soft";
+ 			#clock-cells = <1>;
+ 
+ 			pcs1_ch0: uniphy-ch@0 {
+@@ -1559,7 +1569,12 @@
+ 				 <&gcc GCC_UNIPHY2_AHB_CLK>;
+ 			clock-names = "sys",
+ 				      "ahb";
+-			resets = <&gcc GCC_UNIPHY2_XPCS_RESET>;
++			resets = <&gcc GCC_UNIPHY2_XPCS_RESET>,
++				 <&gcc GCC_UNIPHY2_SYS_RESET>,
++				 <&nsscc UNIPHY2_SOFT_RESET>;
++			reset-names = "xpcs",
++				      "sys",
++				      "soft";
+ 			#clock-cells = <1>;
+ 
+ 			pcs2_ch0: pcs-mii@0 {