From: Julian Seward <jseward@acm.org>
Date: Tue, 1 Feb 2005 15:24:10 +0000 (+0000)
Subject: PowerPC-32 has at at least two variant (with and without Altivec).
X-Git-Tag: svn/VALGRIND_3_0_1^2~533
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2d362402b4f04aa32fb750b3a6f7d524431e436e;p=thirdparty%2Fvalgrind.git

PowerPC-32 has at at least two variant (with and without Altivec).
Add preliminary support for distinguishing the two.


git-svn-id: svn://svn.valgrind.org/vex/trunk@801
---

diff --git a/VEX/priv/guest-ppc32/toIR.c b/VEX/priv/guest-ppc32/toIR.c
index 4d232f6f45..34046f50cd 100644
--- a/VEX/priv/guest-ppc32/toIR.c
+++ b/VEX/priv/guest-ppc32/toIR.c
@@ -215,7 +215,8 @@ IRBB* bbToIR_PPC32 ( UChar*           ppc32code,
    vassert(vex_control.guest_chase_thresh >= 0);
    vassert(vex_control.guest_chase_thresh < vex_control.guest_max_insns);
 
-   vassert(subarch_guest == VexSubArchPPC32);
+   vassert(subarch_guest == VexSubArchPPC32_noAV
+           || subarch_guest == VexSubArchPPC32_AV);
 
    /* Start a new, empty extent. */
    vge->n_used  = 1;
diff --git a/VEX/priv/main/vex_main.c b/VEX/priv/main/vex_main.c
index 43ac46d11b..3c99420f68 100644
--- a/VEX/priv/main/vex_main.c
+++ b/VEX/priv/main/vex_main.c
@@ -311,7 +311,8 @@ VexTranslateResult LibVEX_Translate (
          guest_sizeB      = sizeof(VexGuestPPC32State);
          guest_word_type  = Ity_I32;
          guest_layout     = &ppc32Guest_layout;
-         vassert(subarch_guest == VexSubArchPPC32);
+         vassert(subarch_guest == VexSubArchPPC32_noAV
+                 || subarch_guest == VexSubArchPPC32_AV);
          break;
 
       default:
@@ -319,10 +320,10 @@ VexTranslateResult LibVEX_Translate (
    }
 
    /* yet more sanity checks ... */
-   if (arch_guest == VexArchX86 && arch_host == VexArchX86) {
+   if (arch_guest == arch_host) {
       /* doesn't necessarily have to be true, but if it isn't it means
-         we are simulating one flavour of x86 on a different one, which
-         is pretty strange. */
+         we are simulating one flavour of an architecture a different
+         flavour of the same architecture, which is pretty strange. */
       vassert(subarch_guest == subarch_host);
    }
 
@@ -543,6 +544,7 @@ const HChar* LibVEX_ppVexArch ( VexArch arch )
       case VexArchX86:      return "X86";
       case VexArchAMD64:    return "AMD64";
       case VexArchARM:      return "ARM";
+      case VexArchPPC32:    return "PPC32";
       default:              return "VexArch???";
    }
 }
@@ -550,13 +552,15 @@ const HChar* LibVEX_ppVexArch ( VexArch arch )
 const HChar* LibVEX_ppVexSubArch ( VexSubArch subarch )
 {
    switch (subarch) {
-      case VexSubArch_INVALID: return "INVALID";
-      case VexSubArch_NONE:    return "NONE";
-      case VexSubArchX86_sse0: return "x86-sse0";
-      case VexSubArchX86_sse1: return "x86-sse1";
-      case VexSubArchX86_sse2: return "x86-sse2";
-      case VexSubArchARM_v4:   return "arm-v4";
-      default:                 return "VexSubArch???";
+      case VexSubArch_INVALID:   return "INVALID";
+      case VexSubArch_NONE:      return "NONE";
+      case VexSubArchX86_sse0:   return "x86-sse0";
+      case VexSubArchX86_sse1:   return "x86-sse1";
+      case VexSubArchX86_sse2:   return "x86-sse2";
+      case VexSubArchARM_v4:     return "arm-v4";
+      case VexSubArchPPC32_noAV: return "ppc32-noAltivec";
+      case VexSubArchPPC32_AV:   return "ppc32-Altivec";
+      default:                   return "VexSubArch???";
    }
 }
 
diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h
index b786a413cb..54159cbd60 100644
--- a/VEX/pub/libvex.h
+++ b/VEX/pub/libvex.h
@@ -62,12 +62,13 @@ typedef
 typedef
    enum {
       VexSubArch_INVALID,
-      VexSubArch_NONE,    /* Arch has no variants */
-      VexSubArchX86_sse0, /* has SSE state but no insns (Pentium II) */
-      VexSubArchX86_sse1, /* SSE1 support (Pentium III) */
-      VexSubArchX86_sse2, /* SSE2 support (Pentium 4) */
-      VexSubArchARM_v4,   /* ARM version 4 */
-      VexSubArchPPC32     /* CAB: ? */
+      VexSubArch_NONE,        /* Arch has no variants */
+      VexSubArchX86_sse0,     /* has SSE state but no insns (Pentium II) */
+      VexSubArchX86_sse1,     /* SSE1 support (Pentium III) */
+      VexSubArchX86_sse2,     /* SSE2 support (Pentium 4) */
+      VexSubArchARM_v4,       /* ARM version 4 */
+      VexSubArchPPC32_noAV,   /* 32-bit PowerPC, no Altivec */
+      VexSubArchPPC32_AV      /* 32-bit PowerPC with Altivec */
    }
    VexSubArch;