From: Kito Cheng <kito.cheng@sifive.com>
Date: Wed, 27 Oct 2021 16:27:39 +0000 (+0800)
Subject: RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern
X-Git-Tag: basepoints/gcc-13~3552
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2dc835cd0b5183a0e30b2b052362ad05f5c082b0;p=thirdparty%2Fgcc.git

RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern

We're wrongly guard zero_extendsidi2_internal pattern both ZBA and ZBB,
only ZBA provide zero_extendsidi2 instruction.

gcc/ChangeLog

	* config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
	use this pattern.
---

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f20..225e5b259c10 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1311,7 +1311,7 @@
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
+  "TARGET_64BIT && !TARGET_ZBA"
   "@
    #
    lwu\t%0,%1"