From: clyon <clyon@138bc75d-0d04-0410-961f-82ee72b054a4>
Date: Fri, 20 Sep 2019 13:32:20 +0000 (+0000)
Subject: Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2f0b2a149cac8b78823f34111232686394a3b143;p=thirdparty%2Fgcc.git

Revert [ARM/FDPIC v6 13/24] [ARM] FDPIC: Force LSB bit for PC in Cortex-M architecture

This is causing regressions when mixing with user code compiled in ARM mode.

2019-09-20  Christophe Lyon  <christophe.lyon@st.com>

	Revert:
	2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
		Mickaël Guêné <mickael.guene@st.com>

	* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
	architecture.




git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@276001 138bc75d-0d04-0410-961f-82ee72b054a4
---

diff --git a/libgcc/ChangeLog b/libgcc/ChangeLog
index 37fadd4149c2..74deb0f185a7 100644
--- a/libgcc/ChangeLog
+++ b/libgcc/ChangeLog
@@ -1,3 +1,12 @@
+2019-09-20  Christophe Lyon  <christophe.lyon@st.com>
+
+	Revert:
+	2019-09-10  Christophe Lyon  <christophe.lyon@st.com>
+		Mickaël Guêné <mickael.guene@st.com>
+
+	* config/arm/unwind-arm.c (_Unwind_VRS_Set): Handle thumb-only
+	architecture.
+
 2019-09-19  Richard Henderson  <richard.henderson@linaro.org>
 
 	* config/aarch64/lse-init.c: New file.
diff --git a/libgcc/config/arm/unwind-arm.c b/libgcc/config/arm/unwind-arm.c
index 8313ee03e903..9ba73e72a2a7 100644
--- a/libgcc/config/arm/unwind-arm.c
+++ b/libgcc/config/arm/unwind-arm.c
@@ -199,11 +199,6 @@ _Unwind_VRS_Result _Unwind_VRS_Set (_Unwind_Context *context,
 	return _UVRSR_FAILED;
 
       vrs->core.r[regno] = *(_uw *) valuep;
-#if defined(__thumb__)
-      /* Force LSB bit since we always run thumb code.  */
-      if (regno == R_PC)
-	vrs->core.r[regno] |= 1;
-#endif
       return _UVRSR_OK;
 
     case _UVRSC_VFP: