From: Linus Torvalds Date: Thu, 27 Mar 2025 16:01:37 +0000 (-0700) Subject: Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc X-Git-Tag: v6.15-rc1~159 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2f24482304ebd32c5aa374f31465b9941a860b92;p=thirdparty%2Flinux.git Merge tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull SoC devicetree updates from Arnd Bergmann: "There is new support for additional on-chip devices on Apple, Mediatek, Renesas, Rockchip, Samsung, Google, TI, ST, Nvidia and Amlogic devices. The Arm Morello reference platform gets a devicetree for booting in normal aarch64 mode. The hardware supports experimental CHERI support, which requires a modified kernel. The AMD (formerly Xilinx) Versal NET SoC gets added, this is a combined FPGA with Cortex-A78 CPUs in a SoC. Six new ST STM32MP2 SoC variants are added. Like the earlier STM32MP25, the MP211, MP213, MP215, MP231, MP233 and MP235 models are based on one or two Cortex-A35 cores but each feature a different set of I/O devices. Mediatek MT8370 is a minor variation of MT8390 with fewer CPU and GPU cores Apple T2 is the baseboard management controller on earlier Intel CPU based Macs, with 16 models now gaining initial support. All the above come with dts files for the reference boards. In addition, these boards are added for the SoCs that are already supported: - The Milk-V Jupiter board based on SpacemiT K1/M1 - NetCube Systems Kumquat board based on the 32-bit Allwinner V3s SoC - Three boards based on 32-bit stm32mp1 - 11 distinct board variants from Toradex and one from Variscite, all based on i.MX6 - Google Pixel Pro 6 phone based on gs101 (Tensor) - Three additional variants of the i.MX8MP based "Skov" board - A second variant of the i.MX95 EVK board - Two boards based on Renesas SoCs - Four boards based the Rockchip RK35xx series, plus the RK3588 'MNT Reform 2' laptop" * tag 'soc-dt-6.15' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (538 commits) arm64: dts: Add gpio_intc node for Amlogic A5 SoCs arm64: dts: Add gpio_intc node for Amlogic A4 SoCs arm64: dts: hi3660: Add property for fixing CPUIdle arm64: dts: rockchip: remove ethm0_clk0_25m_out from Sige5 gmac0 arm64: dts: marvell: Use preferred node names for "simple-bus" arm64: dts: marvell: Drop unused CP11X_TYPE define arm64: dts: marvell: Move arch timer and pmu nodes to top-level arm64: dts: rockchip: Fix PWM pinctrl names arm64: dts: rockchip: fix RK3576 SCMI clock IDs dt-bindings: clock: rk3576: add SCMI clocks arm64: dts: rockchip: Fix pcie reset gpio on Orange Pi 5 Max arm64: dts: amd/seattle: Drop undocumented "spi-controller" properties arm64: dts: amd/seattle: Fix bus, mmc, and ethernet node names arm64: dts: amd/seattle: Move and simplify fixed clocks arm64: dts: amd/seattle: Base Overdrive B1 on top of B0 version arm64: dts: rockchip: Enable HDMI audio output for ArmSoM Sige7 arm64: dts: rockchip: Enable onboard eMMC on Radxa E20C arm64: dts: rockchip: Add SDHCI controller for RK3528 arm64: dts: rockchip: Remove bluetooth node from rock-3a arm64: dts: rockchip: Move rk356x scmi SHMEM to reserved memory ... --- 2f24482304ebd32c5aa374f31465b9941a860b92 diff --cc arch/arm64/boot/dts/rockchip/rk3576.dtsi index bd55bd8a67cbd,b379e46229476..ebb5fc8bb8b13 --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi @@@ -1221,30 -1334,17 +1334,41 @@@ }; }; + ufshc: ufshc@2a2d0000 { + compatible = "rockchip,rk3576-ufshc"; + reg = <0x0 0x2a2d0000 0x0 0x10000>, + <0x0 0x2b040000 0x0 0x10000>, + <0x0 0x2601f000 0x0 0x1000>, + <0x0 0x2603c000 0x0 0x1000>, + <0x0 0x2a2e0000 0x0 0x10000>; + reg-names = "hci", "mphy", "hci_grf", "mphy_grf", "hci_apb"; + clocks = <&cru ACLK_UFS_SYS>, <&cru PCLK_USB_ROOT>, <&cru PCLK_MPHY>, + <&cru CLK_REF_UFS_CLKOUT>; + clock-names = "core", "pclk", "pclk_mphy", "ref_out"; + assigned-clocks = <&cru CLK_REF_OSC_MPHY>; + assigned-clock-parents = <&cru CLK_REF_MPHY_26M>; + interrupts = ; + power-domains = <&power RK3576_PD_USB>; + pinctrl-0 = <&ufs_refclk>; + pinctrl-names = "default"; + resets = <&cru SRST_A_UFS_BIU>, <&cru SRST_A_UFS_SYS>, + <&cru SRST_A_UFS>, <&cru SRST_P_UFS_GRF>; + reset-names = "biu", "sys", "ufs", "grf"; + reset-gpios = <&gpio4 RK_PD0 GPIO_ACTIVE_LOW>; + status = "disabled"; + }; + + sfc1: spi@2a300000 { + compatible = "rockchip,sfc"; + reg = <0x0 0x2a300000 0x0 0x4000>; + interrupts = ; + clocks = <&cru SCLK_FSPI1_X2>, <&cru HCLK_FSPI1>; + clock-names = "clk_sfc", "hclk_sfc"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + sdmmc: mmc@2a310000 { compatible = "rockchip,rk3576-dw-mshc"; reg = <0x0 0x2a310000 0x0 0x4000>;