From: Aric Cyr Date: Tue, 5 May 2026 20:27:29 +0000 (-0400) Subject: drm/amd/display: Fix assertion due to disable/enable CM blocks X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2f28f0063a117d55dfa1672a1698cfe8fb2ee5c3;p=thirdparty%2Flinux.git drm/amd/display: Fix assertion due to disable/enable CM blocks [why] Some dc state transitions can result in CM blocks being disabled, then re-enabled. The disable will set a defer bit, but re-enable will not clear it. When optimizing later, an assert will be hit due to incorrect expected HW state. [how] Clear defer bits if the block is re-enabled before optimization is executed. Reviewed-by: Alvin Lee Signed-off-by: Aric Cyr Signed-off-by: Ivan Lipski Tested-by: Dan Wheeler Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c index 8faffc2993b4..2ebc738c37f2 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c @@ -603,6 +603,7 @@ static void dpp3_power_on_blnd_lut( if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL, BLNDGAM_MEM_PWR_FORCE, 0); REG_WAIT(CM_MEM_PWR_STATUS, BLNDGAM_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_blnd_lut = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_blnd_lut = true; @@ -620,6 +621,7 @@ static void dpp3_power_on_hdr3dlut( if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL2, HDR3DLUT_MEM_PWR_FORCE, 0); REG_WAIT(CM_MEM_PWR_STATUS2, HDR3DLUT_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_3dlut = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_3dlut = true; @@ -637,6 +639,7 @@ static void dpp3_power_on_shaper( if (power_on) { REG_UPDATE(CM_MEM_PWR_CTRL2, SHAPER_MEM_PWR_FORCE, 0); REG_WAIT(CM_MEM_PWR_STATUS2, SHAPER_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_shaper = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_shaper = true; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c index 99581f35e54b..e01d8e9672fc 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp_cm.c @@ -136,6 +136,7 @@ static void dpp3_power_on_gamcor_lut( if (dpp_base->ctx->dc->caps.ips_v2_support) REG_UPDATE(CM_MEM_PWR_CTRL, GAMCOR_MEM_PWR_DIS, 1); REG_WAIT(CM_MEM_PWR_STATUS, GAMCOR_MEM_PWR_STATE, 0, 1, 5); + dpp_base->deferred_reg_writes.bits.disable_gamcor = false; } else { dpp_base->ctx->dc->optimized_required = true; dpp_base->deferred_reg_writes.bits.disable_gamcor = true; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index df3c21ef57a1..62994aecf499 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -161,6 +161,7 @@ static void dpp401_power_on_dscl( REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 100); } else REG_WAIT(DSCL_MEM_PWR_STATUS, LUT_MEM_PWR_STATE, 0, 1, 5); + dpp->base.deferred_reg_writes.bits.disable_dscl = false; } else { if (dpp->base.ctx->dc->debug.enable_mem_low_power.bits.dscl) { dpp->base.ctx->dc->optimized_required = true;