From: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date: Wed, 9 Nov 2022 23:43:05 +0000 (+0100)
Subject: RISC-V: Fix selection of pipeline model for sifive-7-series
X-Git-Tag: basepoints/gcc-14~3329
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2f6cb9c51a933de19cd88f4c9180ac9cf5093522;p=thirdparty%2Fgcc.git

RISC-V: Fix selection of pipeline model for sifive-7-series

A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a
while now, due to the pipeline model for sifive-7-series not being
selected despite -mtune=sifive-7-series.  The root cause is that the
respective RISCV_TUNE entry points to generic instead.  Fix this.

Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune")

gcc/ChangeLog:

	* config/riscv/riscv-cores.def (RISCV_TUNE): Update
	sifive-7-series to point to the sifive_7 pipeline description.
---

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index b84ad999ac14..31ad34682c54 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -36,7 +36,7 @@
 RISCV_TUNE("rocket", generic, rocket_tune_info)
 RISCV_TUNE("sifive-3-series", generic, rocket_tune_info)
 RISCV_TUNE("sifive-5-series", generic, rocket_tune_info)
-RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info)
+RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info)
 RISCV_TUNE("thead-c906", generic, thead_c906_tune_info)
 RISCV_TUNE("size", generic, optimize_size_tune_info)