From: Herve Codina (Schneider Electric) Date: Tue, 24 Mar 2026 12:04:30 +0000 (+0100) Subject: clk: renesas: r9a06g032: Enable watchdog reset sources X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=2fcaaf15e4ab86e7a81e3bd3eaeb8aa2f730ca29;p=thirdparty%2Fkernel%2Fstable.git clk: renesas: r9a06g032: Enable watchdog reset sources The watchdog timeout is signaled using an interrupt and, on this interrupt, a software initiated reset is performed. This software initiated reset performs, in the end, a hardware system reset using SWRST_REQ of RSTCTRL register. The watchdog itself is able to control directly the hardware system reset without any operation done by the interrupt handler. This feature allows the watchdog to not depend on the software to reset the system when a watchdog timeout occurs. Indeed, when the watchdog timeout occurs, the watchdog requests a system reset using its own hardware dedicated line but this reset source is disabled at the reset controller level. To benefit of this feature and be robust against software issues, enable watchdogs reset sources. Suggested-by: Wolfram Sang Signed-off-by: Herve Codina (Schneider Electric) Reviewed-by: Wolfram Sang Tested-by: Wolfram Sang Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20260324120435.243641-2-herve.codina@bootlin.com Signed-off-by: Geert Uytterhoeven --- diff --git a/drivers/clk/renesas/r9a06g032-clocks.c b/drivers/clk/renesas/r9a06g032-clocks.c index 7407a4183a6c..076f587dfd39 100644 --- a/drivers/clk/renesas/r9a06g032-clocks.c +++ b/drivers/clk/renesas/r9a06g032-clocks.c @@ -1342,8 +1342,9 @@ static int __init r9a06g032_clocks_probe(struct platform_device *pdev) /* Clear potentially pending resets */ writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1, clocks->reg + R9A06G032_SYSCTRL_RSTCTRL); - /* Allow software reset */ - writel(R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN, + /* Allow watchdog and software resets */ + writel(R9A06G032_SYSCTRL_WDA7RST_0 | R9A06G032_SYSCTRL_WDA7RST_1 | + R9A06G032_SYSCTRL_SWRST | R9A06G032_SYSCTRL_RSTEN_MRESET_EN, clocks->reg + R9A06G032_SYSCTRL_RSTEN); error = devm_register_sys_off_handler(dev, SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,