From: Abel Vesa Date: Mon, 23 Mar 2026 18:57:12 +0000 (+0200) Subject: clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3006f7fbc7ef53bf8316b02d7f23f647b24c3eca;p=thirdparty%2Flinux.git clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock According to internal documentation, the UFS AXI PHY clock requires FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this, the UFS controller fails when operating in MCQ mode, which is already enabled in the device tree. The UFS PHY ICE core clock already has this bit set, so apply the same configuration to the UFS PHY AXI clock. Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza") Reported-by: Nitin Rawat Signed-off-by: Abel Vesa Reviewed-by: Taniya Das Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20260323-eliza-gcc-set-ufs-axi-phyforce-mem-core-on-v1-1-b6b7a6f3f8c5@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/drivers/clk/qcom/gcc-eliza.c b/drivers/clk/qcom/gcc-eliza.c index 06ee1469badd..338494385752 100644 --- a/drivers/clk/qcom/gcc-eliza.c +++ b/drivers/clk/qcom/gcc-eliza.c @@ -3046,8 +3046,9 @@ static const struct regmap_config gcc_eliza_regmap_config = { static void clk_eliza_regs_configure(struct device *dev, struct regmap *regmap) { - /* FORCE_MEM_CORE_ON for ufs phy ice core clocks */ + /* FORCE_MEM_CORE_ON for ufs phy ice core and gcc ufs phy axi clocks */ qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_ice_core_clk, true); + qcom_branch_set_force_mem_core(regmap, gcc_ufs_phy_axi_clk, true); } static struct qcom_cc_driver_data gcc_eliza_driver_data = {