From: Fabiano Rosas Date: Fri, 28 Jan 2022 12:15:03 +0000 (+0100) Subject: target/ppc: 405: Add missing MSR_ME bit X-Git-Tag: v7.0.0-rc0~69^2~26 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=301e5d48b15d2846cabe0f5c7600860b35c58c12;p=thirdparty%2Fqemu.git target/ppc: 405: Add missing MSR_ME bit The 405 MSR has the Machine Check Enable bit. We're making use of it when dispatching Machine Check, so add the bit to the msr_mask. Signed-off-by: Fabiano Rosas Reviewed-by: Cédric Le Goater Message-Id: <20220118184448.852996-3-farosas@linux.ibm.com> Signed-off-by: Cédric Le Goater --- diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index e63705b1c6b..23a13036b21 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2540,6 +2540,7 @@ POWERPC_FAMILY(405)(ObjectClass *oc, void *data) (1ull << MSR_EE) | (1ull << MSR_PR) | (1ull << MSR_FP) | + (1ull << MSR_ME) | (1ull << MSR_DWE) | (1ull << MSR_DE) | (1ull << MSR_IR) |