From: Julian Seward <jseward@acm.org>
Date: Wed, 27 Dec 2006 21:38:35 +0000 (+0000)
Subject: Merge r1707 (Enable lvxl and stvxl.)
X-Git-Tag: svn/VALGRIND_3_2_3^2~21
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=304fa745a17c6d81ddd281db8aa694edeae43713;p=thirdparty%2Fvalgrind.git

Merge r1707 (Enable lvxl and stvxl.)


git-svn-id: svn://svn.valgrind.org/vex/branches/VEX_3_2_BRANCH@1708
---

diff --git a/VEX/priv/guest-ppc/toIR.c b/VEX/priv/guest-ppc/toIR.c
index c896983608..aef1852b63 100644
--- a/VEX/priv/guest-ppc/toIR.c
+++ b/VEX/priv/guest-ppc/toIR.c
@@ -6862,10 +6862,9 @@ static Bool dis_av_load ( UInt theInstr )
       break;
 
    case 0x167: // lvxl (Load Vector Indexed LRU, AV p128)
-     // XXX: lvxl gives explicit control over cache block replacement
       DIP("lvxl v%d,r%u,r%u\n", vD_addr, rA_addr, rB_addr);
-      DIP(" => not implemented\n");
-      return False;
+      putVReg( vD_addr, loadBE(Ity_V128, mkexpr(EA_align16)) );
+      break;
 
    default:
       vex_printf("dis_av_load(ppc)(opc2)\n");
@@ -6950,12 +6949,9 @@ static Bool dis_av_store ( UInt theInstr )
       break;
 
    case 0x1E7: // stvxl (Store Vector Indexed LRU, AV p135)
-     // XXX: stvxl can give explicit control over cache block replacement
       DIP("stvxl v%d,r%u,r%u\n", vS_addr, rA_addr, rB_addr);
-      DIP(" => not implemented\n");
-      return False;
-//      STORE(vS, 16, addr_align( mkexpr(EA), 16 ));
-//      break;
+      storeBE( addr_align( mkexpr(EA), 16 ), mkexpr(vS) );
+      break;
 
    default:
       vex_printf("dis_av_store(ppc)(opc2)\n");