From: Ju-Zhe Zhong Date: Tue, 7 Feb 2023 06:46:48 +0000 (+0800) Subject: RISC-V: Add vwmulsu.v C++ API tests X-Git-Tag: basepoints/gcc-14~1315 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=307241cbaa9d183b57076bac7be2d3876d918e0b;p=thirdparty%2Fgcc.git RISC-V: Add vwmulsu.v C++ API tests gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwmulsu_vv-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C: New test. --- diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C new file mode 100644 index 000000000000..3fc5597750a7 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C new file mode 100644 index 000000000000..0bfa1ed0d7ac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C new file mode 100644 index 000000000000..e5651eb11581 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C new file mode 100644 index 000000000000..4c0c93dedd93 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C new file mode 100644 index 000000000000..3728d13f59f4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C new file mode 100644 index 000000000000..efc18cdf0a06 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C new file mode 100644 index 000000000000..7133c9efe975 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C new file mode 100644 index 000000000000..70254246d06f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C new file mode 100644 index 000000000000..1c5fd72ad92f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C new file mode 100644 index 000000000000..3cf1259177f5 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C new file mode 100644 index 000000000000..9d506dd33f28 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C new file mode 100644 index 000000000000..d17ddcb612ac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C new file mode 100644 index 000000000000..24cb1dfe22a9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C new file mode 100644 index 000000000000..af588dfb6bf2 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C new file mode 100644 index 000000000000..e8878d41891c --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vuint8m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vuint8m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vuint8m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vuint16m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vuint16m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vuint16m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vuint32m1_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vuint32m2_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vuint32m4_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C new file mode 100644 index 000000000000..d45e1752626d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C new file mode 100644 index 000000000000..af185c29fb22 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C new file mode 100644 index 000000000000..245fab88866d --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu(vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu(vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu(vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu(vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu(vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu(vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu(vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu(vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu(vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu(vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu(vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu(vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu(vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu(vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu(vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwmulsu(vbool64_t mask,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu(vbool32_t mask,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu(vbool16_t mask,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu(vbool8_t mask,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu(vbool4_t mask,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu(vbool2_t mask,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu(vbool64_t mask,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu(vbool32_t mask,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu(vbool16_t mask,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu(vbool8_t mask,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu(vbool4_t mask,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu(vbool64_t mask,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu(vbool32_t mask,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu(vbool16_t mask,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu(vbool8_t mask,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C new file mode 100644 index 000000000000..8293e9721755 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C new file mode 100644 index 000000000000..42989e0186c1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C new file mode 100644 index 000000000000..b098a5871387 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C new file mode 100644 index 000000000000..71933e4e41dc --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C new file mode 100644 index 000000000000..78f2a3441b37 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C new file mode 100644 index 000000000000..60f1f0589e99 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tu(vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_tu(vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_tu(vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_tu(vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_tu(vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_tu(vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_tu(vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_tu(vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_tu(vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_tu(vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_tu(vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_tu(vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_tu(vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_tu(vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_tu(vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C new file mode 100644 index 000000000000..78a817d3f7da --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C new file mode 100644 index 000000000000..ac7395735939 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C new file mode 100644 index 000000000000..9d1ce8327ad4 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C new file mode 100644 index 000000000000..c5880edf5e30 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C new file mode 100644 index 000000000000..fe37f4bab12e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C new file mode 100644 index 000000000000..d760b8e8b0b1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwmulsu_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwmulsu_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,uint8_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwmulsu_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,uint16_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwmulsu_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwmulsu_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwmulsu_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwmulsu_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,uint32_t op2,size_t vl) +{ + return __riscv_vwmulsu_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwmulsu\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */