From: Carl Love <carll@us.ibm.com>
Date: Fri, 22 Mar 2019 17:42:27 +0000 (-0500)
Subject: PPC64, fix output for xvcvdpsp instruction.
X-Git-Tag: VALGRIND_3_15_0~41
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=30a24515f09f9118c469ae11c9d574da729c97ed;p=thirdparty%2Fvalgrind.git

PPC64, fix output for xvcvdpsp instruction.

The instruction should write the output to the upper and lower 32-bit
halfs of the results.

Valgrind bugzilla 405733.
---

diff --git a/NEWS b/NEWS
index a18d3406ab..c2a78482f6 100644
--- a/NEWS
+++ b/NEWS
@@ -119,6 +119,7 @@ where XXXXXX is the bug number as listed below.
 405363  PPC64, xvcvdpsxws, xvcvdpuxws, do not handle NaN arguments correctly.
 405365  PPC64, function _get_maxmin_fp_NaN() doesn't handle QNaN, SNaN case
         correctly.
+405733  PPC64, xvcvdpsp should write 32-bit result to upper and lower 32-bits of the 64-bit destination field.
 
 n-i-bz  add syswrap for PTRACE_GET|SET_THREAD_AREA on amd64.
 n-i-bz  Fix callgrind_annotate non deterministic order for equal total
diff --git a/VEX/priv/guest_ppc_toIR.c b/VEX/priv/guest_ppc_toIR.c
index 3725e6ae9c..9bc7c3bf7c 100644
--- a/VEX/priv/guest_ppc_toIR.c
+++ b/VEX/priv/guest_ppc_toIR.c
@@ -16332,6 +16332,9 @@ dis_vx_conv ( UInt theInstr, UInt opc2 )
       case 0x312: // xvcvdpsp (VSX Vector round Double-Precision to single-precision
                   //           and Convert to Single-Precision format)
          DIP("xvcvdpsp v%u,v%u\n", XT, XB);
+
+         /* Note, the 32-bit result is put into the upper and lower bits of the
+            doubleword result.  */
          putVSReg( XT,
                    binop( Iop_64HLtoV128,
                           binop( Iop_32HLto64,
@@ -16340,14 +16343,22 @@ dis_vx_conv ( UInt theInstr, UInt opc2 )
                                              binop( Iop_RoundF64toF32,
                                                     get_IR_roundingmode(),
                                                     mkexpr( xB ) ) ) ),
-                                 mkU32( 0 ) ),
+                                 unop( Iop_ReinterpF32asI32,
+                                       unop( Iop_TruncF64asF32,
+                                             binop( Iop_RoundF64toF32,
+                                                    get_IR_roundingmode(),
+                                                    mkexpr( xB ) ) ) ) ),
                           binop( Iop_32HLto64,
                                  unop( Iop_ReinterpF32asI32,
                                        unop( Iop_TruncF64asF32,
                                              binop( Iop_RoundF64toF32,
                                                     get_IR_roundingmode(),
                                                     mkexpr( xB2 ) ) ) ),
-                                 mkU32( 0 ) ) ) );
+                                 unop( Iop_ReinterpF32asI32,
+                                       unop( Iop_TruncF64asF32,
+                                             binop( Iop_RoundF64toF32,
+                                                    get_IR_roundingmode(),
+                                                    mkexpr( xB2 ) ) ) ) ) ) );
          break;
       case 0x390: // xvcvdpuxds (VSX Vector truncate Double-Precision to integer
                   //             and Convert to Unsigned Integer Doubleword format