From: Ju-Zhe Zhong Date: Tue, 7 Feb 2023 06:54:25 +0000 (+0800) Subject: RISC-V: Add vwadd v C++ api test X-Git-Tag: basepoints/gcc-14~1309 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=316c83b158dbae2559f130fb7e44718c99941266;p=thirdparty%2Fgcc.git RISC-V: Add vwadd v C++ api test gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwadd_vv-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vv-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vv-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vx-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vx-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vx-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C: New test. --- diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-1.C new file mode 100644 index 000000000000..b9ee1e9b64e9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vv(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vv(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vv(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vv(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vv(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vv(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vv(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vv(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vv(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vv(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vv(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vv(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vv(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vv(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwadd_vv(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vv(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vv(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vv(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vv(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vv(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vv(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vv(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vv(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vv(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vv(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vv(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vv(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vv(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vv(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-2.C new file mode 100644 index 000000000000..66472e44a70e --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vv(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vv(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vv(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vv(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vv(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vv(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vv(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vv(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vv(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vv(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vv(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vv(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vv(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vv(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwadd_vv(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vv(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vv(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vv(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vv(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vv(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vv(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vv(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vv(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vv(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vv(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vv(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vv(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vv(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vv(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-3.C new file mode 100644 index 000000000000..ea37d0282dad --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv(vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vv(vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vv(vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vv(vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vv(vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vv(vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vv(vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vv(vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vv(vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vv(vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vv(vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vv(vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vv(vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vv(vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vv(vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwadd_vv(vbool64_t mask,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vv(vbool32_t mask,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vv(vbool16_t mask,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vv(vbool8_t mask,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vv(vbool4_t mask,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vv(vbool2_t mask,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vv(vbool64_t mask,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vv(vbool32_t mask,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vv(vbool16_t mask,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vv(vbool8_t mask,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vv(vbool4_t mask,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vv(vbool64_t mask,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vv(vbool32_t mask,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vv(vbool16_t mask,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vv(vbool8_t mask,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-1.C new file mode 100644 index 000000000000..d07f3dc79a65 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vv_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vv_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vv_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-2.C new file mode 100644 index 000000000000..0fd4a4c7423a --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vv_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vv_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vv_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-3.C new file mode 100644 index 000000000000..e58d58f950e3 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vv_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vv_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vv_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vv_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vv_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vv_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vv_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-1.C new file mode 100644 index 000000000000..8253bd3b5dc9 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vv_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vv_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vv_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vv_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vv_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vv_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vv_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vv_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vv_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vv_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vv_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vv_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vv_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vv_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-2.C new file mode 100644 index 000000000000..8960c155ef38 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vv_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vv_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vv_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vv_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vv_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vv_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vv_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vv_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vv_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vv_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vv_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vv_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vv_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vv_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-3.C new file mode 100644 index 000000000000..8b4be1399547 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tu(vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vv_tu(vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vv_tu(vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vv_tu(vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vv_tu(vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vv_tu(vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vv_tu(vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vv_tu(vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vv_tu(vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vv_tu(vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vv_tu(vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vv_tu(vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vv_tu(vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vv_tu(vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vv_tu(vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-1.C new file mode 100644 index 000000000000..5e6d5241e588 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vv_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vv_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vv_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-2.C new file mode 100644 index 000000000000..85e1f802b049 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vv_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vv_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vv_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-3.C new file mode 100644 index 000000000000..30f3bf886504 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vv_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vv_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vv_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vv_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vv_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vv_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vv_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C new file mode 100644 index 000000000000..2b3c3516ffd8 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vv_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vv_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vv_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C new file mode 100644 index 000000000000..c7493cb13f87 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vv_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vv_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vv_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C new file mode 100644 index 000000000000..8c26a744411f --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vv_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,vint8m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vv_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,vint8m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vv_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,vint8m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vv_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vv_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vv_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vv_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vv_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{ + return __riscv_vwadd_vv_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-1.C new file mode 100644 index 000000000000..8db0812fcf61 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-1.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vx(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vx(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vx(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vx(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vx(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vx(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vx(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vx(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vx(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vx(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vx(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vx(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vx(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vx(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,vl); +} + + +vint16mf4_t test___riscv_vwadd_vx(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vx(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vx(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vx(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vx(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vx(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vx(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vx(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vx(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vx(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vx(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vx(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vx(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vx(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vx(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-2.C new file mode 100644 index 000000000000..66aaa000b978 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-2.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vx(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vx(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vx(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vx(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vx(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vx(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vx(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vx(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vx(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vx(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vx(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vx(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vx(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vx(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,31); +} + + +vint16mf4_t test___riscv_vwadd_vx(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vx(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vx(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vx(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vx(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vx(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vx(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vx(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vx(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vx(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vx(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vx(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vx(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vx(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vx(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-3.C new file mode 100644 index 000000000000..60eb8e92c29b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx-3.C @@ -0,0 +1,216 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx(vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vx(vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vx(vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vx(vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vx(vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vx(vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vx(vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vx(vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vx(vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vx(vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vx(vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vx(vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vx(vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vx(vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vx(vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(op1,op2,32); +} + + +vint16mf4_t test___riscv_vwadd_vx(vbool64_t mask,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vx(vbool32_t mask,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vx(vbool16_t mask,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vx(vbool8_t mask,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vx(vbool4_t mask,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vx(vbool2_t mask,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vx(vbool64_t mask,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vx(vbool32_t mask,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vx(vbool16_t mask,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vx(vbool8_t mask,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vx(vbool4_t mask,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vx(vbool64_t mask,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vx(vbool32_t mask,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vx(vbool16_t mask,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vx(vbool8_t mask,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx(mask,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-1.C new file mode 100644 index 000000000000..b18ef7d46fa6 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vx_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vx_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vx_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-2.C new file mode 100644 index 000000000000..5efe16db842b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vx_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vx_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vx_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-3.C new file mode 100644 index 000000000000..45b444a34eac --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_mu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vx_mu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vx_mu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vx_mu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vx_mu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vx_mu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vx_mu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vx_mu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_mu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-1.C new file mode 100644 index 000000000000..413849748d42 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vx_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vx_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vx_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vx_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vx_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vx_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vx_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vx_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vx_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vx_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vx_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vx_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vx_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vx_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-2.C new file mode 100644 index 000000000000..c2fa70d577a0 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vx_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vx_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vx_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vx_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vx_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vx_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vx_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vx_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vx_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vx_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vx_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vx_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vx_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vx_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-3.C new file mode 100644 index 000000000000..33dcfbe8571b --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tu(vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vx_tu(vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vx_tu(vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vx_tu(vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vx_tu(vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vx_tu(vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vx_tu(vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vx_tu(vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vx_tu(vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vx_tu(vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vx_tu(vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vx_tu(vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vx_tu(vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vx_tu(vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vx_tu(vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tu(merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-1.C new file mode 100644 index 000000000000..53455105a8bb --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vx_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vx_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vx_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-2.C new file mode 100644 index 000000000000..ba7e37af2d17 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vx_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vx_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vx_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-3.C new file mode 100644 index 000000000000..935284e04665 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tum-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vx_tum(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vx_tum(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vx_tum(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vx_tum(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vx_tum(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vx_tum(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vx_tum(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tum(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C new file mode 100644 index 000000000000..d01ae38ec677 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-1.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint16mf2_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint16m1_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint16m2_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint16m4_t test___riscv_vwadd_vx_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint16m8_t test___riscv_vwadd_vx_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint32mf2_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint32m1_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint32m2_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint32m4_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint32m8_t test___riscv_vwadd_vx_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint64m1_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint64m2_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint64m4_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + +vint64m8_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,vl); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C new file mode 100644 index 000000000000..b24b9a681183 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-2.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint16mf2_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint16m1_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint16m2_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint16m4_t test___riscv_vwadd_vx_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint16m8_t test___riscv_vwadd_vx_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint32mf2_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint32m1_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint32m2_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint32m4_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint32m8_t test___riscv_vwadd_vx_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint64m1_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint64m2_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint64m4_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + +vint64m8_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,31); +} + + + +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C new file mode 100644 index 000000000000..32e8d0f728c1 --- /dev/null +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vwadd_vx_tumu-3.C @@ -0,0 +1,111 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */ + +#include "riscv_vector.h" + +vint16mf4_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint16mf4_t merge,vint8mf8_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint16mf2_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint16mf2_t merge,vint8mf4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint16m1_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint16m1_t merge,vint8mf2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint16m2_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint16m2_t merge,vint8m1_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint16m4_t test___riscv_vwadd_vx_tumu(vbool4_t mask,vint16m4_t merge,vint8m2_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint16m8_t test___riscv_vwadd_vx_tumu(vbool2_t mask,vint16m8_t merge,vint8m4_t op1,int8_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint32mf2_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint32mf2_t merge,vint16mf4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint32m1_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint32m1_t merge,vint16mf2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint32m2_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint32m2_t merge,vint16m1_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint32m4_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint32m4_t merge,vint16m2_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint32m8_t test___riscv_vwadd_vx_tumu(vbool4_t mask,vint32m8_t merge,vint16m4_t op1,int16_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint64m1_t test___riscv_vwadd_vx_tumu(vbool64_t mask,vint64m1_t merge,vint32mf2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint64m2_t test___riscv_vwadd_vx_tumu(vbool32_t mask,vint64m2_t merge,vint32m1_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint64m4_t test___riscv_vwadd_vx_tumu(vbool16_t mask,vint64m4_t merge,vint32m2_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + +vint64m8_t test___riscv_vwadd_vx_tumu(vbool8_t mask,vint64m8_t merge,vint32m4_t op1,int32_t op2,size_t vl) +{ + return __riscv_vwadd_vx_tumu(mask,merge,op1,op2,32); +} + + + +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */ +/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */