From: Kyrylo Tkachov Date: Wed, 27 Apr 2016 14:38:10 +0000 (+0000) Subject: [rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS X-Git-Tag: basepoints/gcc-8~7383 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=317d98872b3c9173d4a9f82693bbdcc84cdeb03c;p=thirdparty%2Fgcc.git [rtlanal.c] Convert conditional compilation on WORD_REGISTER_OPERATIONS * rtlanal.c (nonzero_bits1): Convert preprocessor check for WORD_REGISTER_OPERATIONS to runtime check. From-SVN: r235512 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index cbfae1ffe66d..c97041a3afd1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,8 @@ +2016-04-27 Kyrylo Tkachov + + * rtlanal.c (nonzero_bits1): Convert preprocessor check + for WORD_REGISTER_OPERATIONS to runtime check. + 2016-04-27 Richard Biener PR ipa/70760 diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index b4dff86c0e9a..0b6e1e0e38d1 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -4584,13 +4584,14 @@ nonzero_bits1 (const_rtx x, machine_mode mode, const_rtx known_x, nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, known_x, known_mode, known_ret); -#if WORD_REGISTER_OPERATIONS && defined (LOAD_EXTEND_OP) +#ifdef LOAD_EXTEND_OP /* If this is a typical RISC machine, we only have to worry about the way loads are extended. */ - if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND - ? val_signbit_known_set_p (inner_mode, nonzero) - : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) - || !MEM_P (SUBREG_REG (x))) + if (WORD_REGISTER_OPERATIONS + && ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND + ? val_signbit_known_set_p (inner_mode, nonzero) + : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) + || !MEM_P (SUBREG_REG (x)))) #endif { /* On many CISC machines, accessing an object in a wider mode