From: Thomas Preud'homme Date: Wed, 7 Dec 2016 17:51:00 +0000 (+0000) Subject: backport: [multiple changes] X-Git-Tag: releases/gcc-5.5.0~658 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=31ecce685371f1376c07991363c76b905b1e99a5;p=thirdparty%2Fgcc.git backport: [multiple changes] 2016-12-07 Thomas Preud'homme Backport from mainline 2016-11-16 Thomas Preud'homme gcc/ * config/arm/arm.md (arm_addsi3): Add alternative for addition of general register with general register or ARM constant into SP register. gcc/testsuite/ * gcc.target/arm/empty_fiq_handler.c: New test. Backport from mainline 2016-11-21 Thomas Preud'homme gcc/testsuite/ * gcc.target/arm/empty_fiq_handler.c: Skip if -mthumb is passed in and target is Thumb-only. From-SVN: r243373 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 7a2498e3dedf..340a755bbc0c 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,12 @@ +2016-12-07 Thomas Preud'homme + + Backport from mainline + 2016-11-16 Thomas Preud'homme + + * config/arm/arm.md (arm_addsi3): Add alternative for addition of + general register with general register or ARM constant into SP + register. + 2016-12-06 Bill Schmidt Backport from mainline diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 32e015d44b35..faa08e47b6b1 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -567,9 +567,9 @@ ;; (plus (reg rN) (reg sp)) into (reg rN). In this case reload will ;; put the duplicated register first, and not try the commutative version. (define_insn_and_split "*arm_addsi3" - [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,r ,k ,r ,k,k,r ,k ,r") - (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,rk,k ,rk,k,r,rk,k ,rk") - (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,Pj,Pj,L ,L,L,PJ,PJ,?n")))] + [(set (match_operand:SI 0 "s_register_operand" "=rk,l,l ,l ,r ,k ,r,k ,r ,k ,r ,k,k,r ,k ,r") + (plus:SI (match_operand:SI 1 "s_register_operand" "%0 ,l,0 ,l ,rk,k ,r,r ,rk,k ,rk,k,r,rk,k ,rk") + (match_operand:SI 2 "reg_or_int_operand" "rk ,l,Py,Pd,rI,rI,k,rI,Pj,Pj,L ,L,L,PJ,PJ,?n")))] "TARGET_32BIT" "@ add%?\\t%0, %0, %2 @@ -579,6 +579,7 @@ add%?\\t%0, %1, %2 add%?\\t%0, %1, %2 add%?\\t%0, %2, %1 + add%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 addw%?\\t%0, %1, %2 sub%?\\t%0, %1, #%n2 @@ -598,10 +599,10 @@ operands[1], 0); DONE; " - [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,16") + [(set_attr "length" "2,4,4,4,4,4,4,4,4,4,4,4,4,4,4,16") (set_attr "predicable" "yes") - (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no") - (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") + (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no,no,no,no,no,no,no,no") + (set_attr "arch" "t2,t2,t2,t2,*,*,*,a,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") (const_string "alu_sreg"))) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index b73a8c241e63..f60246814545 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,16 @@ +2016-12-07 Thomas Preud'homme + + Backport from mainline + 2016-11-16 Thomas Preud'homme + + * gcc.target/arm/empty_fiq_handler.c: New test. + + Backport from mainline + 2016-11-21 Thomas Preud'homme + + * gcc.target/arm/empty_fiq_handler.c: Skip if -mthumb is passed in and + target is Thumb-only. + 2016-12-04 Janus Weil Backport from trunk diff --git a/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c new file mode 100644 index 000000000000..8313f2199122 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/empty_fiq_handler.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-skip-if "" { ! arm_cortex_m } { "-mthumb" } } */ + +/* Below code used to trigger an ICE due to missing constraints for + sp = fp + cst pattern. */ + +void fiq_handler (void) __attribute__((interrupt ("FIQ"))); + +void +fiq_handler (void) +{ +}