From: Szabolcs Nagy <szabolcs.nagy@arm.com>
Date: Fri, 21 Oct 2022 14:41:13 +0000 (+0100)
Subject: Revert "TODO(drop): aarch64: morello: CPU feature detection for Morello"
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3295936b272a1018e31fd634b7e327101eacd711;p=thirdparty%2Fglibc.git

Revert "TODO(drop): aarch64: morello: CPU feature detection for Morello"

This reverts commit 078ebf3e35bd0c50b58dc2ec796530054f69b9a9.
---

diff --git a/sysdeps/aarch64/multiarch/init-arch.h b/sysdeps/aarch64/multiarch/init-arch.h
index d5219186be0..a4dcac00192 100644
--- a/sysdeps/aarch64/multiarch/init-arch.h
+++ b/sysdeps/aarch64/multiarch/init-arch.h
@@ -35,6 +35,4 @@
   bool __attribute__((unused)) mte =					      \
     MTE_ENABLED ();							      \
   bool __attribute__((unused)) sve =					      \
-    GLRO(dl_aarch64_cpu_features).sve;					      \
-  bool __attribute__((unused)) morello =				      \
-    GLRO(dl_hwcap2) & HWCAP2_MORELLO;
+    GLRO(dl_aarch64_cpu_features).sve;
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
index 3d95815d5f0..d14c0f4e1f2 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.c
@@ -126,7 +126,4 @@ init_cpu_features (struct cpu_features *cpu_features)
 
   /* Check if SVE is supported.  */
   cpu_features->sve = GLRO (dl_hwcap) & HWCAP_SVE;
-
-  /* Check if Morello is supported.  */
-  cpu_features->morello = GLRO (dl_hwcap2) & HWCAP2_MORELLO;
 }
diff --git a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
index 0742ac14092..391165a99c2 100644
--- a/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
+++ b/sysdeps/unix/sysv/linux/aarch64/cpu-features.h
@@ -68,11 +68,6 @@
 #define IS_A64FX(midr) (MIDR_IMPLEMENTOR(midr) == 'F'			      \
 			&& MIDR_PARTNUM(midr) == 0x001)
 
-/* TODO: This is based on the Morello Fast Model.
-	 Will MIDR_IMPLEMENTOR change to 'A'?  */
-#define IS_MORELLO(midr) (MIDR_IMPLEMENTOR(midr) == 0x3f       \
-                         && MIDR_PARTNUM(midr) == 0x412)
-
 struct cpu_features
 {
   uint64_t midr_el1;
@@ -81,7 +76,6 @@ struct cpu_features
   /* Currently, the GLIBC memory tagging tunable only defines 8 bits.  */
   uint8_t mte_state;
   bool sve;
-  bool morello;
 };
 
 #endif /* _CPU_FEATURES_AARCH64_H  */