From: Carl Love Date: Mon, 21 Sep 2020 20:57:26 +0000 (-0500) Subject: Prefixed load-store support X-Git-Tag: VALGRIND_3_17_0~154 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=336b8c514dbfc177283ee71b803b67f5145e8bf7;p=thirdparty%2Fvalgrind.git Prefixed load-store support --- diff --git a/NEWS b/NEWS index eacf97bf6a..13bfe4fa1e 100644 --- a/NEWS +++ b/NEWS @@ -238,6 +238,7 @@ n-i-bz Add support for the Linux io_uring system calls n-i-bz sys_statx: don't complain if both |filename| and |buf| are NULL. n-i-bz Fix non-glibc build of test suite with s390x_features n-i-bz MinGW, include/valgrind.h: Fix detection of 64-bit mode +423195 PPC ISA 3.1 support is missing, part 1 (3.16.0.RC1: 18 May 2020, git 6052ee66a0cf5234e8e2a2b49a8760226bc13b92) (3.16.0.RC2: 19 May 2020, git 940ec1ca69a09f7fdae3e800b7359f85c13c4b37) diff --git a/none/tests/ppc64/Makefile.am b/none/tests/ppc64/Makefile.am index a43e527fe6..e029e7398f 100644 --- a/none/tests/ppc64/Makefile.am +++ b/none/tests/ppc64/Makefile.am @@ -49,10 +49,10 @@ EXTRA_DIST = \ test_isa_3_0_altivec.stdout.exp-LE test_isa_3_0_altivec.vgtest \ test_isa_3_0_other.stderr.exp \ test_isa_3_0_other.stdout.exp-LE test_isa_3_0_other.vgtest \ + test_isa_3_1_RT.vgtest test_isa_3_1_RT.stderr.exp test_isa_3_1_RT.stdout.exp \ + test_isa_3_1_XT.vgtest test_isa_3_1_XT.stderr.exp test_isa_3_1_XT.stdout.exp \ subnormal_test.stderr.exp subnormal_test.stdout.exp \ subnormal_test.vgtest -# test_isa_3_1_RT.vgtest test_isa_3_1_RT.stderr.exp test_isa_3_1_RT.stdout.exp -# test_isa_3_1_XT.vgtest test_isa_3_1_XT.stderr.exp test_isa_3_1_XT.stdout.exp # test_isa_3_1_VRT.vgtest test_isa_3_1_VRT.stderr.exp test_isa_3_1_VRT.stdout.exp # test_isa_3_1_Misc.vgtest test_isa_3_1_Misc.stderr.exp test_isa_3_1_Misc.stdout.exp # test_isa_3_1_AT.vgtest test_isa_3_1_AT.stderr.exp test_isa_3_1_AT.stdout.exp @@ -64,11 +64,11 @@ check_PROGRAMS = \ test_dfp1 test_dfp2 test_dfp3 test_dfp4 test_dfp5 \ test_isa_2_07_part1 test_isa_2_07_part2 \ test_isa_3_0 \ + test_isa_3_1_RT test_isa_3_1_XT \ subnormal_test \ test_tm test_touch_tm ldst_multiple data-cache-instructions \ power6_mf_gpr std_reg_imm \ twi_tdi tw_td power6_bcmp -# test_isa_3_1_RT test_isa_3_1_XT # test_isa_3_1_Misc test_isa_3_1_VRT test_isa_3_1_AT AM_CFLAGS += @FLAG_M64@ @@ -77,8 +77,9 @@ AM_CCASFLAGS += @FLAG_M64@ allexec_CFLAGS = $(AM_CFLAGS) @FLAG_W_NO_NONNULL@ -#test_isa_3_1_XT_SOURCES = test_isa_3_1_XT.c test_isa_3_1_common.c -#test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c +test_isa_3_1_XT_SOURCES = test_isa_3_1_XT.c test_isa_3_1_common.c +test_isa_3_1_RT_SOURCES = test_isa_3_1_RT.c test_isa_3_1_common.c + #test_isa_3_1_VRT_SOURCES = test_isa_3_1_VRT.c test_isa_3_1_common.c #test_isa_3_1_AT_SOURCES = test_isa_3_1_AT.c test_isa_3_1_common.c #test_isa_3_1_Misc_SOURCES = test_isa_3_1_Misc.c test_isa_3_1_common.c diff --git a/none/tests/ppc64/test_isa_3_1_RT.c b/none/tests/ppc64/test_isa_3_1_RT.c new file mode 100644 index 0000000000..fc33c76722 --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_RT.c @@ -0,0 +1,507 @@ +/* + * Valgrind testcase for PowerPC ISA 3.1 + * + * Copyright (C) 2019-2020 Will Schmidt + * + * 64bit build: + * gcc -Winline -Wall -g -O -mregnames -maltivec -m64 + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Condition Register fields. + These are used to capture the condition register values immediately after + the instruction under test is executed. This is done to help prevent other + test overhead (switch statements, result compares, etc) from disturbing + the test case results. */ +unsigned long current_cr; +unsigned long current_fpscr; + + +struct test_list_t current_test; + +#include "isa_3_1_helpers.h" + +#ifdef HAS_ISA_3_1 + +static void test_plbz_off0 (void) { + __asm__ __volatile__ ("plbz %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plbz_off8 (void) { + __asm__ __volatile__ ("plbz %0, 8(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plbz_off16 (void) { + __asm__ __volatile__ ("plbz %0, 16(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plbz_off32 (void) { + __asm__ __volatile__ ("plbz %0, 32(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plbz_off64 (void) { + __asm__ __volatile__ ("plbz %0, 64(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plhz_off0 (void) { + __asm__ __volatile__ ("plhz %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plhz_off8 (void) { + __asm__ __volatile__ ("plhz %0, 8(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plhz_off16 (void) { + __asm__ __volatile__ ("plhz %0, 16(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plhz_off32 (void) { + __asm__ __volatile__ ("plhz %0, 32(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plhz_off64 (void) { + __asm__ __volatile__ ("plhz %0, 64(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plha_off0 (void) { + __asm__ __volatile__ ("plha %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plha_off8 (void) { + __asm__ __volatile__ ("plha %0, 8(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plha_off16 (void) { + __asm__ __volatile__ ("plha %0, 16(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plha_off32 (void) { + __asm__ __volatile__ ("plha %0, 32(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plha_off64 (void) { + __asm__ __volatile__ ("plha %0, 64(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwz_off0 (void) { + __asm__ __volatile__ ("plwz %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwz_off8 (void) { + __asm__ __volatile__ ("plwz %0, 8(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwz_off16 (void) { + __asm__ __volatile__ ("plwz %0, 16(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwz_off32 (void) { + __asm__ __volatile__ ("plwz %0, 32(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwz_off64 (void) { + __asm__ __volatile__ ("plwz %0, 64(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwa_off0 (void) { + __asm__ __volatile__ ("plwa %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwa_off8 (void) { + __asm__ __volatile__ ("plwa %0, 8(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwa_off16 (void) { + __asm__ __volatile__ ("plwa %0, 16(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwa_off32 (void) { + __asm__ __volatile__ ("plwa %0, 32(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plwa_off64 (void) { + __asm__ __volatile__ ("plwa %0, 64(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_pld_off0 (void) { + __asm__ __volatile__ ("pld %0, 0(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_pld_off8 (void) { + __asm__ __volatile__ ("pld %0, 8(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_pld_off16 (void) { + __asm__ __volatile__ ("pld %0, 16(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_pld_off32 (void) { + __asm__ __volatile__ ("pld %0, 32(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_pld_off64 (void) { + __asm__ __volatile__ ("pld %0, 64(%1), 0" : "=r" (rt) : "r" (ra) ); +} +static void test_pstb_off0 (void) { + __asm__ __volatile__ ("pstb %0, 0(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstb_off8 (void) { + __asm__ __volatile__ ("pstb %0, 8(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstb_off16 (void) { + __asm__ __volatile__ ("pstb %0, 16(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstb_off32 (void) { + __asm__ __volatile__ ("pstb %0, 32(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_psth_off0 (void) { + __asm__ __volatile__ ("psth %0, 0(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_psth_off8 (void) { + __asm__ __volatile__ ("psth %0, 8(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_psth_off16 (void) { + __asm__ __volatile__ ("psth %0, 16(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_psth_off32 (void) { + __asm__ __volatile__ ("psth %0, 32(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstw_off0 (void) { + __asm__ __volatile__ ("pstw %0, 0(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstw_off8 (void) { + __asm__ __volatile__ ("pstw %0, 8(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstw_off16 (void) { + __asm__ __volatile__ ("pstw %0, 16(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstw_off32 (void) { + __asm__ __volatile__ ("pstw %0, 32(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstd_off0 (void) { + __asm__ __volatile__ ("pstd %0, 0(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstd_off8 (void) { + __asm__ __volatile__ ("pstd %0, 8(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstd_off16 (void) { + __asm__ __volatile__ ("pstd %0, 16(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_pstd_off32 (void) { + __asm__ __volatile__ ("pstd %0, 32(%1), 0" :: "r" (rs), "r" (ra) ); +} +static void test_paddi_0 (void) { + __asm__ __volatile__ ("paddi %0, %1, 0, 0" : "=r" (rt) : "r" (ra) ); +} +static void test_paddi_12 (void) { + __asm__ __volatile__ ("paddi %0, %1, 12, 0" : "=r" (rt) : "r" (ra) ); +} +static void test_paddi_48 (void) { + __asm__ __volatile__ ("paddi %0, %1, 48, 0" : "=r" (rt) : "r" (ra) ); +} +static void test_paddi_98 (void) { + __asm__ __volatile__ ("paddi %0, %1, 98, 0" : "=r" (rt) : "r" (ra) ); +} +static void test_plq_off0 (void) { + __asm__ __volatile__ ("plq 26, 0(%0), 0" :: "r" (ra) ); +} +static void test_plq_off8 (void) { + __asm__ __volatile__ ("plq 26, 8(%0), 0" :: "r" (ra) ); +} +static void test_plq_off16 (void) { + __asm__ __volatile__ ("plq 26, 16(%0), 0" :: "r" (ra) ); +} +static void test_plq_off32 (void) { + __asm__ __volatile__ ("plq 26, 32(%0), 0" :: "r" (ra) ); +} +static void test_plq_off48 (void) { + __asm__ __volatile__ ("plq 26, 48(%0), 0" :: "r" (ra) ); +} +static void test_plq_off64 (void) { + __asm__ __volatile__ ("plq 26, 64(%0), 0" :: "r" (ra) ); +} +static void test_pstq_off0 (void) { + __asm__ __volatile__ ("pstq 24, 0(%0), 0" :: "r" (ra) ); +} +static void test_pstq_off8 (void) { + __asm__ __volatile__ ("pstq 24, 8(%0), 0" :: "r" (ra) ); +} +static void test_pstq_off16 (void) { + __asm__ __volatile__ ("pstq 24, 16(%0), 0" :: "r" (ra) ); +} +static void test_pstq_off32 (void) { + __asm__ __volatile__ ("pstq 24, 32(%0), 0" :: "r" (ra) ); +} +static void test_pstq_off64 (void) { + __asm__ __volatile__ ("pstq 24, 64(%0), 0" :: "r" (ra) ); +} + +static test_list_t testgroup_generic[] = { + { &test_paddi_0, "paddi 0", "RT,RA,SI,R"}, /* bcwp */ + { &test_paddi_12, "paddi 12", "RT,RA,SI,R"}, /* bcwp */ + { &test_paddi_48, "paddi 48", "RT,RA,SI,R"}, /* bcwp */ + { &test_paddi_98, "paddi 98", "RT,RA,SI,R"}, /* bcwp */ + { &test_plbz_off0, "plbz off0", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off8, "plbz off8", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off16, "plbz off16", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off32, "plbz off32", "RT,D(RA),R"}, /* bcwp */ + { &test_plbz_off64, "plbz off64", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off0, "pld off0", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off8, "pld off8", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off16, "pld off16", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off32, "pld off32", "RT,D(RA),R"}, /* bcwp */ + { &test_pld_off64, "pld off64", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off0, "plha off0", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off8, "plha off8", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off16, "plha off16", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off32, "plha off32", "RT,D(RA),R"}, /* bcwp */ + { &test_plha_off64, "plha off64", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off0, "plhz off0", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off8, "plhz off8", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off16, "plhz off16", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off32, "plhz off32", "RT,D(RA),R"}, /* bcwp */ + { &test_plhz_off64, "plhz off64", "RT,D(RA),R"}, /* bcwp */ + { &test_plq_off0, "plq off0", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off8, "plq off8", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off16, "plq off16", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off32, "plq off32", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off48, "plq off48", "RTp,D(RA),R"}, /* bcwp */ + { &test_plq_off64, "plq off64", "RTp,D(RA),R"}, /* bcwp */ + { &test_plwa_off0, "plwa off0", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off8, "plwa off8", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off16, "plwa off16", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off32, "plwa off32", "RT,D(RA),R"}, /* bcwp */ + { &test_plwa_off64, "plwa off64", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off0, "plwz off0", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off8, "plwz off8", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off16, "plwz off16", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off32, "plwz off32", "RT,D(RA),R"}, /* bcwp */ + { &test_plwz_off64, "plwz off64", "RT,D(RA),R"}, /* bcwp */ + { &test_pstb_off0, "pstb off0", "RS,D(RA),R"}, /* bcwp */ + { &test_pstb_off8, "pstb off8", "RS,D(RA),R"}, /* bcwp */ + { &test_pstb_off16, "pstb off16", "RS,D(RA),R"}, /* bcwp */ + { &test_pstb_off32, "pstb off32", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off0, "pstd off0", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off8, "pstd off8", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off16, "pstd off16", "RS,D(RA),R"}, /* bcwp */ + { &test_pstd_off32, "pstd off32", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off0, "psth off0", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off8, "psth off8", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off16, "psth off16", "RS,D(RA),R"}, /* bcwp */ + { &test_psth_off32, "psth off32", "RS,D(RA),R"}, /* bcwp */ + { &test_pstq_off0, "pstq off0", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off8, "pstq off8", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off16, "pstq off16", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off32, "pstq off32", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstq_off64, "pstq off64", "RSp,D(RA),R"}, /* bcwp */ + { &test_pstw_off0, "pstw off0", "RS,D(RA),R"}, /* bcwp */ + { &test_pstw_off8, "pstw off8", "RS,D(RA),R"}, /* bcwp */ + { &test_pstw_off16, "pstw off16", "RS,D(RA),R"}, /* bcwp */ + { &test_pstw_off32, "pstw off32", "RS,D(RA),R"}, /* bcwp */ + { NULL, NULL }, +}; + +/* Allow skipping of tests. */ +unsigned long test_count=0xffff; +unsigned long skip_count=0; +unsigned long setup_only=0; + +/* Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs. */ +static jmp_buf mybuf; + +/* This (testfunction_generic) is meant to handle all of the instruction + variations. The helpers set up the register and iterator values + as is appropriate for the instruction being tested. */ +static void testfunction_generic (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags, + char * cur_form) { + + identify_form_components (instruction_name , cur_form); + debug_show_form (instruction_name, cur_form); + set_up_iterators (); + debug_show_iter_ranges (); + initialize_buffer (0); + debug_dump_buffer (); + + for (vrai = 0; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = 0; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = 0; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = 0; (vrmi < m_iters) ; vrmi+=m_inc) { + CHECK_OVERRIDES + debug_show_current_iteration (); + // Be sure to initialize the target registers first. + initialize_target_registers (); + initialize_source_registers (); + printf ("%s", instruction_name); + print_register_header (); + printf( " =>"); fflush (stdout); + if (!setup_only) { + if (enable_setjmp) { + if ( setjmp ( mybuf ) ) { + printf("signal tripped. (FIXME)\n"); + continue; + } + } + (*test_function) (); + } + print_register_footer (); + print_result_buffer (); + printf ("\n"); + } + } + } + } +} + +void mykillhandler ( int x ) { longjmp (mybuf, 1); } +void mysegvhandler ( int x ) { longjmp (mybuf, 1); } + +static void do_tests ( void ) +{ + int groupcount; + char * cur_form; + test_group_t group_function = &testfunction_generic; + test_list_t *tests = testgroup_generic; + + struct sigaction kill_action, segv_action; + struct sigaction old_kill_action, old_segv_action; + if (enable_setjmp) { + kill_action.sa_handler = mykillhandler; + segv_action.sa_handler = mysegvhandler; + sigemptyset ( &kill_action.sa_mask ); + sigemptyset ( &segv_action.sa_mask ); + kill_action.sa_flags = SA_NODEFER; + segv_action.sa_flags = SA_NODEFER; + sigaction ( SIGILL, &kill_action, &old_kill_action); + sigaction ( SIGSEGV, &segv_action, &old_segv_action); + } + + for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) { + cur_form = strdup(tests[groupcount].form); + current_test = tests[groupcount]; + if (groupcount < skip_count) continue; + if (verbose) printf("Test #%d ,", groupcount); + if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose); + (*group_function) (current_test.name, current_test.func, 0, cur_form ); + printf ("\n"); + if (groupcount >= (skip_count+test_count)) break; + } + if (debug_show_labels) printf("\n"); + printf ("All done. Tested %d different instruction groups\n", groupcount); +} + +static void usage (void) +{ + fprintf(stderr, + "Usage: test_isa_XXX [OPTIONS]\n" + "\t-h: display this help and exit\n" + "\t-v: increase verbosity\n" + "\t-a : limit number of a-iterations to \n" + "\t-b : limit number of b-iterations to \n" + "\t-c : limit number of c-iterations to \n" + "\t-n : limit to this number of tests.\n" + "\t-r : run only test # \n" + "\t\n" + "\t-j :enable setjmp to recover from illegal insns. \n" + "\t-m :(dev only?) lock VRM value to zero.\n" + "\t-z :(dev only?) lock MC value to zero.\n" + "\t-p :(dev only?) disable prefix instructions\n" + "\t-s : skip tests \n" + "\t-c : stop after running # of tests \n" + "\t-f : Do the test setup but do not actually execute the test instruction. \n" + ); +} + +int main (int argc, char **argv) +{ + int c; + while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) { + switch (c) { + case 'h': + usage(); + return 0; + + case 'v': + verbose++; + break; + + /* Options related to limiting the test iterations. */ + case 'a': + a_limit=atoi (optarg); + printf ("limiting a-iters to %ld.\n", a_limit); + break; + case 'b': + b_limit=atoi (optarg); + printf ("limiting b-iters to %ld.\n", b_limit); + break; + case 'c': + c_limit=atoi (optarg); + printf ("limiting c-iters to %ld.\n", c_limit); + break; + case 'n': // run this number of tests. + test_count=atoi (optarg); + printf ("limiting to %ld tests\n", test_count); + break; + case 'r': // run just test #. + skip_count=atoi (optarg); + test_count=0; + if (verbose) printf("Running only test number %ld\n", skip_count); + break; + case 's': // skip this number of tests. + skip_count=atoi (optarg); + printf ("skipping %ld tests\n", skip_count); + break; + + /* debug options. */ + case 'd': + dump_tables=1; + printf("DEBUG:dump_tables.\n"); + break; + case 'f': + setup_only=1; + printf("DEBUG:setup_only.\n"); + break; + case 'j': + enable_setjmp=1; + printf ("DEBUG:setjmp enabled.\n"); + break; + case 'm': + vrm_override=1; + printf ("DEBUG:vrm override enabled.\n"); + break; + case 'p': + prefix_override=1; + printf ("DEBUG:prefix override enabled.\n"); + break; + case 'z': + mc_override=1; + printf ("DEBUG:MC override enabled.\n"); + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + } + } + + generic_prologue (); + build_vsx_table (); + build_args_table (); + build_float_vsx_tables (); + + if (dump_tables) { + dump_float_vsx_tables (); + dump_vsxargs (); + } + + do_tests (); + + return 0; +} + +#else // HAS_ISA_3_1 +int main (int argc, char **argv) +{ + printf("NO ISA 3.1 SUPPORT\n"); + return 0; +} +#endif diff --git a/none/tests/ppc64/test_isa_3_1_RT.stderr.exp b/none/tests/ppc64/test_isa_3_1_RT.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_RT.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_isa_3_1_RT.stdout.exp b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp new file mode 100644 index 0000000000..4ebe7e162a --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_RT.stdout.exp @@ -0,0 +1,148 @@ +paddi 0 102030405060708 => 102030405060708 +paddi 0 a5b4c3d2e1f00918 => a5b4c3d2e1f00918 +paddi 0 fff7fffafff3fff1 => fff7fffafff3fff1 +paddi 0 7ff7000100030005 => 7ff7000100030005 +paddi 0 ffe7111022203330 => ffe7111022203330 +paddi 0 0 => 0 + +paddi 12 102030405060708 => 102030405060714 +paddi 12 a5b4c3d2e1f00918 => a5b4c3d2e1f00924 +paddi 12 fff7fffafff3fff1 => fff7fffafff3fffd +paddi 12 7ff7000100030005 => 7ff7000100030011 +paddi 12 ffe7111022203330 => ffe711102220333c +paddi 12 0 => c + +paddi 48 102030405060708 => 102030405060738 +paddi 48 a5b4c3d2e1f00918 => a5b4c3d2e1f00948 +paddi 48 fff7fffafff3fff1 => fff7fffafff40021 +paddi 48 7ff7000100030005 => 7ff7000100030035 +paddi 48 ffe7111022203330 => ffe7111022203360 +paddi 48 0 => 30 + +paddi 98 102030405060708 => 10203040506076a +paddi 98 a5b4c3d2e1f00918 => a5b4c3d2e1f0097a +paddi 98 fff7fffafff3fff1 => fff7fffafff40053 +paddi 98 7ff7000100030005 => 7ff7000100030067 +paddi 98 ffe7111022203330 => ffe7111022203392 +paddi 98 0 => 62 + +plbz off0 (&buffer) => 59 + +plbz off8 (&buffer) => 7 + +plbz off16 (&buffer) => 0 + +plbz off32 (&buffer) => 5 + +plbz off64 (&buffer) => 88 + +pld off0 (&buffer) => 3fe00094e0007359 + +pld off8 (&buffer) => 7ff7020304057607 + +pld off16 (&buffer) => 7ff0000000007000 + +pld off32 (&buffer) => 5a05a05a05a07a05 + +pld off64 (&buffer) => ffeeddccbbaa7988 + +plha off0 (&buffer) => 7359 + +plha off8 (&buffer) => 7607 + +plha off16 (&buffer) => 7000 + +plha off32 (&buffer) => 7a05 + +plha off64 (&buffer) => 7988 + +plhz off0 (&buffer) => 7359 + +plhz off8 (&buffer) => 7607 + +plhz off16 (&buffer) => 7000 + +plhz off32 (&buffer) => 7a05 + +plhz off64 (&buffer) => 7988 + +plq off0 (&buffer) => 3fe00094e0007359 7ff7020304057607 + +plq off8 (&buffer) => 7ff7020304057607 7ff0000000007000 + +plq off16 (&buffer) => 7ff0000000007000 7f0000007f007000 + +plq off32 (&buffer) => 5a05a05a05a07a05 102030405067708 + +plq off48 (&buffer) => fedcba9876547210 123456789ab7def + +plq off64 (&buffer) => ffeeddccbbaa7988 1112111211127112 + +plwa off0 (&buffer) => ffffffffe0007359 + +plwa off8 (&buffer) => 4057607 + +plwa off16 (&buffer) => 7000 + +plwa off32 (&buffer) => 5a07a05 + +plwa off64 (&buffer) => ffffffffbbaa7988 + +plwz off0 (&buffer) => e0007359 + +plwz off8 (&buffer) => 4057607 + +plwz off16 (&buffer) => 7000 + +plwz off32 (&buffer) => 5a07a05 + +plwz off64 (&buffer) => bbaa7988 + +pstb off0 (&buffer) 102030405060708 => [3fe00094e0007308 - - - - - - - ] + +pstb off8 (&buffer) 102030405060708 => [ - 7ff7020304057608 - - - - - - ] + +pstb off16 (&buffer) 102030405060708 => [ - - 7ff0000000007008 - - - - - ] + +pstb off32 (&buffer) 102030405060708 => [ - - - - 5a05a05a05a07a08 - - - ] + +pstd off0 (&buffer) 102030405060708 => [0102030405060708 - - - - - - - ] + +pstd off8 (&buffer) 102030405060708 => [ - 0102030405060708 - - - - - - ] + +pstd off16 (&buffer) 102030405060708 => [ - - 0102030405060708 - - - - - ] + +pstd off32 (&buffer) 102030405060708 => [ - - - - 0102030405060708 - - - ] + +psth off0 (&buffer) 102030405060708 => [3fe00094e0000708 - - - - - - - ] + +psth off8 (&buffer) 102030405060708 => [ - 7ff7020304050708 - - - - - - ] + +psth off16 (&buffer) 102030405060708 => [ - - 7ff0000000000708 - - - - - ] + +psth off32 (&buffer) 102030405060708 => [ - - - - 5a05a05a05a00708 - - - ] + +pstq off0 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [0102030405060708 a5b4c3d2e1f00918 - - - - - - ] +pstq off0 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [0102030405060708 a5b4c3d2e1f00918 - - - - - - ] + +pstq off8 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [ - 0102030405060708 a5b4c3d2e1f00918 - - - - - ] +pstq off8 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [ - 0102030405060708 a5b4c3d2e1f00918 - - - - - ] + +pstq off16 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [ - - 0102030405060708 a5b4c3d2e1f00918 - - - - ] +pstq off16 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [ - - 0102030405060708 a5b4c3d2e1f00918 - - - - ] + +pstq off32 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [ - - - - 0102030405060708 a5b4c3d2e1f00918 - - ] +pstq off32 (&buffer) 102030405060708 a5b4c3d2e1f00918 => [ - - - - 0102030405060708 a5b4c3d2e1f00918 - - ] + +pstq off64 (&buffer) 102030405060708 a5b4c3d2e1f00918 => +pstq off64 (&buffer) 102030405060708 a5b4c3d2e1f00918 => + +pstw off0 (&buffer) 102030405060708 => [3fe0009405060708 - - - - - - - ] + +pstw off8 (&buffer) 102030405060708 => [ - 7ff7020305060708 - - - - - - ] + +pstw off16 (&buffer) 102030405060708 => [ - - 7ff0000005060708 - - - - - ] + +pstw off32 (&buffer) 102030405060708 => [ - - - - 5a05a05a05060708 - - - ] + +All done. Tested 61 different instruction groups diff --git a/none/tests/ppc64/test_isa_3_1_XT.c b/none/tests/ppc64/test_isa_3_1_XT.c new file mode 100644 index 0000000000..dfe11c3c6c --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_XT.c @@ -0,0 +1,479 @@ +/* + * Valgrind testcase for PowerPC ISA 3.1 + * + * Copyright (C) 2019-2020 Will Schmidt + * + * 64bit build: + * gcc -Winline -Wall -g -O -mregnames -maltivec -m64 + */ + +/* + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of the + * License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +/* Condition Register fields. + These are used to capture the condition register values immediately after + the instruction under test is executed. This is done to help prevent other + test overhead (switch statements, result compares, etc) from disturbing + the test case results. */ +unsigned long current_cr; +unsigned long current_fpscr; + + +struct test_list_t current_test; + +#include "isa_3_1_helpers.h" + +#ifdef HAS_ISA_3_1 + +static void test_plfd_64 (void) { + __asm__ __volatile__ ("plfd 28, 64(%0), 0" :: "r" (ra) ); +} +static void test_plfd_32 (void) { + __asm__ __volatile__ ("plfd 28, 32(%0), 0" :: "r" (ra) ); +} +static void test_plfd_16 (void) { + __asm__ __volatile__ ("plfd 28, 16(%0), 0" :: "r" (ra) ); +} +static void test_plfd_8 (void) { + __asm__ __volatile__ ("plfd 28, 8(%0), 0" :: "r" (ra) ); +} +static void test_plfd_4 (void) { + __asm__ __volatile__ ("plfd 28, 4(%0), 0" :: "r" (ra) ); +} +static void test_plfd_0 (void) { + __asm__ __volatile__ ("plfd 28, 0(%0), 0" :: "r" (ra) ); +} +static void test_plfs_64 (void) { + __asm__ __volatile__ ("plfs 28, 64(%0), 0" :: "r" (ra) ); +} +static void test_plfs_32 (void) { + __asm__ __volatile__ ("plfs 28, 32(%0), 0" :: "r" (ra) ); +} +static void test_plfs_16 (void) { + __asm__ __volatile__ ("plfs 28, 16(%0), 0" :: "r" (ra) ); +} +static void test_plfs_8 (void) { + __asm__ __volatile__ ("plfs 28, 8(%0), 0" :: "r" (ra) ); +} +static void test_plfs_4 (void) { + __asm__ __volatile__ ("plfs 28, 4(%0), 0" :: "r" (ra) ); +} +static void test_plfs_0 (void) { + __asm__ __volatile__ ("plfs 28, 0(%0), 0" :: "r" (ra) ); +} +static void test_pstfd_32 (void) { + __asm__ __volatile__ ("pstfd 26, 32(%0), 0" :: "r" (ra) ); +} +static void test_pstfd_16 (void) { + __asm__ __volatile__ ("pstfd 26, 16(%0), 0" :: "r" (ra) ); +} +static void test_pstfd_8 (void) { + __asm__ __volatile__ ("pstfd 26, 8(%0), 0" :: "r" (ra) ); +} +static void test_pstfd_4 (void) { + __asm__ __volatile__ ("pstfd 26, 4(%0), 0" :: "r" (ra) ); +} +static void test_pstfd_0 (void) { + __asm__ __volatile__ ("pstfd 26, 0(%0), 0" :: "r" (ra) ); +} +static void test_pstfs_32 (void) { + __asm__ __volatile__ ("pstfs 26, 32(%0), 0" :: "r" (ra) ); +} +static void test_pstfs_16 (void) { + __asm__ __volatile__ ("pstfs 26, 16(%0), 0" :: "r" (ra) ); +} +static void test_pstfs_8 (void) { + __asm__ __volatile__ ("pstfs 26, 8(%0), 0" :: "r" (ra) ); +} +static void test_pstfs_4 (void) { + __asm__ __volatile__ ("pstfs 26, 4(%0), 0" :: "r" (ra) ); +} +static void test_pstfs_0 (void) { + __asm__ __volatile__ ("pstfs 26, 0(%0), 0" :: "r" (ra) ); +} +static void test_plxsd_64 (void) { + __asm__ __volatile__ ("plxsd %0, 64(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxsd_32 (void) { + __asm__ __volatile__ ("plxsd %0, 32(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxsd_16 (void) { + __asm__ __volatile__ ("plxsd %0, 16(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxsd_8 (void) { + __asm__ __volatile__ ("plxsd %0, 8(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxsd_4 (void) { + __asm__ __volatile__ ("plxsd %0, 4(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxsd_0 (void) { + __asm__ __volatile__ ("plxsd %0, 0(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxssp_64 (void) { + __asm__ __volatile__ ("plxssp %0, 64(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxssp_32 (void) { + __asm__ __volatile__ ("plxssp %0, 32(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxssp_16 (void) { + __asm__ __volatile__ ("plxssp %0, 16(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxssp_8 (void) { + __asm__ __volatile__ ("plxssp %0, 8(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxssp_4 (void) { + __asm__ __volatile__ ("plxssp %0, 4(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxssp_0 (void) { + __asm__ __volatile__ ("plxssp %0, 0(%1), 0" : "=v" (vrt) : "r" (ra) ); +} +static void test_plxv_16_0 (void) { + __asm__ __volatile__ ("plxv %x0, 16(%1), 0" : "=wa" (vec_xt) : "r" (ra) ); +} +static void test_plxv_8_0 (void) { + __asm__ __volatile__ ("plxv %x0, 8(%1), 0" : "=wa" (vec_xt) : "r" (ra) ); +} +static void test_plxv_4_0 (void) { + __asm__ __volatile__ ("plxv %x0, 4(%1), 0" : "=wa" (vec_xt) : "r" (ra) ); +} +static void test_plxv_0_0 (void) { + __asm__ __volatile__ ("plxv %x0, 0(%1), 0" : "=wa" (vec_xt) : "r" (ra) ); +} +static void test_pstxsd_64 (void) { + __asm__ __volatile__ ("pstxsd 22, 64(%0), 0" :: "r" (ra) ); +} +static void test_pstxsd_32 (void) { + __asm__ __volatile__ ("pstxsd 22, 32(%0), 0" :: "r" (ra) ); +} +static void test_pstxsd_16 (void) { + __asm__ __volatile__ ("pstxsd 22, 16(%0), 0" :: "r" (ra) ); +} +static void test_pstxsd_8 (void) { + __asm__ __volatile__ ("pstxsd 22, 8(%0), 0" :: "r" (ra) ); +} +static void test_pstxsd_4 (void) { + __asm__ __volatile__ ("pstxsd 22, 4(%0), 0" :: "r" (ra) ); +} +static void test_pstxsd_0 (void) { + __asm__ __volatile__ ("pstxsd 22, 0(%0), 0" :: "r" (ra) ); +} +static void test_pstxssp_64 (void) { + __asm__ __volatile__ ("pstxssp 22, 64(%0), 0" :: "r" (ra) ); +} +static void test_pstxssp_32 (void) { + __asm__ __volatile__ ("pstxssp 22, 32(%0), 0" :: "r" (ra) ); +} +static void test_pstxssp_16 (void) { + __asm__ __volatile__ ("pstxssp 22, 16(%0), 0" :: "r" (ra) ); +} +static void test_pstxssp_8 (void) { + __asm__ __volatile__ ("pstxssp 22, 8(%0), 0" :: "r" (ra) ); +} +static void test_pstxssp_4 (void) { + __asm__ __volatile__ ("pstxssp 22, 4(%0), 0" :: "r" (ra) ); +} +static void test_pstxssp_0 (void) { + __asm__ __volatile__ ("pstxssp 22, 0(%0), 0" :: "r" (ra) ); +} +static void test_pstxv_16 (void) { + __asm__ __volatile__ ("pstxv %x0, 16(%1), 0" :: "wa" (vec_xs), "r" (ra) ); +} +static void test_pstxv_8 (void) { + __asm__ __volatile__ ("pstxv %x0, 8(%1), 0" :: "wa" (vec_xs), "r" (ra) ); +} +static void test_pstxv_4 (void) { + __asm__ __volatile__ ("pstxv %x0, 4(%1), 0" :: "wa" (vec_xs), "r" (ra) ); +} +static void test_pstxv_0 (void) { + __asm__ __volatile__ ("pstxv %x0, 0(%1), 0" :: "wa" (vec_xs), "r" (ra) ); +} + +static test_list_t testgroup_generic[] = { + { &test_plfd_0, "plfd 0", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_4, "plfd 4", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_8, "plfd 8", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_16, "plfd 16", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_32, "plfd 32", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfd_64, "plfd 64", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_0, "plfs 0", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_4, "plfs 4", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_8, "plfs 8", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_16, "plfs 16", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_32, "plfs 32", "FRT,D(RA),R"}, /* bcwp */ + { &test_plfs_64, "plfs 64", "FRT,D(RA),R"}, /* bcwp */ + { &test_plxsd_0, "plxsd 0", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_4, "plxsd 4", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_8, "plxsd 8", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_16, "plxsd 16", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_32, "plxsd 32", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxsd_64, "plxsd 64", "VRT,D(RA),R", 0b00110000}, /* bcwp */ + { &test_plxssp_0, "plxssp 0", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_4, "plxssp 4", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_8, "plxssp 8", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_16, "plxssp 16", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_32, "plxssp 32", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxssp_64, "plxssp 64", "VRT,D(RA),R", 0b00001111}, /* bcwp */ + { &test_plxv_0_0, "plxv 0_0", "XT,D(RA),R"}, /* bcwp */ + { &test_plxv_4_0, "plxv 4_0", "XT,D(RA),R"}, /* bcwp */ + { &test_plxv_8_0, "plxv 8_0", "XT,D(RA),R"}, /* bcwp */ + { &test_plxv_16_0, "plxv 16_0", "XT,D(RA),R"}, /* bcwp */ + { &test_pstfd_0, "pstfd 0", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_4, "pstfd 4", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_8, "pstfd 8", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_16, "pstfd 16", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfd_32, "pstfd 32", "FRS,D(RA),R", 0b00110000}, /* bcwp */ + { &test_pstfs_0, "pstfs 0", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_4, "pstfs 4", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_8, "pstfs 8", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_16, "pstfs 16", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstfs_32, "pstfs 32", "FRS,D(RA),R", 0b00001111}, /* bcwp */ + { &test_pstxsd_0, "pstxsd 0", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_4, "pstxsd 4", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_8, "pstxsd 8", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_16, "pstxsd 16", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_32, "pstxsd 32", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxsd_64, "pstxsd 64", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_0, "pstxssp 0", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_4, "pstxssp 4", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_8, "pstxssp 8", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_16, "pstxssp 16", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_32, "pstxssp 32", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxssp_64, "pstxssp 64", "VRS,D(RA),R"}, /* bcwp */ + { &test_pstxv_0, "pstxv 0", "XS,D(RA),R"}, /* bcwp */ + { &test_pstxv_4, "pstxv 4", "XS,D(RA),R"}, /* bcwp */ + { &test_pstxv_8, "pstxv 8", "XS,D(RA),R"}, /* bcwp */ + { &test_pstxv_16, "pstxv 16", "XS,D(RA),R"}, /* bcwp */ + { NULL, NULL }, +}; + +/* Allow skipping of tests. */ +unsigned long test_count=0xffff; +unsigned long skip_count=0; +unsigned long setup_only=0; + +/* Set up a setjmp/longjmp to gently handle our SIGILLs and SIGSEGVs. */ +static jmp_buf mybuf; + +/* This (testfunction_generic) is meant to handle all of the instruction + variations. The helpers set up the register and iterator values + as is appropriate for the instruction being tested. */ +static void testfunction_generic (const char* instruction_name, + test_func_t test_function, + unsigned int ignore_flags, + char * cur_form) { + + identify_form_components (instruction_name , cur_form); + debug_show_form (instruction_name, cur_form); + set_up_iterators (); + debug_show_iter_ranges (); + initialize_buffer (0); + debug_dump_buffer (); + + for (vrai = 0; vrai < a_iters ; vrai+=a_inc) { + for (vrbi = 0; vrbi < b_iters ; vrbi+=b_inc) { + for (vrci = 0; vrci < c_iters ; vrci+=c_inc) { + for (vrmi = 0; (vrmi < m_iters) ; vrmi+=m_inc) { + CHECK_OVERRIDES + debug_show_current_iteration (); + // Be sure to initialize the target registers first. + initialize_target_registers (); + initialize_source_registers (); + printf ("%s", instruction_name); + print_register_header (); + printf( " =>"); fflush (stdout); + if (!setup_only) { + if (enable_setjmp) { + if ( setjmp ( mybuf ) ) { + printf("signal tripped. (FIXME)\n"); + continue; + } + } + (*test_function) (); + } + print_register_footer (); + print_result_buffer (); + printf ("\n"); + } + } + } + } +} + +void mykillhandler ( int x ) { longjmp (mybuf, 1); } +void mysegvhandler ( int x ) { longjmp (mybuf, 1); } + +static void do_tests ( void ) +{ + int groupcount; + char * cur_form; + test_group_t group_function = &testfunction_generic; + test_list_t *tests = testgroup_generic; + + struct sigaction kill_action, segv_action; + struct sigaction old_kill_action, old_segv_action; + if (enable_setjmp) { + kill_action.sa_handler = mykillhandler; + segv_action.sa_handler = mysegvhandler; + sigemptyset ( &kill_action.sa_mask ); + sigemptyset ( &segv_action.sa_mask ); + kill_action.sa_flags = SA_NODEFER; + segv_action.sa_flags = SA_NODEFER; + sigaction ( SIGILL, &kill_action, &old_kill_action); + sigaction ( SIGSEGV, &segv_action, &old_segv_action); + } + + for (groupcount = 0; tests[groupcount].name != NULL; groupcount++) { + cur_form = strdup(tests[groupcount].form); + current_test = tests[groupcount]; + if (groupcount < skip_count) continue; + if (verbose) printf("Test #%d ,", groupcount); + if (verbose > 1) printf(" instruction %s (v=%d)", current_test.name, verbose); + (*group_function) (current_test.name, current_test.func, 0, cur_form ); + printf ("\n"); + if (groupcount >= (skip_count+test_count)) break; + } + if (debug_show_labels) printf("\n"); + printf ("All done. Tested %d different instruction groups\n", groupcount); +} + +static void usage (void) +{ + fprintf(stderr, + "Usage: test_isa_XXX [OPTIONS]\n" + "\t-h: display this help and exit\n" + "\t-v: increase verbosity\n" + "\t-a : limit number of a-iterations to \n" + "\t-b : limit number of b-iterations to \n" + "\t-c : limit number of c-iterations to \n" + "\t-n : limit to this number of tests.\n" + "\t-r : run only test # \n" + "\t\n" + "\t-j :enable setjmp to recover from illegal insns. \n" + "\t-m :(dev only?) lock VRM value to zero.\n" + "\t-z :(dev only?) lock MC value to zero.\n" + "\t-p :(dev only?) disable prefix instructions\n" + "\t-s : skip tests \n" + "\t-c : stop after running # of tests \n" + "\t-f : Do the test setup but do not actually execute the test instruction. \n" + ); +} + +int main (int argc, char **argv) +{ + int c; + while ((c = getopt(argc, argv, "dhjvmpfzs:a:b:c:n:r:")) != -1) { + switch (c) { + case 'h': + usage(); + return 0; + + case 'v': + verbose++; + break; + + /* Options related to limiting the test iterations. */ + case 'a': + a_limit=atoi (optarg); + printf ("limiting a-iters to %ld.\n", a_limit); + break; + case 'b': + b_limit=atoi (optarg); + printf ("limiting b-iters to %ld.\n", b_limit); + break; + case 'c': + c_limit=atoi (optarg); + printf ("limiting c-iters to %ld.\n", c_limit); + break; + case 'n': // run this number of tests. + test_count=atoi (optarg); + printf ("limiting to %ld tests\n", test_count); + break; + case 'r': // run just test #. + skip_count=atoi (optarg); + test_count=0; + if (verbose) printf("Running only test number %ld\n", skip_count); + break; + case 's': // skip this number of tests. + skip_count=atoi (optarg); + printf ("skipping %ld tests\n", skip_count); + break; + + /* debug options. */ + case 'd': + dump_tables=1; + printf("DEBUG:dump_tables.\n"); + break; + case 'f': + setup_only=1; + printf("DEBUG:setup_only.\n"); + break; + case 'j': + enable_setjmp=1; + printf ("DEBUG:setjmp enabled.\n"); + break; + case 'm': + vrm_override=1; + printf ("DEBUG:vrm override enabled.\n"); + break; + case 'p': + prefix_override=1; + printf ("DEBUG:prefix override enabled.\n"); + break; + case 'z': + mc_override=1; + printf ("DEBUG:MC override enabled.\n"); + break; + default: + usage(); + fprintf(stderr, "Unknown argument: '%c'\n", c); + } + } + + generic_prologue (); + build_vsx_table (); + build_args_table (); + build_float_vsx_tables (); + + if (dump_tables) { + dump_float_vsx_tables (); + dump_vsxargs (); + } + + do_tests (); + + return 0; +} + +#else // HAS_ISA_3_1 +int main (int argc, char **argv) +{ + printf("NO ISA 3.1 SUPPORT\n"); + return 0; +} +#endif diff --git a/none/tests/ppc64/test_isa_3_1_XT.stderr.exp b/none/tests/ppc64/test_isa_3_1_XT.stderr.exp new file mode 100644 index 0000000000..139597f9cb --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_XT.stderr.exp @@ -0,0 +1,2 @@ + + diff --git a/none/tests/ppc64/test_isa_3_1_XT.stdout.exp b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp new file mode 100644 index 0000000000..aec8e1270e --- /dev/null +++ b/none/tests/ppc64/test_isa_3_1_XT.stdout.exp @@ -0,0 +1,119 @@ +plfd 0 (&buffer) => 5.000710e-01 + +plfd 4 (&buffer) => 2.752739e-289 + +plfd 8 (&buffer) => nan + +plfd 16 (&buffer) => nan + +plfd 32 (&buffer) => 4.574798e+125 + +plfd 64 (&buffer) => -1.734010e+308 + +plfs 0 (&buffer) => -3.702336e+19 + +plfs 4 (&buffer) => 1.750018e+00 + +plfs 8 (&buffer) => 1.568827e-36 + +plfs 16 (&buffer) => 4.017803e-41 + +plfs 32 (&buffer) => 1.509115e-35 + +plfs 64 (&buffer) => -5.202476e-03 + +plxsd 0 (&buffer) => 3fe00094e0007359,0000000000000000 5.00070989e-01 +Zero + +plxsd 4 (&buffer) => 40576073fe00094,0000000000000000 2.75273943e-289 +Zero + +plxsd 8 (&buffer) => 7ff7020304057607,0000000000000000 NaN +Zero + +plxsd 16 (&buffer) => 7ff0000000007000,0000000000000000 NaN +Zero + +plxsd 32 (&buffer) => 5a05a05a05a07a05,0000000000000000 4.57479788e+125 +Zero + +plxsd 64 (&buffer) => ffeeddccbbaa7988,0000000000000000 -1.73401015e+308 +Zero + +plxssp 0 (&buffer) => c4000e6b20000000,0000000000000000 -5.12225e+02 1.08420e-19 +Zero +Zero + +plxssp 4 (&buffer) => 3ffc001280000000,0000000000000000 1.96875e+00 -Zero +Zero +Zero + +plxssp 8 (&buffer) => 3880aec0e0000000,0000000000000000 6.13607e-05 -3.68935e+19 +Zero +Zero + +plxssp 16 (&buffer) => 378c000000000000,0000000000000000 1.66893e-05 +Zero +Zero +Zero + +plxssp 32 (&buffer) => 38b40f40a0000000,0000000000000000 8.58591e-05 -1.08420e-19 +Zero +Zero + +plxssp 64 (&buffer) => bf754f3100000000,0000000000000000 -9.58240e-01 +Zero +Zero +Zero + +plxv 0_0 (&buffer) => 3fe00094e0007359 7ff7020304057607 + +plxv 4_0 (&buffer) => 40576073fe00094 70007ff70203 + +plxv 8_0 (&buffer) => 7ff7020304057607 7ff0000000007000 + +plxv 16_0 (&buffer) => 7ff0000000007000 7f0000007f007000 + +pstfd 0 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ { 9.18734324e+18} 43dfe000003fe000 - - - - - - - ] +pstfd 0 (&buffer) 43eff000000ff000 43efefffffcff000 => [ { 1.84107153e+19} 43eff000000ff000 - - - - - - - ] + +pstfd 4 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ { 1.77310647e-307} 003fe000e0007359 { NaN} 7ff7020343dfe000 - - - - - - ] +pstfd 4 (&buffer) 43eff000000ff000 43efefffffcff000 => [ { +Den} 000ff000e0007359 { NaN} 7ff7020343eff000 - - - - - - ] + +pstfd 8 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - { 9.18734324e+18} 43dfe000003fe000 - - - - - - ] +pstfd 8 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - { 1.84107153e+19} 43eff000000ff000 - - - - - - ] + +pstfd 16 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - - { 9.18734324e+18} 43dfe000003fe000 - - - - - ] +pstfd 16 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - - { 1.84107153e+19} 43eff000000ff000 - - - - - ] + +pstfd 32 (&buffer) 43dfe000003fe000 43eff000000ff000 => [ - - - - { 9.18734324e+18} 43dfe000003fe000 - - - ] +pstfd 32 (&buffer) 43eff000000ff000 43efefffffcff000 => [ - - - - { 1.84107153e+19} 43eff000000ff000 - - - ] + +pstfs 0 (&buffer) 000000005eff0000 000000005f7f8000 => [ ( 1.75002e+00 9.18734e+18) 3fe000945eff0000 - - - - - - - ] +pstfs 0 (&buffer) 000000005f7f8000 000000005f7f8000 => [ ( 1.75002e+00 1.84107e+19) 3fe000945f7f8000 - - - - - - - ] + +pstfs 4 (&buffer) 000000005eff0000 000000005f7f8000 => [ ( 9.18734e+18 -3.70234e+19) 5eff0000e0007359 - - - - - - - ] +pstfs 4 (&buffer) 000000005f7f8000 000000005f7f8000 => [ ( 1.84107e+19 -3.70234e+19) 5f7f8000e0007359 - - - - - - - ] + +pstfs 8 (&buffer) 000000005eff0000 000000005f7f8000 => [ - ( NaN 9.18734e+18) 7ff702035eff0000 - - - - - - ] +pstfs 8 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - ( NaN 1.84107e+19) 7ff702035f7f8000 - - - - - - ] + +pstfs 16 (&buffer) 000000005eff0000 000000005f7f8000 => [ - - ( NaN 9.18734e+18) 7ff000005eff0000 - - - - - ] +pstfs 16 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - - ( NaN 1.84107e+19) 7ff000005f7f8000 - - - - - ] + +pstfs 32 (&buffer) 000000005eff0000 000000005f7f8000 => [ - - - - ( 9.40312e+15 9.18734e+18) 5a05a05a5eff0000 - - - ] +pstfs 32 (&buffer) 000000005f7f8000 000000005f7f8000 => [ - - - - ( 9.40312e+15 1.84107e+19) 5a05a05a5f7f8000 - - - ] + +pstxsd 0 (&buffer) => [0000000000000000 - - - - - - - ] + +pstxsd 4 (&buffer) => [00000000e0007359 7ff7020300000000 - - - - - - ] + +pstxsd 8 (&buffer) => [ - 0000000000000000 - - - - - - ] + +pstxsd 16 (&buffer) => [ - - 0000000000000000 - - - - - ] + +pstxsd 32 (&buffer) => [ - - - - 0000000000000000 - - - ] + +pstxsd 64 (&buffer) => + +pstxssp 0 (&buffer) => [3fe0009400000000 - - - - - - - ] + +pstxssp 4 (&buffer) => [00000000e0007359 - - - - - - - ] + +pstxssp 8 (&buffer) => [ - 7ff7020300000000 - - - - - - ] + +pstxssp 16 (&buffer) => [ - - 7ff0000000000000 - - - - - ] + +pstxssp 32 (&buffer) => [ - - - - 5a05a05a00000000 - - - ] + +pstxssp 64 (&buffer) => + +pstxv 0 (&buffer) 7f800000ff800000,ff8000007f800000 => [7f800000ff800000 ff8000007f800000 - - - - - - ] + +pstxv 4 (&buffer) 7f800000ff800000,ff8000007f800000 => [ff800000e0007359 7f8000007f800000 7ff00000ff800000 - - - - - ] + +pstxv 8 (&buffer) 7f800000ff800000,ff8000007f800000 => [ - 7f800000ff800000 ff8000007f800000 - - - - - ] + +pstxv 16 (&buffer) 7f800000ff800000,ff8000007f800000 => [ - - 7f800000ff800000 ff8000007f800000 - - - - ] + +All done. Tested 54 different instruction groups