From: Kito Cheng Date: Thu, 16 Oct 2025 08:41:48 +0000 (+0800) Subject: RISC-V: Add testsuite for fixed-length vector calling convention variant [Part 1] X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=339d585bec6ba36b6e9e0692660ce34f442d7a46;p=thirdparty%2Fgcc.git RISC-V: Add testsuite for fixed-length vector calling convention variant [Part 1] Add comprehensive testsuite for VLS calling convention covering various ABI_VLEN (128, 256) and XLEN (32, 64) combinations. Tests include single vectors, structs, unions, register exhaustion, and mixed type scenarios. This patch adds the test infrastructure and tests for ABI_VLEN 128 and 256. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c: New test. * gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c: New test. * gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_single_register.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h: New test. * gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h: New test. * gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp: New test. * gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c: New test. * gcc.target/riscv/rvv/vls-cc/vls-cc-common.h: New test. --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c new file mode 100644 index 00000000000..7091d2ad9b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c new file mode 100644 index 00000000000..da3ff2ad0e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c new file mode 100644 index 00000000000..907aa706bcc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c new file mode 100644 index 00000000000..3036adaa12f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c new file mode 100644 index 00000000000..1a5788114e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c new file mode 100644 index 00000000000..90ab8c55846 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c new file mode 100644 index 00000000000..43099842c5b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c new file mode 100644 index 00000000000..66cd6269fdf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 00000000000..09def6d7739 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c new file mode 100644 index 00000000000..8cd74f0a383 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c new file mode 100644 index 00000000000..837932c105b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 00000000000..1c1564aa0d5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 00000000000..e44a8af4685 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c new file mode 100644 index 00000000000..8b3b2a1f796 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c new file mode 100644 index 00000000000..32f3de41928 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c new file mode 100644 index 00000000000..ac2ef23dbdb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c new file mode 100644 index 00000000000..5b2ea03b9c2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 00000000000..69623639c5d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 00000000000..0eb676e2882 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c new file mode 100644 index 00000000000..5be696c7294 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c new file mode 100644 index 00000000000..3f3c5e0f264 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 00000000000..3bab9a3d909 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c new file mode 100644 index 00000000000..7ab38ee2df4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 00000000000..6fd3c0bb9bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 00000000000..ca0f8b27746 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c new file mode 100644 index 00000000000..92acb9695f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c new file mode 100644 index 00000000000..201ff4eefa3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c new file mode 100644 index 00000000000..bb928808c2e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c new file mode 100644 index 00000000000..9cfa86629ed --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 00000000000..24478f8e048 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 00000000000..21c918cfe15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 00000000000..f32b61c9549 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 00000000000..8efa10f421f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 00000000000..0204829719c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c new file mode 100644 index 00000000000..8a40a16808d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c new file mode 100644 index 00000000000..94e516cacc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl128b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c new file mode 100644 index 00000000000..12acdaa359c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c new file mode 100644 index 00000000000..ead0e70bc04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c new file mode 100644 index 00000000000..c97a7c7891e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c new file mode 100644 index 00000000000..f3fb86d84e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c new file mode 100644 index 00000000000..7eeaa6bedae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c new file mode 100644 index 00000000000..0676290392c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c new file mode 100644 index 00000000000..dff67ab507d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c new file mode 100644 index 00000000000..40d44425d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 00000000000..2cd13227656 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c new file mode 100644 index 00000000000..6463c5c3513 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c new file mode 100644 index 00000000000..4d84a378e96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 00000000000..7e992f79e04 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 00000000000..ab3027b2e2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v12 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c new file mode 100644 index 00000000000..d16d14bbf43 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c new file mode 100644 index 00000000000..5cd6e52f4a0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c new file mode 100644 index 00000000000..fb4aff99f89 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c new file mode 100644 index 00000000000..3db1d276539 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 00000000000..a8c07f84dc0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 00000000000..0a230ac12bc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c new file mode 100644 index 00000000000..18051f5f5bd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c new file mode 100644 index 00000000000..25a604269b2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 00000000000..c9959ae89e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c new file mode 100644 index 00000000000..3da8d8f6301 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 00000000000..7fc773b7460 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 00000000000..9c3cd7963a1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c new file mode 100644 index 00000000000..42041b553ba --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c new file mode 100644 index 00000000000..9ea145f776e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c new file mode 100644 index 00000000000..a52c0a85391 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c new file mode 100644 index 00000000000..f467fd565c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 00000000000..7d7bedde187 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 00000000000..8e576f2142b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 00000000000..5575aab462a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 00000000000..6e9fd330d8b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 00000000000..734d9293f25 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c new file mode 100644 index 00000000000..743d773a4e5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c new file mode 100644 index 00000000000..dc4623e39fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-128-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl128b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 128 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c new file mode 100644 index 00000000000..6ee556566b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c new file mode 100644 index 00000000000..363dd61a961 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c new file mode 100644 index 00000000000..63e2a844a1f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c new file mode 100644 index 00000000000..5c1269a0d33 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c new file mode 100644 index 00000000000..75805041431 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c new file mode 100644 index 00000000000..1d494e6099c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c new file mode 100644 index 00000000000..9650ea41b3b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c new file mode 100644 index 00000000000..41335d06fbf --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c new file mode 100644 index 00000000000..da85d524553 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c new file mode 100644 index 00000000000..d2d0f07a1aa --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c new file mode 100644 index 00000000000..c11c3e5dc54 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c new file mode 100644 index 00000000000..3862322f1c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c new file mode 100644 index 00000000000..1ec92f3d0fe --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c new file mode 100644 index 00000000000..d0a01e3aa4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c new file mode 100644 index 00000000000..9acf2473c80 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c new file mode 100644 index 00000000000..4d3265c56fd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c new file mode 100644 index 00000000000..63b5ea0eb84 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c new file mode 100644 index 00000000000..8721f444174 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c new file mode 100644 index 00000000000..10efd1e18bb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c new file mode 100644 index 00000000000..ab9055569af --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_unions.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c new file mode 100644 index 00000000000..8ec429b3183 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c new file mode 100644 index 00000000000..bf8f4d1ab47 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c new file mode 100644 index 00000000000..892fa749ebd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c new file mode 100644 index 00000000000..8f280613deb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c new file mode 100644 index 00000000000..e16b94591be --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c new file mode 100644 index 00000000000..9e9c55d2818 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c new file mode 100644 index 00000000000..34f83d6633c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_simple_union.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c new file mode 100644 index 00000000000..141684ca5ad --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c new file mode 100644 index 00000000000..c275b402c72 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c new file mode 100644 index 00000000000..27044519cfb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c new file mode 100644 index 00000000000..30209a79d7a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c new file mode 100644 index 00000000000..3a3f4b1887e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c new file mode 100644 index 00000000000..9822d961624 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c new file mode 100644 index 00000000000..5231401b8f6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+.*\).*\(reg.*:SI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ \[ \.result_ptr \]\).*\(reg.*:SI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:SI \d+ a0\).*\(reg.*:SI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c new file mode 100644 index 00000000000..c313cfc1d46 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c new file mode 100644 index 00000000000..33843a23cec --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-32/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c new file mode 100644 index 00000000000..87d7ac30082 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_128bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_128bit_vector.h" +// Function under test: +// int32x4_t test_128bit_vector(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c new file mode 100644 index 00000000000..1c5b27d8b4a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_256bit_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_256bit_vector.h" +// Function under test: +// int32x8_t test_256bit_vector(int32x8_t vec1, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c new file mode 100644 index 00000000000..b985252f3b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_32bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_32bit_vector.h" +// Function under test: +// int16x2_t test_32bit_vector(int16x2_t vec1, int16x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2HI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2HI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2HI \d+ v8\)[[:space:]]+\(reg.*:V2HI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c new file mode 100644 index 00000000000..b12c6a6bc5f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_64bit_vector.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_64bit_vector.h" +// Function under test: +// int32x2_t test_64bit_vector(int32x2_t vec1, int32x2_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c new file mode 100644 index 00000000000..770bec6ac1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_all_mixed.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_all_mixed.h" +// Function under test: +// double test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c new file mode 100644 index 00000000000..dc5a6cd8cb9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_call_mixed_function.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_call_mixed_function.h" +// Function under test: +// int helper_mixed_function(int i, int32x4_t v, float f) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c new file mode 100644 index 00000000000..bed512b3e83 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vector_elements.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vector_elements.h" +// Function under test: +// int test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, +// int32x4_t int_vec, int64x2_t long_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16QI \d+ \[ byte_vec \]\)[[:space:]]+\(reg.*:V16QI \d+ v8 \[ byte_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+ \[ short_vec \]\)[[:space:]]+\(reg.*:V8HI \d+ v9 \[ short_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ int_vec \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DI \d+ \[ long_vec \]\)[[:space:]]+\(reg.*:V2DI \d+ v11 \[ long_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c new file mode 100644 index 00000000000..0b56802b46d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_vectors_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_vectors_struct.h" +// Function under test: +// struct_different_vectors_t test_different_vectors_struct(struct_different_vectors_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c new file mode 100644 index 00000000000..361bff79203 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_different_width_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_different_width_vectors_struct.h" +// Function under test: +// different_width_vectors_struct_t test_different_width_vectors_struct(different_width_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8HI \d+\)[[:space:]]+\(reg:V8HI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c new file mode 100644 index 00000000000..42d7c957ef2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_equivalent_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_equivalent_struct.h" +// Function under test: +// equivalent_struct_t test_equivalent_struct(equivalent_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c new file mode 100644 index 00000000000..a4897e5fcd4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_four_registers.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_four_registers.h" +// Function under test: +// int32x16_t test_four_registers(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c new file mode 100644 index 00000000000..90f15c6ecce --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_fp_vs_int_vectors.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_fp_vs_int_vectors.h" +// Function under test: +// float test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, +// double64x2_t double_vec) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ int_vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ int_vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ float_vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ float_vec \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2DF \d+ \[ double_vec \]\)[[:space:]]+\(reg.*:V2DF \d+ v10 \[ double_vec \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c new file mode 100644 index 00000000000..166bc8d560b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_large_vector_small_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_large_vector_small_abi_vlen.h" +// Function under test: +// int32x16_t test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V16SI \d+ v10 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c new file mode 100644 index 00000000000..5f95941d5b8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_args.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_args.h" +// Function under test: +// int test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c new file mode 100644 index 00000000000..7cef54c19e3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_float_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_float_vector.h" +// Function under test: +// float test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SF \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SF \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c new file mode 100644 index 00000000000..d383a3421e0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_int_vector.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_int_vector.h" +// Function under test: +// int test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c new file mode 100644 index 00000000000..44c80b9ffdd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct.h" +// Function under test: +// struct_mixed_t test_mixed_struct(struct_mixed_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c new file mode 100644 index 00000000000..c173c0aa907 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_struct_advanced.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_struct_advanced.h" +// Function under test: +// mixed_struct_advanced_t test_mixed_struct_advanced(mixed_struct_advanced_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c new file mode 100644 index 00000000000..bda5096a35d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_mixed_vector_types_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_mixed_vector_types_struct.h" +// Function under test: +// mixed_vector_types_struct_t test_mixed_vector_types_struct(mixed_vector_types_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SF \d+\)[[:space:]]+\(reg:V4SF \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c new file mode 100644 index 00000000000..58bac010b2f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_unions.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_unions.h" +// Function under test: +// union_vector_t test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c new file mode 100644 index 00000000000..8294c5487ee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_vectors.h" +// Function under test: +// int32x4_t test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c new file mode 100644 index 00000000000..2f0c620445a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_multiple_with_small_abi_vlen.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_multiple_with_small_abi_vlen.h" +// Function under test: +// int32x4_t test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, +// int32x4_t v3, int32x4_t v4) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c new file mode 100644 index 00000000000..9538ba0b0a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion.c @@ -0,0 +1,45 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion.h" +// Function under test: +// int32x4_t test_register_exhaustion(int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, +// int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, +// int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, +// int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, +// int32x4_t v17) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c new file mode 100644 index 00000000000..118627dd19d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_exhaustion_mixed.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_exhaustion_mixed.h" +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ v1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ v2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v3 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ v3 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v4 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ v4 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v5 \]\)[[:space:]]+\(reg.*:V4SI \d+ v12 \[ v5 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v6 \]\)[[:space:]]+\(reg.*:V4SI \d+ v13 \[ v6 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v7 \]\)[[:space:]]+\(reg.*:V4SI \d+ v14 \[ v7 \]\)\)} "expand" } } */ +// Check vector argument 8 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v8 \]\)[[:space:]]+\(reg.*:V4SI \d+ v15 \[ v8 \]\)\)} "expand" } } */ +// Check vector argument 9 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v9 \]\)[[:space:]]+\(reg.*:V4SI \d+ v16 \[ v9 \]\)\)} "expand" } } */ +// Check argument 10 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v10 \]\)[[:space:]]+\(reg.*:V4SI \d+ v17 \[ v10 \]\)\)} "expand" } } */ +// Check argument 11 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v11 \]\)[[:space:]]+\(reg.*:V4SI \d+ v18 \[ v11 \]\)\)} "expand" } } */ +// Check argument 12 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v12 \]\)[[:space:]]+\(reg.*:V4SI \d+ v19 \[ v12 \]\)\)} "expand" } } */ +// Check argument 13 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v13 \]\)[[:space:]]+\(reg.*:V4SI \d+ v20 \[ v13 \]\)\)} "expand" } } */ +// Check argument 14 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v14 \]\)[[:space:]]+\(reg.*:V4SI \d+ v21 \[ v14 \]\)\)} "expand" } } */ +// Check argument 15 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v15 \]\)[[:space:]]+\(reg.*:V4SI \d+ v22 \[ v15 \]\)\)} "expand" } } */ +// Check argument 16 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ v16 \]\)[[:space:]]+\(reg.*:V4SI \d+ v23 \[ v16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c new file mode 100644 index 00000000000..7b6737b7d15 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_register_pressure_scenarios.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_register_pressure_scenarios.h" +// Function under test: +// void test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, +// int32x4_t medium1, int32x4_t medium2, +// int32x8_t large1) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small1 \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ small1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ small2 \]\)[[:space:]]+\(reg.*:V2SI \d+ v9 \[ small2 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v10 \[ medium1 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ medium2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v11 \[ medium2 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ large1 \]\)[[:space:]]+\(reg.*:V8SI \d+ v12 \[ large1 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c new file mode 100644 index 00000000000..04e1befc49f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_same_vectors_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_same_vectors_struct.h" +// Function under test: +// struct_two_same_vectors_t test_same_vectors_struct(struct_two_same_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c new file mode 100644 index 00000000000..beaa25e3d39 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_simple_union.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_simple_union.h" +// Function under test: +// union_vector_t test_simple_union(union_vector_t u) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) 0\).*\(reg.*:DI \d+ a0 \[[^\]]+\]\)\)} "expand" } } */ +// Check argument 2 register assignment +/* { dg-final { scan-rtl-dump {\(set \(subreg:DI \(reg.*:TI \d+ \[[^\]]+\]\) [0-9]+\).*\(reg.*:DI \d+ a1 \[[^\]]+\]\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) 0\)\)} "expand" } } */ +// Check return value passed via integer registers using subreg +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a1 \[[^\]]*\]\).*\(subreg:DI \(reg.*:TI \d+ \[.*.*\]\) \d+\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c new file mode 100644 index 00000000000..d21028e5ab5 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_register.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_register.h" +// Function under test: +// int32x4_t test_single_register(int32x4_t vec1, int32x4_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec1 \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec1 \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V4SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c new file mode 100644 index 00000000000..bab73584f93 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_single_vector_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_single_vector_struct.h" +// Function under test: +// struct_single_vector_t test_single_vector_struct(struct_single_vector_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ s \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c new file mode 100644 index 00000000000..11dd3c63843 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_different_abi_vlen.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_different_abi_vlen.h" +// Function under test: +// two_medium_vectors_t test_struct_different_abi_vlen(two_medium_vectors_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c new file mode 100644 index 00000000000..b1199d4486b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_eight_128bit_vectors.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_eight_128bit_vectors.h" +// Function under test: +// eight_128bit_vectors_struct_t test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v10 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v11 \[ s\+48 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v12 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 6 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v13 \[ s\+80 \]\)\)} "expand" } } */ +// Check argument 7 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v14 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 8 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v15 \[ s\+112 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c new file mode 100644 index 00000000000..fe48ae0aa1d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_five_256bit_vectors.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_five_256bit_vectors.h" +// Function under test: +// five_256bit_vectors_struct_t test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ +// Check argument 5 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v12 \[ s\+128 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c new file mode 100644 index 00000000000..d4026bac446 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_four_256bit_vectors.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_four_256bit_vectors.h" +// Function under test: +// four_256bit_vectors_struct_t test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v9 \[ s\+32 \]\)\)} "expand" } } */ +// Check argument 3 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v10 \[ s\+64 \]\)\)} "expand" } } */ +// Check argument 4 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+\)[[:space:]]+\(reg:V8SI \d+ v11 \[ s\+96 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c new file mode 100644 index 00000000000..c6111b84dcc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_struct_nine_128bit_vectors.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_struct_nine_128bit_vectors.h" +// Function under test: +// nine_128bit_vectors_struct_t test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) +// Check argument 1 register assignment +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+.*\).*\(reg.*:DI \d+ a1\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ \[ \.result_ptr \]\).*\(reg.*:DI \d+ a0 \[ \.result_ptr \]\)\)} "expand" } } */ +// Check return value passed via pointer (result_ptr) +/* { dg-final { scan-rtl-dump {\(set \(reg.*:DI \d+ a0\).*\(reg.*:DI \d+ \[ \.result_ptr \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c new file mode 100644 index 00000000000..7c919f3c4a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_two_registers.c @@ -0,0 +1,15 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_two_registers.h" +// Function under test: +// int32x8_t test_two_registers(int32x8_t vec, int32x8_t vec2) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec2 \]\)[[:space:]]+\(reg.*:V8SI \d+ v9 \[ vec2 \]\)\)} "expand" } } */ +// Check return value passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c new file mode 100644 index 00000000000..c4c57f74e92 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/abi-vlen-256-xlen-64/test_vector_array_struct.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl256b -mabi=lp64d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +#define ABI_VLEN 256 + +#include "../common/test_vector_array_struct.h" +// Function under test: +// struct_vector_array_t test_vector_array_struct(struct_vector_array_t s) +// Check vector argument 1 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v8 \[ s \]\)\)} "expand" } } */ +// Check vector argument 2 passed in vector register +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+\)[[:space:]]+\(reg:V4SI \d+ v9 \[ s\+16 \]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h new file mode 100644 index 00000000000..0732cf564d4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_128bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 128-bit vectors behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_128bit_vector(int32x4_t vec1, int32x4_t vec2) { + // Two 128-bit vectors: + // - ABI_VLEN=128: each uses 1 vector register (2 total) + // - ABI_VLEN=64: each uses 2 vector registers (4 total) + // - ABI_VLEN=32: each uses 4 vector registers (8 total) + int32x4_t result; + result = vec1 + vec2; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h new file mode 100644 index 00000000000..18b99bfdb71 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_256bit_vector.h @@ -0,0 +1,14 @@ +// Test: Two 256-bit vectors behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +int32x8_t VLS_CC(ABI_VLEN) test_256bit_vector(int32x8_t vec1, int32x8_t vec2) { + // Two 256-bit vectors: + // - ABI_VLEN=256: each uses 1 vector register (2 total) + // - ABI_VLEN=128: each uses 2 vector registers (4 total) + // - ABI_VLEN=64: each uses 4 vector registers (8 total) + // - ABI_VLEN=32: each uses 8 vector registers (16 total) + int32x8_t result; + result = vec1 + vec2; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h new file mode 100644 index 00000000000..e18b8e424c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_32bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 32-bit vectors (very small vectors) + +#include "../vls-cc-common.h" + +int16x2_t VLS_CC(ABI_VLEN) test_32bit_vector(int16x2_t vec1, int16x2_t vec2) { + // Two 32-bit vectors: + // - Each always uses 1 vector register regardless of ABI_VLEN + // - Uses even smaller portion when ABI_VLEN > 32 + int16x2_t result; + result[0] = vec1[0] + vec2[0]; + result[1] = vec1[1] + vec2[1]; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h new file mode 100644 index 00000000000..dc3a2c1e793 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_64bit_vector.h @@ -0,0 +1,13 @@ +// Test: Two 64-bit vectors (always fit in one register each) + +#include "../vls-cc-common.h" + +int32x2_t VLS_CC(ABI_VLEN) test_64bit_vector(int32x2_t vec1, int32x2_t vec2) { + // Two 64-bit vectors: + // - Each always uses 1 vector register regardless of ABI_VLEN + // - Only uses portion of the register when ABI_VLEN > 64 + int32x2_t result; + result[0] = vec1[0] + vec2[0]; + result[1] = vec1[1] + vec2[1]; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h new file mode 100644 index 00000000000..6cc50b11c6f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_all_mixed.h @@ -0,0 +1,13 @@ +// Test: All three types mixed (int, float, vector) + +#include "../vls-cc-common.h" + +double VLS_CC(ABI_VLEN) test_all_mixed(int i, float f, int32x4_t vec1, double d, float32x4_t vec2, int j) { + // int i -> a0 (integer register) + // float f -> fa0 (FP register) + // int32x4_t vec1 -> v8 (vector register) + // double d -> fa1 (FP register) + // float32x4_t vec2 -> v9 (vector register) + // int j -> a1 (integer register) + return i + f + vec1[0] + d + vec2[0] + j; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h new file mode 100644 index 00000000000..e5cd837ac3d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_call_mixed_function.h @@ -0,0 +1,14 @@ +// Test: Function pointers with mixed signatures + +#include "../vls-cc-common.h" + +typedef int (*mixed_func_ptr_t)(int, int32x4_t, float) VLS_CC(ABI_VLEN); + +// Helper function to be called via function pointer +int VLS_CC(ABI_VLEN) helper_mixed_function(int i, int32x4_t v, float f) { + return i + v[0] + (int)f; +} + +int VLS_CC(ABI_VLEN) test_call_mixed_function(mixed_func_ptr_t func, int i, int32x4_t v, float f) { + return func(i, v, f); +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h new file mode 100644 index 00000000000..3ef700b921c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vector_elements.h @@ -0,0 +1,10 @@ +// Test: Vector types with different element types in same call + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_different_vector_elements(int8x16_t byte_vec, int16x8_t short_vec, + int32x4_t int_vec, int64x2_t long_vec) { + // All are 128-bit vectors but with different element types + // Should all use same vector register allocation rules + return byte_vec[0] + short_vec[0] + int_vec[0] + (int)long_vec[0]; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h new file mode 100644 index 00000000000..b7c1e48cfee --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_vectors_struct.h @@ -0,0 +1,9 @@ +// Test: Struct with different sized vectors - uses hardware FP calling convention + +#include "../vls-cc-common.h" + +struct_different_vectors_t VLS_CC(ABI_VLEN) test_different_vectors_struct(struct_different_vectors_t s) { + // Contains int32x2_t (64 bits) and int32x4_t (128 bits) - different lengths + // Should use hardware floating-point calling convention, not vector registers + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h new file mode 100644 index 00000000000..a0b8e151ba6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_different_width_vectors_struct.h @@ -0,0 +1,27 @@ +// Test: Struct with two vectors of different widths but same total size +// int32x4_t (128 bits, 4 x 32-bit) and int16x8_t (128 bits, 8 x 16-bit) - both should be flattened + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t wide_vec; // 128-bit vector with 4 x 32-bit elements + int16x8_t narrow_vec; // 128-bit vector with 8 x 16-bit elements +} different_width_vectors_struct_t; + +different_width_vectors_struct_t VLS_CC(ABI_VLEN) test_different_width_vectors_struct(different_width_vectors_struct_t s) { + // Should be flattened and passed as two separate vector arguments + // wide_vec should use first vector register, narrow_vec should use second vector register + different_width_vectors_struct_t result; + + // Process wide vector: add 100 to each 32-bit element + for (int i = 0; i < 4; i++) { + result.wide_vec[i] = s.wide_vec[i] + 100; + } + + // Process narrow vector: add 10 to each 16-bit element + for (int i = 0; i < 8; i++) { + result.narrow_vec[i] = s.narrow_vec[i] + 10; + } + + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h new file mode 100644 index 00000000000..859fc10609a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_equivalent_struct.h @@ -0,0 +1,14 @@ +// Test: Compare struct vs union behavior + +#include "../vls-cc-common.h" + +// Struct equivalent to union (should use vector calling convention) +typedef struct { + int32x4_t vec; +} equivalent_struct_t; + +equivalent_struct_t VLS_CC(ABI_VLEN) test_equivalent_struct(equivalent_struct_t s) { + // This struct should use vector calling convention (flattened) + // Compare behavior with the union version + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h new file mode 100644 index 00000000000..e53d417889f --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_four_registers.h @@ -0,0 +1,11 @@ +// Test: Two vectors passed in eight registers (<= 4 * ABI_VLEN bits each) +// int32x16_t (512 bits) should use 4 registers each when ABI_VLEN = 128 + +#include "../vls-cc-common.h" + +int32x16_t VLS_CC(ABI_VLEN) test_four_registers(int32x16_t vec1, int32x16_t vec2) { + // Add vectors element-wise + int32x16_t result; + result = vec1 + vec2; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h new file mode 100644 index 00000000000..649dc13b897 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_fp_vs_int_vectors.h @@ -0,0 +1,10 @@ +// Test: Floating-point vectors vs integer vectors + +#include "../vls-cc-common.h" + +float VLS_CC(ABI_VLEN) test_fp_vs_int_vectors(int32x4_t int_vec, float32x4_t float_vec, + double64x2_t double_vec) { + // All vectors should use vector registers, regardless of element type + // Element type shouldn't affect register allocation for fixed-length vectors + return int_vec[0] + float_vec[0] + (float)double_vec[0]; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h new file mode 100644 index 00000000000..90627cf4cb4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_large_vector_small_abi_vlen.h @@ -0,0 +1,13 @@ +// Test: Two large vectors that might be passed by reference with small ABI_VLEN + +#include "../vls-cc-common.h" + +int32x16_t VLS_CC(ABI_VLEN) test_large_vector_small_abi_vlen(int32x16_t vec1, int32x16_t vec2) { + // Two 512-bit vectors: + // - ABI_VLEN=128: each uses 4 registers (8 total, fits in available registers) + // - ABI_VLEN=64: each needs 8 registers (16 total, exceeds available, passed by reference) + // - ABI_VLEN=32: each needs 16 registers (32 total, far exceeds available, passed by reference) + int32x16_t result; + result = vec1 + vec2; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h new file mode 100644 index 00000000000..c6d91e3df77 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_args.h @@ -0,0 +1,8 @@ +// Test: Mixed scalar and vector arguments + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_mixed_args(int scalar1, int32x4_t vec1, float scalar2, int32x4_t vec2) { + // scalars use integer/float registers, vectors use vector registers + return scalar1 + (int)scalar2 + vec1[0] + vec2[0]; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h new file mode 100644 index 00000000000..03ca452bb65 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_float_vector.h @@ -0,0 +1,10 @@ +// Test: Mixed floating-point scalars and vectors + +#include "../vls-cc-common.h" + +float VLS_CC(ABI_VLEN) test_mixed_float_vector(float f1, float32x4_t vec, double d1, float32x4_t vec2) { + // Float scalars should use FP registers (fa0, fa1, ...) + // Vectors should use vector registers (v8, v9, ...) + // Different register classes should not interfere + return f1 + (float)d1 + vec[0] + vec2[0]; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h new file mode 100644 index 00000000000..f3795343b01 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_int_vector.h @@ -0,0 +1,10 @@ +// Test: Mixed integer scalars and vectors + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_mixed_int_vector(int a, int32x4_t vec, int b, int32x4_t vec2) { + // Scalars should use integer registers (a0, a1, a2, ...) + // Vectors should use vector registers (v8, v9, ...) + // Should not interfere with each other's register allocation + return a + b + vec[0] + vec2[0]; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h new file mode 100644 index 00000000000..fb289be97c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct.h @@ -0,0 +1,8 @@ +// Test: Struct with mixed vector and scalar - uses hardware FP calling convention + +#include "../vls-cc-common.h" + +struct_mixed_t VLS_CC(ABI_VLEN) test_mixed_struct(struct_mixed_t s) { + // Contains vector and scalar - should use hardware FP calling convention + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h new file mode 100644 index 00000000000..5660a16c126 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_struct_advanced.h @@ -0,0 +1,15 @@ +// Test: Vector and scalar struct members (advanced mixed struct) + +#include "../vls-cc-common.h" + +typedef struct { + int scalar; + int32x4_t vector; + float fp_scalar; +} mixed_struct_advanced_t; + +mixed_struct_advanced_t VLS_CC(ABI_VLEN) test_mixed_struct_advanced(mixed_struct_advanced_t s) { + // Should use hardware FP calling convention due to mixed types + // Vector part will be treated according to standard struct rules + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h new file mode 100644 index 00000000000..d916423f0f0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_mixed_vector_types_struct.h @@ -0,0 +1,23 @@ +// Test: Struct with two vectors of same width but different types +// int32x4_t (128 bits) and float32x4_t (128 bits) - both should be flattened + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t int_vec; // 128-bit integer vector + float32x4_t float_vec; // 128-bit float vector +} mixed_vector_types_struct_t; + +mixed_vector_types_struct_t VLS_CC(ABI_VLEN) test_mixed_vector_types_struct(mixed_vector_types_struct_t s) { + // Should be flattened and passed as two separate vector arguments + // int_vec should use first vector register, float_vec should use second vector register + mixed_vector_types_struct_t result; + + // Combine the vectors: add 10 to int elements, multiply float elements by 2.0 + for (int i = 0; i < 4; i++) { + result.int_vec[i] = s.int_vec[i] + 10; + result.float_vec[i] = s.float_vec[i] * 2.0f; + } + + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h new file mode 100644 index 00000000000..2205020b9b0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_unions.h @@ -0,0 +1,14 @@ +// Test: Multiple union arguments + +#include "../vls-cc-common.h" + +union_vector_t VLS_CC(ABI_VLEN) test_multiple_unions(union_vector_t u1, union_vector_t u2, union_vector_t u3) { + // All should use integer calling convention + // Should consume integer registers, not vector registers + union_vector_t result; + result.scalars[0] = u1.scalars[0] + u2.scalars[0] + u3.scalars[0]; + result.scalars[1] = u1.scalars[1] + u2.scalars[1] + u3.scalars[1]; + result.scalars[2] = u1.scalars[2] + u2.scalars[2] + u3.scalars[2]; + result.scalars[3] = u1.scalars[3] + u2.scalars[3] + u3.scalars[3]; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h new file mode 100644 index 00000000000..96c8009ea0a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_vectors.h @@ -0,0 +1,12 @@ +// Test: Multiple vector arguments consuming available registers + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_multiple_vectors(int32x4_t v1, int32x4_t v2, int32x4_t v3) { + // Each vector uses 1 register, total 3 registers + int32x4_t result = {v1[0] + v2[0] + v3[0], + v1[1] + v2[1] + v3[1], + v1[2] + v2[2] + v3[2], + v1[3] + v2[3] + v3[3]}; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h new file mode 100644 index 00000000000..39a957eb935 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_multiple_with_small_abi_vlen.h @@ -0,0 +1,12 @@ +// Test: Multiple vectors that may exceed register count with small ABI_VLEN + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_multiple_with_small_abi_vlen(int32x4_t v1, int32x4_t v2, + int32x4_t v3, int32x4_t v4) { + // With ABI_VLEN=32, each 128-bit vector needs 4 registers + // 4 vectors * 4 registers = 16 registers needed + // Will exceed available vector registers, some passed by reference + int32x4_t result = {v1[0] + v2[0], v1[1] + v3[1], v1[2] + v4[2], v1[3] + v2[3]}; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h new file mode 100644 index 00000000000..66621851f96 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion.h @@ -0,0 +1,15 @@ +// Test: Vector register exhaustion - should fall back to reference passing + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_register_exhaustion( + int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, + int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, + int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, + int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, + int32x4_t v17) { + // First 16 vectors (v1-v16) should use vector registers v8-v23 + // 17th vector (v17) should be passed by reference due to register exhaustion + int32x4_t result = {v1[0] + v17[0], v2[1] + v17[1], v3[2] + v17[2], v4[3] + v17[3]}; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h new file mode 100644 index 00000000000..3825584b8d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_exhaustion_mixed.h @@ -0,0 +1,21 @@ +// Test: Large number of mixed arguments to test register exhaustion + +#include "../vls-cc-common.h" + +int VLS_CC(ABI_VLEN) test_register_exhaustion_mixed( + // Integer arguments (use a0-a7) + int i1, int i2, int i3, int i4, int i5, int i6, int i7, int i8, int i9, + // FP arguments (use fa0-fa7) + float f1, float f2, float f3, float f4, float f5, float f6, float f7, float f8, float f9, + // Vector arguments (use v8-v23, 16 registers available) + int32x4_t v1, int32x4_t v2, int32x4_t v3, int32x4_t v4, + int32x4_t v5, int32x4_t v6, int32x4_t v7, int32x4_t v8, + int32x4_t v9, int32x4_t v10, int32x4_t v11, int32x4_t v12, + int32x4_t v13, int32x4_t v14, int32x4_t v15, int32x4_t v16, + int32x4_t v17 +) { + // i9, f9 should be passed via stack due to integer/FP register exhaustion + // v1-v16 should use vector registers v8-v23 + // v17 should be passed via stack/memory due to vector register exhaustion + return i1 + i9 + (int)f1 + (int)f9 + v1[0] + v17[0]; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h new file mode 100644 index 00000000000..e55c56b031c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_register_pressure_scenarios.h @@ -0,0 +1,15 @@ +// Test: Function demonstrating register pressure with different ABI_VLEN + +#include "../vls-cc-common.h" + +void VLS_CC(ABI_VLEN) test_register_pressure_scenarios(int32x2_t small1, int32x2_t small2, + int32x4_t medium1, int32x4_t medium2, + int32x8_t large1) { + // Different register consumption based on ABI_VLEN: + // ABI_VLEN=128: 2 * 1 + 2 * 1 + 1 * 2 = 6 registers + // ABI_VLEN=64: 2 * 1 + 2 * 2 + 1 * 4 = 10 registers (exceeds 8, some by reference) + // ABI_VLEN=32: 2 * 2 + 2 * 4 + 1 * 8 = 20 registers (many by reference) + + // Just use the parameters to avoid warnings + (void)small1; (void)small2; (void)medium1; (void)medium2; (void)large1; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h new file mode 100644 index 00000000000..d5cd78d7bd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_same_vectors_struct.h @@ -0,0 +1,10 @@ +// Test: Struct with two same-length vectors - should be passed as vector tuple + +#include "../vls-cc-common.h" + +struct_two_same_vectors_t VLS_CC(ABI_VLEN) test_same_vectors_struct(struct_two_same_vectors_t s) { + // Should be passed in vector registers like a vector tuple + // Both vectors are int32x4_t (128 bits each), total 256 bits + // Should use 2 vector registers when ABI_VLEN = 128 + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h new file mode 100644 index 00000000000..09c57c27796 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_simple_union.h @@ -0,0 +1,9 @@ +// Test: Simple union with vector - should use integer calling convention + +#include "../vls-cc-common.h" + +union_vector_t VLS_CC(ABI_VLEN) test_simple_union(union_vector_t u) { + // Union with fixed-length vector should always use integer calling convention + // Should NOT use vector registers, even though it contains a vector + return u; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h new file mode 100644 index 00000000000..b65a1e9695c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_register.h @@ -0,0 +1,11 @@ +// Test: Two vectors passed in registers (<= ABI_VLEN bits each) +// int32x4_t (128 bits) should use 1 register per vector when ABI_VLEN >= 128 + +#include "../vls-cc-common.h" + +int32x4_t VLS_CC(ABI_VLEN) test_single_register(int32x4_t vec1, int32x4_t vec2) { + // Add vectors element-wise + int32x4_t result; + result = vec1 + vec2; + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h new file mode 100644 index 00000000000..7d1d2a481c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_single_vector_struct.h @@ -0,0 +1,8 @@ +// Test: Struct with single vector - should be flattened + +#include "../vls-cc-common.h" + +struct_single_vector_t VLS_CC(ABI_VLEN) test_single_vector_struct(struct_single_vector_t s) { + // Should be flattened and passed as single vector argument + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h new file mode 100644 index 00000000000..b0b388e7c98 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_different_abi_vlen.h @@ -0,0 +1,17 @@ +// Test: Struct behavior under different ABI_VLEN + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; + int32x4_t vec2; +} two_medium_vectors_t; + +two_medium_vectors_t VLS_CC(ABI_VLEN) test_struct_different_abi_vlen(two_medium_vectors_t s) { + // Struct with 2 * 128-bit vectors (256 bits total): + // - ABI_VLEN=256: fits in single "vector tuple" concept, uses 2 registers + // - ABI_VLEN=128: each vector uses 1 register, total 2 registers + // - ABI_VLEN=64: each vector uses 2 registers, total 4 registers + // - ABI_VLEN=32: each vector uses 4 registers, total 8 registers + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h new file mode 100644 index 00000000000..78b9d507057 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_eight_128bit_vectors.h @@ -0,0 +1,38 @@ +// Test: Struct with eight 128-bit vectors +// Each int32x4_t is 128 bits (4 x 32-bit elements) +// Total: 8 vectors * 128 bits = 1024 bits +// With ABI_VLEN=128: 8 vectors * 1 register each = 8 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; // 128-bit vector + int32x4_t vec2; // 128-bit vector + int32x4_t vec3; // 128-bit vector + int32x4_t vec4; // 128-bit vector + int32x4_t vec5; // 128-bit vector + int32x4_t vec6; // 128-bit vector + int32x4_t vec7; // 128-bit vector + int32x4_t vec8; // 128-bit vector +} eight_128bit_vectors_struct_t; + +eight_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_eight_128bit_vectors(eight_128bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec8 uses v15 + // Total uses 8 out of 16 available vector argument registers + eight_128bit_vectors_struct_t result; + + // Process each 128-bit vector: multiply by (index + 1) + for (int i = 0; i < 4; i++) { + result.vec1[i] = s.vec1[i] * 1; + result.vec2[i] = s.vec2[i] * 2; + result.vec3[i] = s.vec3[i] * 3; + result.vec4[i] = s.vec4[i] * 4; + result.vec5[i] = s.vec5[i] * 5; + result.vec6[i] = s.vec6[i] * 6; + result.vec7[i] = s.vec7[i] * 7; + result.vec8[i] = s.vec8[i] * 8; + } + + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h new file mode 100644 index 00000000000..190cafd5b5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_five_256bit_vectors.h @@ -0,0 +1,33 @@ +// Test: Struct with five 256-bit vectors +// Each int32x8_t is 256 bits (8 x 32-bit elements) +// Total: 5 vectors * 256 bits = 1280 bits +// With ABI_VLEN=128: 5 vectors * 2 registers each = 10 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x8_t vec1; // 256-bit vector + int32x8_t vec2; // 256-bit vector + int32x8_t vec3; // 256-bit vector + int32x8_t vec4; // 256-bit vector + int32x8_t vec5; // 256-bit vector +} five_256bit_vectors_struct_t; + +five_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_five_256bit_vectors(five_256bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, + // vec4 uses v14+v15, vec5 uses v16+v17 + // Total uses 10 out of 16 available vector argument registers + five_256bit_vectors_struct_t result; + + // Process each 256-bit vector: add different values to each vector + for (int i = 0; i < 8; i++) { + result.vec1[i] = s.vec1[i] + 1000; + result.vec2[i] = s.vec2[i] + 2000; + result.vec3[i] = s.vec3[i] + 3000; + result.vec4[i] = s.vec4[i] + 4000; + result.vec5[i] = s.vec5[i] + 5000; + } + + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h new file mode 100644 index 00000000000..02e9cfe6d1a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_four_256bit_vectors.h @@ -0,0 +1,30 @@ +// Test: Struct with four 256-bit vectors +// Each int32x8_t is 256 bits (8 x 32-bit elements) +// Total: 4 vectors * 256 bits = 1024 bits +// With ABI_VLEN=128: 4 vectors * 2 registers each = 8 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x8_t vec1; // 256-bit vector + int32x8_t vec2; // 256-bit vector + int32x8_t vec3; // 256-bit vector + int32x8_t vec4; // 256-bit vector +} four_256bit_vectors_struct_t; + +four_256bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_four_256bit_vectors(four_256bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8+v9, vec2 uses v10+v11, vec3 uses v12+v13, vec4 uses v14+v15 + // With ABI_VLEN=256: vec1 uses v8, vec2 uses v9, vec3 uses v10, vec4 uses v11 + four_256bit_vectors_struct_t result; + + // Process each 256-bit vector: add 100 to first element, add 200 to second element, etc. + for (int i = 0; i < 8; i++) { + result.vec1[i] = s.vec1[i] + 100; + result.vec2[i] = s.vec2[i] + 200; + result.vec3[i] = s.vec3[i] + 300; + result.vec4[i] = s.vec4[i] + 400; + } + + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h new file mode 100644 index 00000000000..fe77bc8e9b9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_struct_nine_128bit_vectors.h @@ -0,0 +1,40 @@ +// Test: Struct with nine 128-bit vectors +// Each int32x4_t is 128 bits (4 x 32-bit elements) +// Total: 9 vectors * 128 bits = 1152 bits +// With ABI_VLEN=128: 9 vectors * 1 register each = 9 registers (fits in 16 available) + +#include "../vls-cc-common.h" + +typedef struct { + int32x4_t vec1; // 128-bit vector + int32x4_t vec2; // 128-bit vector + int32x4_t vec3; // 128-bit vector + int32x4_t vec4; // 128-bit vector + int32x4_t vec5; // 128-bit vector + int32x4_t vec6; // 128-bit vector + int32x4_t vec7; // 128-bit vector + int32x4_t vec8; // 128-bit vector + int32x4_t vec9; // 128-bit vector +} nine_128bit_vectors_struct_t; + +nine_128bit_vectors_struct_t VLS_CC(ABI_VLEN) test_struct_nine_128bit_vectors(nine_128bit_vectors_struct_t s) { + // Should be flattened and passed as separate vector arguments + // With ABI_VLEN=128: vec1 uses v8, vec2 uses v9, ..., vec9 uses v16 + // Total uses 9 out of 16 available vector argument registers + nine_128bit_vectors_struct_t result; + + // Process each 128-bit vector: add vector index * 100 to each element + for (int i = 0; i < 4; i++) { + result.vec1[i] = s.vec1[i] + 100; + result.vec2[i] = s.vec2[i] + 200; + result.vec3[i] = s.vec3[i] + 300; + result.vec4[i] = s.vec4[i] + 400; + result.vec5[i] = s.vec5[i] + 500; + result.vec6[i] = s.vec6[i] + 600; + result.vec7[i] = s.vec7[i] + 700; + result.vec8[i] = s.vec8[i] + 800; + result.vec9[i] = s.vec9[i] + 900; + } + + return result; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h new file mode 100644 index 00000000000..b9fe52354c6 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_two_registers.h @@ -0,0 +1,8 @@ +// Test: Vector passed in two registers (<= 2 * ABI_VLEN bits) +// int32x8_t (256 bits) should use 2 registers when ABI_VLEN = 128 + +#include "../vls-cc-common.h" + +int32x8_t VLS_CC(ABI_VLEN) test_two_registers(int32x8_t vec, int32x8_t vec2) { + return vec + vec2; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h new file mode 100644 index 00000000000..77a84d8d606 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/common/test_vector_array_struct.h @@ -0,0 +1,9 @@ +// Test: Struct with vector array - should be passed as vector tuple + +#include "../vls-cc-common.h" + +struct_vector_array_t VLS_CC(ABI_VLEN) test_vector_array_struct(struct_vector_array_t s) { + // Array of 2 int32x4_t vectors, should be passed as vector tuple + // Total size: 256 bits, should use 2 vector registers + return s; +} \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp new file mode 100644 index 00000000000..68b40674ab1 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/riscv-vls-cc.exp @@ -0,0 +1,63 @@ +# Copyright (C) 2025 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a RISC-V target. +if ![istarget riscv*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " -ansi -pedantic-errors" +} + +# Initialize `dg'. +dg-init + +# Main loop. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# Test for specific XLEN and VLEN. +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-32-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-64-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-128-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-256-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-32/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +gcc-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/abi-vlen-512-xlen-64/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS + +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c new file mode 100644 index 00000000000..69a47ad6f57 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Large vector with ABI_VLEN=128 + +#include "vls-cc-common.h" + +int32x8_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_large_vector(int32x8_t vec) { + // 256-bit vector with ABI_VLEN=128 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c new file mode 100644 index 00000000000..3c179d67bf0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_128_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=128 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(128))) test_128_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=128 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c new file mode 100644 index 00000000000..ba0630d6082 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Large vector with ABI_VLEN=256 + +#include "vls-cc-common.h" + +int32x8_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_large_vector(int32x8_t vec) { + // 256-bit vector with ABI_VLEN=256 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V8SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V8SI \d+ v8\)[[:space:]]+\(reg.*:V8SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c new file mode 100644 index 00000000000..503f9ce2dd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_256_abi_vlen_very_large_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Very large vector with ABI_VLEN=256 + +#include "vls-cc-common.h" + +int32x16_t __attribute__((riscv_vls_cc(256))) test_256_abi_vlen_very_large_vector(int32x16_t vec) { + // 512-bit vector with ABI_VLEN=256 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V16SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V16SI \d+ v8\)[[:space:]]+\(reg.*:V16SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c new file mode 100644 index 00000000000..496b77c2a10 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=32 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=32 -> uses 4 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c new file mode 100644 index 00000000000..1b44a091e45 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_32_abi_vlen_small_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Small vector with ABI_VLEN=32 + +#include "vls-cc-common.h" + +int32x2_t __attribute__((riscv_vls_cc(32))) test_32_abi_vlen_small_vector(int32x2_t vec) { + // 64-bit vector with ABI_VLEN=32 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c new file mode 100644 index 00000000000..c1f367342d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_medium_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Medium vector with ABI_VLEN=64 + +#include "vls-cc-common.h" + +int32x4_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_medium_vector(int32x4_t vec) { + // 128-bit vector with ABI_VLEN=64 -> uses 2 registers + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V4SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V4SI \d+ v8\)[[:space:]]+\(reg.*:V4SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c new file mode 100644 index 00000000000..241e897ee09 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/test_64_abi_vlen_small_vector.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gcv_zvl512b -mabi=ilp32d -fdump-rtl-expand" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" } } */ + +// Test: Small vector with ABI_VLEN=64 + +#include "vls-cc-common.h" + +int32x2_t __attribute__((riscv_vls_cc(64))) test_64_abi_vlen_small_vector(int32x2_t vec) { + // 64-bit vector with ABI_VLEN=64 -> uses 1 register + return vec; +} +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ \[ vec \]\)[[:space:]]+\(reg.*:V2SI \d+ v8 \[ vec \]\)\)} "expand" } } */ +/* { dg-final { scan-rtl-dump {\(set \(reg.*:V2SI \d+ v8\)[[:space:]]+\(reg.*:V2SI \d+ \[ .*\]\)\)} "expand" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h new file mode 100644 index 00000000000..105f5a7e4a2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/vls-cc/vls-cc-common.h @@ -0,0 +1,125 @@ +#ifndef VLS_CC_COMMON_H +#define VLS_CC_COMMON_H + +#include + +// Check if ABI_VLEN is defined +#ifndef ABI_VLEN +#define ABI_VLEN 128 // Default fallback value +#endif + +// VLS Calling Convention attribute macro +#define VLS_CC(ABI_VLEN) \ + __attribute__((riscv_vls_cc(ABI_VLEN))) + +// Fixed-length vector type definitions following x_t naming convention +// These use GCC/Clang __attribute__((vector_size(N))) extension + +// 8-bit integer vectors +typedef int8_t int8x2_t __attribute__((vector_size(2))); +typedef int8_t int8x4_t __attribute__((vector_size(4))); +typedef int8_t int8x8_t __attribute__((vector_size(8))); +typedef int8_t int8x16_t __attribute__((vector_size(16))); +typedef int8_t int8x32_t __attribute__((vector_size(32))); +typedef int8_t int8x64_t __attribute__((vector_size(64))); + +typedef uint8_t uint8x2_t __attribute__((vector_size(2))); +typedef uint8_t uint8x4_t __attribute__((vector_size(4))); +typedef uint8_t uint8x8_t __attribute__((vector_size(8))); +typedef uint8_t uint8x16_t __attribute__((vector_size(16))); +typedef uint8_t uint8x32_t __attribute__((vector_size(32))); +typedef uint8_t uint8x64_t __attribute__((vector_size(64))); + +// 16-bit integer vectors +typedef int16_t int16x2_t __attribute__((vector_size(4))); +typedef int16_t int16x4_t __attribute__((vector_size(8))); +typedef int16_t int16x8_t __attribute__((vector_size(16))); +typedef int16_t int16x16_t __attribute__((vector_size(32))); +typedef int16_t int16x32_t __attribute__((vector_size(64))); + +typedef uint16_t uint16x2_t __attribute__((vector_size(4))); +typedef uint16_t uint16x4_t __attribute__((vector_size(8))); +typedef uint16_t uint16x8_t __attribute__((vector_size(16))); +typedef uint16_t uint16x16_t __attribute__((vector_size(32))); +typedef uint16_t uint16x32_t __attribute__((vector_size(64))); + +// 32-bit integer vectors +typedef int32_t int32x2_t __attribute__((vector_size(8))); +typedef int32_t int32x4_t __attribute__((vector_size(16))); +typedef int32_t int32x8_t __attribute__((vector_size(32))); +typedef int32_t int32x16_t __attribute__((vector_size(64))); + +typedef uint32_t uint32x2_t __attribute__((vector_size(8))); +typedef uint32_t uint32x4_t __attribute__((vector_size(16))); +typedef uint32_t uint32x8_t __attribute__((vector_size(32))); +typedef uint32_t uint32x16_t __attribute__((vector_size(64))); + +// 64-bit integer vectors +typedef int64_t int64x2_t __attribute__((vector_size(16))); +typedef int64_t int64x4_t __attribute__((vector_size(32))); +typedef int64_t int64x8_t __attribute__((vector_size(64))); + +typedef uint64_t uint64x2_t __attribute__((vector_size(16))); +typedef uint64_t uint64x4_t __attribute__((vector_size(32))); +typedef uint64_t uint64x8_t __attribute__((vector_size(64))); + +// Floating-point vectors (following the same pattern) +typedef float float32x2_t __attribute__((vector_size(8))); +typedef float float32x4_t __attribute__((vector_size(16))); +typedef float float32x8_t __attribute__((vector_size(32))); +typedef float float32x16_t __attribute__((vector_size(64))); + +typedef double double64x2_t __attribute__((vector_size(16))); +typedef double double64x4_t __attribute__((vector_size(32))); +typedef double double64x8_t __attribute__((vector_size(64))); + +// Test structures containing fixed-length vectors +typedef struct { + int32x4_t vec1; + int32x4_t vec2; +} struct_two_same_vectors_t; + +typedef struct { + int32x4_t vec; +} struct_single_vector_t; + +typedef struct { + int32x4_t vec_array[2]; +} struct_vector_array_t; + +typedef struct { + int32x2_t vec1; + int32x4_t vec2; // Different sizes +} struct_different_vectors_t; + +typedef struct { + int32x4_t vec; + int scalar; +} struct_mixed_t; + +// Union containing fixed-length vectors (always uses integer calling convention) +typedef union { + int32x4_t vec; + int32_t scalars[4]; +} union_vector_t; + +// Function pointer types for testing +typedef int32x4_t (*func_return_vector_t)(int32x4_t); +typedef void (*func_pass_vector_t)(int32x4_t); +typedef struct_single_vector_t (*func_return_struct_t)(struct_single_vector_t); + +// Test constants for initialization +#define INIT_INT32X4(a, b, c, d) (int32x4_t){a, b, c, d} +#define INIT_FLOAT32X4(a, b, c, d) (float32x4_t){a, b, c, d} +#define INIT_INT16X8(a, b, c, d, e, f, g, h) (int16x8_t){a, b, c, d, e, f, g, h} + +#ifdef SUPPORT_NON_POWER_OF_2_VEC +#define INIT_INT32X3(a, b, c) (int32x3_t){a, b, c} +#define INIT_FLOAT32X3(a, b, c) (float32x3_t){a, b, c} +#endif + +// Utility macros for vector operations testing +#define VEC_SIZE_BYTES(type) sizeof(type) +#define VEC_ELEMENT_COUNT(type, element_type) (sizeof(type) / sizeof(element_type)) + +#endif // VLS_CC_COMMON_H