From: Petar Jovanovic Date: Wed, 10 Aug 2016 14:33:21 +0000 (+0000) Subject: mips32: extend the current fp-mode code to support fpxx features X-Git-Tag: svn/VALGRIND_3_12_0^2~23 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=33d3fa20a3ec705ad91b4bd7b755a6bad4b57375;p=thirdparty%2Fvalgrind.git mips32: extend the current fp-mode code to support fpxx features Part of the changes to support FPXX mode for MIPS32. Patch by Aleksandar Rikalo Related issue BZ #366079. git-svn-id: svn://svn.valgrind.org/vex/trunk@3243 --- diff --git a/VEX/priv/guest_mips_helpers.c b/VEX/priv/guest_mips_helpers.c index e5f3d5539d..fd42513675 100644 --- a/VEX/priv/guest_mips_helpers.c +++ b/VEX/priv/guest_mips_helpers.c @@ -165,6 +165,8 @@ void LibVEX_GuestMIPS32_initialise( /*OUT*/ VexGuestMIPS32State * vex_state) vex_state->guest_COND = 0; + vex_state->guest_CP0_status = 0; + /* MIPS32 DSP ASE(r2) specific registers */ vex_state->guest_DSPControl = 0; /* DSPControl register */ vex_state->guest_ac0 = 0; /* Accumulator 0 */ @@ -272,6 +274,8 @@ void LibVEX_GuestMIPS64_initialise ( /*OUT*/ VexGuestMIPS64State * vex_state ) vex_state->guest_NRADDR = 0; vex_state->guest_COND = 0; + + vex_state->guest_CP0_status = MIPS_CP0_STATUS_FR; } /*-----------------------------------------------------------*/ diff --git a/VEX/priv/guest_mips_toIR.c b/VEX/priv/guest_mips_toIR.c index 24f371e114..c3228315f1 100644 --- a/VEX/priv/guest_mips_toIR.c +++ b/VEX/priv/guest_mips_toIR.c @@ -17300,10 +17300,7 @@ DisResult disInstr_MIPS( IRSB* irsb_IN, vassert(guest_arch == VexArchMIPS32 || guest_arch == VexArchMIPS64); mode64 = guest_arch != VexArchMIPS32; -#if (__mips_fpr==64) - fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(archinfo->hwcaps) - || guest_arch == VexArchMIPS64); -#endif + fp_mode64 = abiinfo->guest_mips_fp_mode64; guest_code = guest_code_IN; irsb = irsb_IN; diff --git a/VEX/priv/host_mips_isel.c b/VEX/priv/host_mips_isel.c index 1cccaa87a4..848234a39f 100644 --- a/VEX/priv/host_mips_isel.c +++ b/VEX/priv/host_mips_isel.c @@ -4183,10 +4183,7 @@ HInstrArray *iselSB_MIPS ( const IRSB* bb, || archinfo_host->endness == VexEndnessBE); mode64 = arch_host != VexArchMIPS32; -#if (__mips_fpr==64) - fp_mode64 = (VEX_MIPS_HAS_32_64BIT_FPRS(hwcaps_host) - || arch_host == VexArchMIPS64); -#endif + fp_mode64 = VEX_MIPS_HOST_FP_MODE(hwcaps_host); /* Make up an initial environment to use. */ env = LibVEX_Alloc_inline(sizeof(ISelEnv)); diff --git a/VEX/pub/libvex.h b/VEX/pub/libvex.h index ee9bbacae6..855bc64f77 100644 --- a/VEX/pub/libvex.h +++ b/VEX/pub/libvex.h @@ -227,8 +227,7 @@ typedef /* * Instead of Company Options values, bits 31:24 will be packed with - * additional information, such as isa level and presence of FPU unit - * with 32 64-bit registers. + * additional information, such as isa level and FP mode. */ #define VEX_MIPS_CPU_ISA_M32R1 0x01000000 #define VEX_MIPS_CPU_ISA_M32R2 0x02000000 @@ -236,8 +235,8 @@ typedef #define VEX_MIPS_CPU_ISA_M64R2 0x08000000 #define VEX_MIPS_CPU_ISA_M32R6 0x10000000 #define VEX_MIPS_CPU_ISA_M64R6 0x20000000 -/* CPU has FPU and 32 dbl. prec. FP registers */ -#define VEX_MIPS_CPU_32FPR 0x40000000 +/* FP mode is FR = 1 (32 dbl. prec. FP registers) */ +#define VEX_MIPS_HOST_FR 0x40000000 /* Get MIPS Extended Information */ #define VEX_MIPS_EX_INFO(x) ((x) & 0xFF000000) /* Get MIPS Company ID from HWCAPS */ @@ -246,10 +245,10 @@ typedef #define VEX_MIPS_PROC_ID(x) ((x) & 0x0000FF00) /* Get MIPS Revision from HWCAPS */ #define VEX_MIPS_REV(x) ((x) & 0x000000FF) -/* Check if the processor has 32 64-bit FP registers */ -#define VEX_MIPS_HAS_32_64BIT_FPRS(x) (VEX_MIPS_EX_INFO(x) | VEX_MIPS_CPU_32FPR) +/* Get host FP mode */ +#define VEX_MIPS_HOST_FP_MODE(x) (!!(VEX_MIPS_EX_INFO(x) & VEX_MIPS_HOST_FR)) /* Check if the processor supports MIPS32R2. */ -#define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) | \ +#define VEX_MIPS_CPU_HAS_MIPS32R2(x) (VEX_MIPS_EX_INFO(x) & \ VEX_MIPS_CPU_ISA_M32R2) /* Check if the processor supports DSP ASE Rev 2. */ #define VEX_MIPS_PROC_DSP2(x) ((VEX_MIPS_COMP_ID(x) == VEX_PRID_COMP_MIPS) && \ @@ -406,6 +405,8 @@ typedef function descriptor on the host, or to the function code itself? True => descriptor, False => code. */ Bool host_ppc_calls_use_fndescrs; + + Bool guest_mips_fp_mode64; } VexAbiInfo; diff --git a/VEX/pub/libvex_guest_mips32.h b/VEX/pub/libvex_guest_mips32.h index fd702a3116..8351f0e91c 100644 --- a/VEX/pub/libvex_guest_mips32.h +++ b/VEX/pub/libvex_guest_mips32.h @@ -147,7 +147,9 @@ typedef /* 472 */ ULong guest_ac2; /* 480 */ ULong guest_ac3; - UInt padding; + /* 488 */ UInt guest_CP0_status; + + /* 492 */ UInt padding; } VexGuestMIPS32State; /*---------------------------------------------------------------*/ /*--- Utility functions for MIPS32 guest stuff. ---*/ @@ -160,6 +162,8 @@ typedef extern void LibVEX_GuestMIPS32_initialise ( /*OUT*/VexGuestMIPS32State* vex_state ); +/* FR bit of CP0_STATUS_FR register */ +#define MIPS_CP0_STATUS_FR (1ul << 26) #endif /* ndef __LIBVEX_PUB_GUEST_MIPS32_H */ diff --git a/VEX/pub/libvex_guest_mips64.h b/VEX/pub/libvex_guest_mips64.h index fe28aca655..88d1f7fc9e 100644 --- a/VEX/pub/libvex_guest_mips64.h +++ b/VEX/pub/libvex_guest_mips64.h @@ -123,6 +123,8 @@ typedef /* 548 */ UInt guest_FENR; /* 552 */ UInt guest_FCSR; + /* 556 */ UInt guest_CP0_status; + /* TLS pointer for the thread. It's read-only in user space. On Linux it is set in user space by various thread-related syscalls. User Local Register. @@ -159,6 +161,9 @@ typedef extern void LibVEX_GuestMIPS64_initialise ( /*OUT*/VexGuestMIPS64State* vex_state ); +/* FR bit of CP0_STATUS_FR register */ +#define MIPS_CP0_STATUS_FR (1ul << 26) + #endif /* ndef __LIBVEX_PUB_GUEST_MIPS64_H */ /*---------------------------------------------------------------*/