From: Dmitry Baryshkov Date: Tue, 15 Apr 2025 10:25:59 +0000 (+0300) Subject: arm64: dts: qcom: sc7280: Use the header with DSI phy clock IDs X-Git-Tag: v6.16-rc1~97^2~20^2~85 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=33e020b942cb4bcf2f3870b573470973e6464bd5;p=thirdparty%2Fkernel%2Fstable.git arm64: dts: qcom: sc7280: Use the header with DSI phy clock IDs Use the header with DSI phy clock IDs to make code more readable. Signed-off-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20250415-drm-msm-dts-fixes-v1-1-90cd91bdd138@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index ec96c917b56b4..d780b5a18cf64 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -6,6 +6,7 @@ */ #include #include +#include #include #include #include @@ -4617,8 +4618,8 @@ reg = <0 0x0af00000 0 0x20000>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_DISP_GPLL0_CLK_SRC>, - <&mdss_dsi_phy 0>, - <&mdss_dsi_phy 1>, + <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&mdss_edp_phy 0>, @@ -4775,8 +4776,10 @@ "iface", "bus"; - assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; - assigned-clock-parents = <&mdss_dsi_phy 0>, <&mdss_dsi_phy 1>; + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; operating-points-v2 = <&dsi_opp_table>; power-domains = <&rpmhpd SC7280_CX>;