From: Jeff Law <jlaw@ventanamicro.com>
Date: Thu, 6 Feb 2025 19:37:11 +0000 (-0700)
Subject: [RISC-V] Fix risc-v expected test output after recent iv changes
X-Git-Tag: basepoints/gcc-16~2156
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=33e610110c933b0d65aa82d67864bb881768609f;p=thirdparty%2Fgcc.git

[RISC-V] Fix risc-v expected test output after recent iv changes

Richard S's recent change to iv increment insertion removed a reg->reg move
(which was its intent AFAICT).  This triggered a failure on a riscv test.

That test was meant to verify that we didn't have an extraneous reg->reg move
due to a buglet in the risc-v splitters.  Before the 2023 change we had two
vector reg->reg moves and after the 2023 fix we had just one.  With Richard's
change we have none ;-)  Adjusting test accordingly.

Pushed to the trunk.

gcc/testsuite
	* gcc.target/riscv/rvv/autovec/madd-split2-1.c: Update expected
	output.
---

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
index 4f99a5f87c4..8cc0c9f407c 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/madd-split2-1.c
@@ -10,4 +10,4 @@ foo (long *__restrict a, long *__restrict b, long n)
   return a[1];
 }
 
-/* { dg-final { scan-assembler-times {\tvmv1r\.v} 1 } } */
+/* { dg-final { scan-assembler-not {\tvmv1r\.v} } } */