From: Marek Vasut Date: Tue, 14 Oct 2025 10:46:03 +0000 (+0200) Subject: dt-bindings: clk: rs9: Fix DIF pattern match X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=341d72ebc2303670936713f5004a2825edc4e7ea;p=thirdparty%2Flinux.git dt-bindings: clk: rs9: Fix DIF pattern match The pattern match [0-19] is incorrect and does not cover range of 0..19, use pattern 1?[0-9] to cover range 0..19 instead. Update the example to validate all parts of the pattern match and prevent such failures in the future. Fixes: 26c1bc67aa2f ("dt-bindings: clk: rs9: Add Renesas 9-series I2C PCIe clock generator") Signed-off-by: Marek Vasut Reviewed-by: Conor Dooley Signed-off-by: Stephen Boyd --- diff --git a/Documentation/devicetree/bindings/clock/renesas,9series.yaml b/Documentation/devicetree/bindings/clock/renesas,9series.yaml index af6319697b1c0..a85f78ce29702 100644 --- a/Documentation/devicetree/bindings/clock/renesas,9series.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,9series.yaml @@ -62,7 +62,7 @@ properties: description: Output clock down spread in pcm (1/1000 of percent) patternProperties: - "^DIF[0-19]$": + "^DIF1?[0-9]$": type: object description: Description of one of the outputs (DIF0..DIF19). @@ -107,6 +107,15 @@ examples: DIF0 { renesas,slew-rate = <3000000>; }; + + /* Not present on 9FGV0241, used for DT validation only */ + DIF2 { + renesas,slew-rate = <2000000>; + }; + + DIF19 { + renesas,slew-rate = <3000000>; + }; }; };