From: Oliver Kurth <okurth@vmware.com>
Date: Tue, 24 Apr 2018 00:08:15 +0000 (-0700)
Subject: Common header file change not applicable to open-vm-tools.
X-Git-Tag: stable-10.3.0~59
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=357e8418e5441c2c5fc75a19f7b6529d6bce7452;p=thirdparty%2Fopen-vm-tools.git

Common header file change not applicable to open-vm-tools.
---

diff --git a/open-vm-tools/lib/include/vm_basic_asm_x86_common.h b/open-vm-tools/lib/include/vm_basic_asm_x86_common.h
index 0d9a34d9d..54270d9e1 100644
--- a/open-vm-tools/lib/include/vm_basic_asm_x86_common.h
+++ b/open-vm-tools/lib/include/vm_basic_asm_x86_common.h
@@ -388,8 +388,8 @@ RDTSC_BARRIER(void)
  * Thanks for pasting this whole comment into every architecture header.
  *
  * On x86, we only need to care specifically about store-load reordering on
- * normal memory types. In other cases, only a compiler barrier is needed. The
- * ST_LD barrier is implemented with a locked xor operation (instead of the
+ * normal memory types. In other cases, only a compiler barrier is needed.
+ * SMP_W_BARRIER_R is implemented with a locked xor operation (instead of the
  * mfence instruction) for performance reasons. See PR 1674199 for more
  * details.
  *
@@ -403,19 +403,17 @@ SMP_W_BARRIER_R(void)
 {
    volatile long temp;
 
-   COMPILER_MEM_BARRIER();
 #if defined __GNUC__
    __asm__ __volatile__ (
-      "lock xorl $1, %0\n"
+      "lock xorl $1, %0"
       : "+m" (temp)
       : /* no additional inputs */
-      : "cc");
+      : "cc", "memory");
 #elif defined _MSC_VER
    _InterlockedXor(&temp, 1);
 #else
 #error SMP_W_BARRIER_R not defined for this compiler
 #endif
-   COMPILER_MEM_BARRIER();
 }
 
 #define SMP_R_BARRIER_R()     COMPILER_READ_BARRIER()