From: Mathias Kresin Date: Wed, 22 Aug 2018 05:30:36 +0000 (+0200) Subject: ramips: fix mt7620 pinmux for second SPI X-Git-Tag: v19.07.0-rc1~2700 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3601c3de23f15e2735adc4becdca14c803b6b1a5;p=thirdparty%2Fopenwrt.git ramips: fix mt7620 pinmux for second SPI The mt7620 doesn't have a pinmux group named spi_cs1. The cs1 is part of the "spi refclk" group. The function "spi refclk" enables the second chip select. On reset, the pins of the "spi refclk" group are used as reference clock and GPIO. Signed-off-by: Mathias Kresin --- diff --git a/target/linux/ramips/dts/mt7620a.dtsi b/target/linux/ramips/dts/mt7620a.dtsi index 4a1b875e499..8cb397cd22f 100644 --- a/target/linux/ramips/dts/mt7620a.dtsi +++ b/target/linux/ramips/dts/mt7620a.dtsi @@ -343,8 +343,8 @@ spi_cs1: spi1 { spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; + ralink,group = "spi refclk"; + ralink,function = "spi refclk"; }; }; diff --git a/target/linux/ramips/dts/mt7620n.dtsi b/target/linux/ramips/dts/mt7620n.dtsi index b211f07cf6c..1a72e98f095 100644 --- a/target/linux/ramips/dts/mt7620n.dtsi +++ b/target/linux/ramips/dts/mt7620n.dtsi @@ -264,8 +264,8 @@ spi_cs1: spi1 { spi1 { - ralink,group = "spi_cs1"; - ralink,function = "spi_cs1"; + ralink,group = "spi refclk"; + ralink,function = "spi refclk"; }; };