From: Edwin Lu <ewlu@rivosinc.com>
Date: Tue, 12 Sep 2023 16:31:40 +0000 (-0700)
Subject: RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert
X-Git-Tag: basepoints/gcc-15~6235
X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=360c8cad6a727d5afd43017ca1ce9a84c6db61c5;p=thirdparty%2Fgcc.git

RISC-V: Finish Typing Un-Typed Instructions and Turn on Assert

Updates autovec instruction that was added after last patch and turns on the
assert statement to ensure all new instructions have a type.

	* config/riscv/autovec-opt.md: Update type
	* config/riscv/riscv.cc (riscv_sched_variable_issue): Enable assert

Reviewed-by: Jeff Law <jlaw@ventanamicro.com>
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---

diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 58e80044f1ee..f1d058ce911b 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -649,7 +649,8 @@
                gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
   riscv_vector::expand_cond_len_unop (icode, ops);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
 (define_insn_and_split "*copysign<mode>_neg"
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 0ecda795b388..9d04ddd69e07 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7721,11 +7721,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
   if (get_attr_type (insn) == TYPE_GHOST)
     return 0;
 
-#if 0
   /* If we ever encounter an insn with an unknown type, trip
      an assert so we can find and fix this problem.  */
   gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN);
-#endif
 
   return more - 1;
 }