From: Brian Ruley Date: Fri, 13 Feb 2026 08:49:51 +0000 (+0200) Subject: clk: imx6q: apply clang-format X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3632346f4bcfb2b40505a382d166dcbcd5516760;p=thirdparty%2Fu-boot.git clk: imx6q: apply clang-format Reduces the number of checkpatch warnings in the following commits. Signed-off-by: Brian Ruley --- diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index b69355cefc7..f11f9045abb 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -31,12 +31,28 @@ static struct clk_ops imx6q_clk_ops = { .disable = ccf_clk_disable, }; -static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; -static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; -static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", - "pll2_pfd0_352m", "pll2_198m", }; -static const char *const uart_sels[] = { "pll3_80m", "osc", }; -static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; +static const char *const usdhc_sels[] = { + "pll2_pfd2_396m", + "pll2_pfd0_352m", +}; +static const char *const periph_sels[] = { + "periph_pre", + "periph_clk2", +}; +static const char *const periph_pre_sels[] = { + "pll2_bus", + "pll2_pfd2_396m", + "pll2_pfd0_352m", + "pll2_198m", +}; +static const char *const uart_sels[] = { + "pll3_80m", + "osc", +}; +static const char *const ecspi_sels[] = { + "pll3_60m", + "osc", +}; static int imx6q_clk_probe(struct udevice *dev) { @@ -52,13 +68,13 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_pllv3(dev, IMX_PLLV3_USB, "pll3_usb_otg", "osc", base + 0x10, 0x3)); clk_dm(IMX6QDL_CLK_PLL3_60M, - imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); + imx_clk_fixed_factor(dev, "pll3_60m", "pll3_usb_otg", 1, 8)); clk_dm(IMX6QDL_CLK_PLL2_PFD0_352M, imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); - clk_dm(IMX6QDL_CLK_PLL6, - imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL6, imx_clk_pllv3(dev, IMX_PLLV3_ENET, "pll6", + "osc", base + 0xe0, 0x3)); clk_dm(IMX6QDL_CLK_PLL6_ENET, imx_clk_gate(dev, "pll6_enet", "pll6", base + 0xe0, 13)); @@ -68,50 +84,54 @@ static int imx6q_clk_probe(struct udevice *dev) return -EINVAL; clk_dm(IMX6QDL_CLK_USDHC1_SEL, - imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc1_sel", base + 0x1c, 16, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC2_SEL, - imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc2_sel", base + 0x1c, 17, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC3_SEL, - imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc3_sel", base + 0x1c, 18, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); clk_dm(IMX6QDL_CLK_USDHC4_SEL, - imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, - usdhc_sels, ARRAY_SIZE(usdhc_sels))); + imx_clk_mux(dev, "usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, + ARRAY_SIZE(usdhc_sels))); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SEL, - imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, uart_sels, - ARRAY_SIZE(uart_sels))); + imx_clk_mux(dev, "uart_sel", base + 0x24, 6, 1, + uart_sels, ARRAY_SIZE(uart_sels))); clk_dm(IMX6QDL_CLK_ECSPI_SEL, - imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, ecspi_sels, - ARRAY_SIZE(ecspi_sels))); + imx_clk_mux(dev, "ecspi_sel", base + 0x38, 18, 1, + ecspi_sels, ARRAY_SIZE(ecspi_sels))); } clk_dm(IMX6QDL_CLK_USDHC1_PODF, - imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", - base + 0x24, 11, 3)); + imx_clk_divider(dev, "usdhc1_podf", "usdhc1_sel", base + 0x24, + 11, 3)); clk_dm(IMX6QDL_CLK_USDHC2_PODF, - imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", - base + 0x24, 16, 3)); + imx_clk_divider(dev, "usdhc2_podf", "usdhc2_sel", base + 0x24, + 16, 3)); clk_dm(IMX6QDL_CLK_USDHC3_PODF, - imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", - base + 0x24, 19, 3)); + imx_clk_divider(dev, "usdhc3_podf", "usdhc3_sel", base + 0x24, + 19, 3)); clk_dm(IMX6QDL_CLK_USDHC4_PODF, - imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", - base + 0x24, 22, 3)); + imx_clk_divider(dev, "usdhc4_podf", "usdhc4_sel", base + 0x24, + 22, 3)); if (of_machine_is_compatible("fsl,imx6qp")) { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider(dev, "uart_serial_podf", "uart_sel", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "uart_sel", + base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider(dev, "ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "ecspi_sel", + base + 0x38, 19, 6)); } else { clk_dm(IMX6QDL_CLK_UART_SERIAL_PODF, - imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", base + 0x24, 0, 6)); + imx_clk_divider(dev, "uart_serial_podf", "pll3_80m", + base + 0x24, 0, 6)); clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider(dev, "ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + imx_clk_divider(dev, "ecspi_root", "pll3_60m", + base + 0x38, 19, 6)); } clk_dm(IMX6QDL_CLK_ECSPI1, @@ -125,7 +145,8 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_UART_IPG, imx_clk_gate2(dev, "uart_ipg", "ipg", base + 0x7c, 24)); clk_dm(IMX6QDL_CLK_UART_SERIAL, - imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", base + 0x7c, 26)); + imx_clk_gate2(dev, "uart_serial", "uart_serial_podf", + base + 0x7c, 26)); clk_dm(IMX6QDL_CLK_USDHC1, imx_clk_gate2(dev, "usdhc1", "usdhc1_podf", base + 0x80, 2)); clk_dm(IMX6QDL_CLK_USDHC2, @@ -136,11 +157,11 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2(dev, "usdhc4", "usdhc4_podf", base + 0x80, 8)); clk_dm(IMX6QDL_CLK_PERIPH_PRE, - imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, periph_pre_sels, - ARRAY_SIZE(periph_pre_sels))); + imx_clk_mux(dev, "periph_pre", base + 0x18, 18, 2, + periph_pre_sels, ARRAY_SIZE(periph_pre_sels))); clk_dm(IMX6QDL_CLK_PERIPH, - imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, - 5, periph_sels, ARRAY_SIZE(periph_sels))); + imx_clk_busy_mux(dev, "periph", base + 0x14, 25, 1, base + 0x48, + 5, periph_sels, ARRAY_SIZE(periph_sels))); clk_dm(IMX6QDL_CLK_AHB, imx_clk_busy_divider(dev, "ahb", "periph", base + 0x14, 10, 3, base + 0x48, 1)); @@ -163,7 +184,8 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_PWM4, imx_clk_gate2(dev, "pwm4", "ipg_per", base + 0x78, 22)); - clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET, + imx_clk_gate2(dev, "enet", "ipg", base + 0x6c, 10)); clk_dm(IMX6QDL_CLK_ENET_REF, imx_clk_fixed_factor(dev, "enet_ref", "pll6_enet", 1, 1)); @@ -172,7 +194,7 @@ static int imx6q_clk_probe(struct udevice *dev) static const struct udevice_id imx6q_clk_ids[] = { { .compatible = "fsl,imx6q-ccm" }, - { }, + {}, }; U_BOOT_DRIVER(imx6q_clk) = {