From: Clint Taylor Date: Mon, 13 Apr 2026 20:08:25 +0000 (-0700) Subject: drm/xe/xe3p: add gt tuning TileY 2x2 walk pattern X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=36acdfbc2cad67f550021725d6550bb0d4973217;p=thirdparty%2Fkernel%2Flinux.git drm/xe/xe3p: add gt tuning TileY 2x2 walk pattern Apply engine tuning for TileY 2x2 walk pattern, starting with IP Xe3p_LPG. v2: move to xe tunings (MattR) Bspec: 72161, 73720 Signed-off-by: Clint Taylor Link: https://patch.msgid.link/20260413200825.4054940-1-clinton.a.taylor@intel.com Signed-off-by: Matt Roper --- diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h index a4472b7acb18a..87a99efa47651 100644 --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h @@ -536,6 +536,9 @@ #define SLM_WMTP_RESTORE REG_BIT(11) #define RES_CHK_SPR_DIS REG_BIT(6) +#define TDL_TSL_CHICKEN2 XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED) +#define TILEY_LOCALID REG_BIT(2) + #define ROW_CHICKEN XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED) #define UGM_BACKUP_MODE REG_BIT(13) #define MDQ_ARBITRATION_MODE REG_BIT(12) diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c index 6fb8887d14828..ce39b77a084ad 100644 --- a/drivers/gpu/drm/xe/xe_tuning.c +++ b/drivers/gpu/drm/xe/xe_tuning.c @@ -124,6 +124,11 @@ static const struct xe_rtp_entry_sr engine_tunings[] = { GHWSP_CSB_REPORT_DIS, XE_RTP_ACTION_FLAG(ENGINE_BASE))) }, + { XE_RTP_NAME("Tuning: TileY 2x2 Walk"), + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED), + FUNC(xe_rtp_match_first_render_or_compute)), + XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID)) + }, }; static const struct xe_rtp_entry_sr lrc_tunings[] = {