From: Florian Krohm Date: Fri, 2 Jan 2026 16:44:49 +0000 (+0000) Subject: s390: Use objdump machinery to disassemble insns X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=370531396ad180a30332caa6a22bb08e836e266b;p=thirdparty%2Fvalgrind.git s390: Use objdump machinery to disassemble insns New directory VEX/priv/objdump to contain the bits and pieces needed from binutils. s390_disasm.c removed as the S390_DISASM machinery is no longer needed. host_s390_defs.c and guest_s390_toIR.c adjusted accordingly. Part of fixing https://bugs.kde.org/show_bug.cgi?id=510840 --- diff --git a/.gitignore b/.gitignore index 7bdac9edf..039ce52a9 100644 --- a/.gitignore +++ b/.gitignore @@ -2538,6 +2538,10 @@ none/tests/freebsd/bug499212 /VEX/priv/.deps /VEX/priv/.dirstamp +# /VEX/priv/objdump +/VEX/priv/objdump/.deps +/VEX/priv/objdump/.dirstamp + # /VEX/pub/ /VEX/pub/libvex_guest_offsets.h diff --git a/Makefile.vex.am b/Makefile.vex.am index f75e9b4c6..437053e03 100644 --- a/Makefile.vex.am +++ b/Makefile.vex.am @@ -68,7 +68,10 @@ noinst_HEADERS = \ priv/host_mips_defs.h \ priv/host_nanomips_defs.h \ priv/common_nanomips_defs.h \ - priv/host_riscv64_defs.h + priv/host_riscv64_defs.h \ + priv/objdump/dis-asm.h \ + priv/objdump/s390.h \ + priv/objdump/stubs.h BUILT_SOURCES = pub/libvex_guest_offsets.h CLEANFILES = pub/libvex_guest_offsets.h @@ -178,13 +181,16 @@ LIBVEX_SOURCES_COMMON = \ priv/host_arm64_isel.c \ priv/host_s390_defs.c \ priv/host_s390_isel.c \ - priv/s390_disasm.c \ priv/host_mips_defs.c \ priv/host_nanomips_defs.c \ priv/host_mips_isel.c \ priv/host_nanomips_isel.c \ priv/host_riscv64_defs.c \ - priv/host_riscv64_isel.c + priv/host_riscv64_isel.c \ + priv/objdump/dis-init.c \ + priv/objdump/s390-dis.c \ + priv/objdump/s390-opc.c \ + priv/objdump/s390-opc.tab LIBVEXMULTIARCH_SOURCES = priv/multiarch_main_main.c diff --git a/NEWS b/NEWS index 4a2593eaf..e0bdc122c 100644 --- a/NEWS +++ b/NEWS @@ -8,7 +8,7 @@ X86/Android, X86/Solaris, AMD64/Solaris, X86/macOS, AMD64/macOS. X86/FreeBSD, AMD64/FreeBSD and ARM64/FreeBSD. There is preliminary support for nanoMIPS/Linux. macOS is supported up to version 12 Monterey (amd64 only). -* ==================== CORE CHANGES =================== + ==================== CORE CHANGES =================== * ================== PLATFORM CHANGES ================= @@ -1121,6 +1121,7 @@ are not entered into bugzilla tend to get forgotten about or ignored. 506211 Constant folding improvements 506453 Unexpected behaviour with IR injection and vex-guest-chase=yes 509157 riscv64: Shift instructions can behave wrong +510840 Use objdump for disassembly in VEX (s390x only) To see details of a given bug, visit https://bugs.kde.org/show_bug.cgi?id=XXXXXX diff --git a/VEX/priv/guest_s390_toIR.c b/VEX/priv/guest_s390_toIR.c index 9e850b78f..11c50dc00 100644 --- a/VEX/priv/guest_s390_toIR.c +++ b/VEX/priv/guest_s390_toIR.c @@ -49,17 +49,6 @@ static UInt s390_decode_and_irgen(const UChar *, UInt, DisResult *); static void s390_irgen_xonc(IROp, IRTemp, IRTemp, IRTemp); static void s390_irgen_CLC_EX(IRTemp, IRTemp, IRTemp); -static const HChar *s390_irgen_BIC(UChar, IRTemp); -static const HChar *s390_irgen_VPDI(UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VFLR(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VFI(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VFPSO(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VCGD(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VCDG(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VCDLG(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_VCLGD(UChar, UChar, UChar, UChar, UChar); -static const HChar *s390_irgen_KMA(UChar, UChar, UChar); -static const HChar *s390_irgen_KMCTR(UChar, UChar, UChar); /*------------------------------------------------------------*/ /*--- Globals ---*/ @@ -661,12 +650,12 @@ yield_if(IRExpr *condition) /* Convenience macro to yield a specification exception if the given condition is not met. Used to pass this type of decoding error up through the call chain. */ -#define s390_insn_assert(mnm, cond) \ +#define s390_insn_assert(cond) \ do { \ if (!(cond)) { \ dis_res->whatNext = Dis_StopHere; \ dis_res->jk_StopHere = Ijk_NoDecode; \ - return (mnm); \ + return; \ } \ } while (0) @@ -2716,622 +2705,440 @@ convert_vex_dfpcc_to_s390(IRTemp vex_cc) /*--- Build IR for formats ---*/ /*------------------------------------------------------------*/ static void -s390_format_I(const HChar *(*irgen)(UChar i), +s390_format_I(void (*irgen)(UChar i), UChar i) { - const HChar *mnm = irgen(i); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UINT(i)); + irgen(i); } static void -s390_format_IE(const HChar *(*irgen)(UChar i1, UChar i2), +s390_format_IE(void (*irgen)(UChar i1, UChar i2), UChar i1, UChar i2) { - const HChar *mnm = irgen(i1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UINT(i1), UINT(i2)); + irgen(i1, i2); } static void -s390_format_E(const HChar *(*irgen)(void)) +s390_format_E(void (*irgen)(void)) { - const HChar *mnm = irgen(); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm)); + irgen(); } static void -s390_format_MII_UPP(const HChar *(*irgen)(UChar m1, UShort i2, UInt i3), +s390_format_MII_UPP(void (*irgen)(UChar m1, UShort i2, UInt i3), UChar m1, UShort i2, UInt i3) { - const HChar *mnm; - - mnm = irgen(m1, i2, i3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UINT(m1), PCREL((Int)((Short)(i2 << 4) >> 4)), - PCREL((Int)(i3 << 8) >> 8)); + irgen(m1, i2, i3); } static void -s390_format_RI(const HChar *(*irgen)(UChar r1, UShort i2), +s390_format_RI(void (*irgen)(UChar r1, UShort i2), UChar r1, UShort i2) { irgen(r1, i2); } static void -s390_format_RI_RU(const HChar *(*irgen)(UChar r1, UShort i2), +s390_format_RI_RU(void (*irgen)(UChar r1, UShort i2), UChar r1, UShort i2) { - const HChar *mnm = irgen(r1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UINT(i2)); + irgen(r1, i2); } static void -s390_format_RI_RI(const HChar *(*irgen)(UChar r1, UShort i2), +s390_format_RI_RI(void (*irgen)(UChar r1, UShort i2), UChar r1, UShort i2) { - const HChar *mnm = irgen(r1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), INT((Int)(Short)i2)); + irgen(r1, i2); } static void -s390_format_RI_RP(const HChar *(*irgen)(UChar r1, UShort i2), +s390_format_RI_RP(void (*irgen)(UChar r1, UShort i2), UChar r1, UShort i2) { - const HChar *mnm = irgen(r1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), PCREL((Int)(Short)i2)); + irgen(r1, i2); } static void -s390_format_RIE_RRP(const HChar *(*irgen)(UChar r1, UChar r3, UShort i2), +s390_format_RIE_RRP(void (*irgen)(UChar r1, UChar r3, UShort i2), UChar r1, UChar r3, UShort i2) { - const HChar *mnm = irgen(r1, r3, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), PCREL((Int)(Short)i2)); + irgen(r1, r3, i2); } static void -s390_format_RIE_RRI0(const HChar *(*irgen)(UChar r1, UChar r3, UShort i2), +s390_format_RIE_RRI0(void (*irgen)(UChar r1, UChar r3, UShort i2), UChar r1, UChar r3, UShort i2) { - const HChar *mnm = irgen(r1, r3, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), INT((Int)(Short)i2)); + irgen(r1, r3, i2); } static void -s390_format_RIE_RRUUU(const HChar *(*irgen)(UChar r1, UChar r2, UChar i3, - UChar i4, UChar i5), +s390_format_RIE_RRUUU(void (*irgen)(UChar r1, UChar r2, UChar i3, + UChar i4, UChar i5), UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { - const HChar *mnm = irgen(r1, r2, i3, i4, i5); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, rotate_disasm), GPR(r1), GPR(r2), MASK(i3), MASK(i4), MASK(i5)); + irgen(r1, r2, i3, i4, i5); } static void -s390_format_R0UU(const HChar *(*irgen)(UChar r1, UShort i2, UChar m3), +s390_format_R0UU(void (*irgen)(UChar r1, UShort i2, UChar m3), UChar r1, UShort i2, UChar m3) { - const HChar *mnm = irgen(r1, i2, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), INT(i2), MASK(m3)); + irgen(r1, i2, m3); } static void -s390_format_R0IU(const HChar *(*irgen)(UChar r1, UShort i2, UChar m3), +s390_format_R0IU(void (*irgen)(UChar r1, UShort i2, UChar m3), UChar r1, UShort i2, UChar m3) { - const HChar *mnm = irgen(r1, i2, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), INT((Int)(Short)i2), MASK(m3)); + irgen(r1, i2, m3); } static void -s390_format_RIE_RRPU(const HChar *(*irgen)(UChar r1, UChar r2, UShort i4, - UChar m3), +s390_format_RIE_RRPU(void (*irgen)(UChar r1, UChar r2, UShort i4, UChar m3), UChar r1, UChar r2, UShort i4, UChar m3) { - const HChar *mnm = irgen(r1, r2, i4, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), GPR(r2), MASK(m3), PCREL((Int)(Short)i4)); + irgen(r1, r2, i4, m3); } static void -s390_format_RIE_RUPU(const HChar *(*irgen)(UChar r1, UChar m3, UShort i4, - UChar i2), +s390_format_RIE_RUPU(void (*irgen)(UChar r1, UChar m3, UShort i4, UChar i2), UChar r1, UChar m3, UShort i4, UChar i2) { - const HChar *mnm = irgen(r1, m3, i4, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), UINT(i2), MASK(m3), PCREL((Int)(Short)i4)); + irgen(r1, m3, i4, i2); } static void -s390_format_RIE_RUPI(const HChar *(*irgen)(UChar r1, UChar m3, UShort i4, - UChar i2), +s390_format_RIE_RUPI(void (*irgen)(UChar r1, UChar m3, UShort i4, UChar i2), UChar r1, UChar m3, UShort i4, UChar i2) { - const HChar *mnm = irgen(r1, m3, i4, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), INT((Int)(Char)i2), MASK(m3), PCREL((Int)(Short)i4)); + irgen(r1, m3, i4, i2); } static void -s390_format_RIE_RUPIX(const HChar *(*irgen)(UChar r1, UChar m3, UShort i2), +s390_format_RIE_RUPIX(void (*irgen)(UChar r1, UChar m3, UShort i2), UChar r1, UChar m3, UShort i2) { - const HChar *mnm = irgen(r1, m3, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cls_disasm), GPR(r1), INT((Int)(Short)i2), MASK(m3)); + irgen(r1, m3, i2); } static void -s390_format_RIL(const HChar *(*irgen)(UChar r1, UInt i2), +s390_format_RIL(void (*irgen)(UChar r1, UInt i2), UChar r1, UInt i2) { irgen(r1, i2); } static void -s390_format_RIL_RU(const HChar *(*irgen)(UChar r1, UInt i2), +s390_format_RIL_RU(void (*irgen)(UChar r1, UInt i2), UChar r1, UInt i2) { - const HChar *mnm = irgen(r1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UINT(i2)); + irgen(r1, i2); } static void -s390_format_RIL_RI(const HChar *(*irgen)(UChar r1, UInt i2), +s390_format_RIL_RI(void (*irgen)(UChar r1, UInt i2), UChar r1, UInt i2) { - const HChar *mnm = irgen(r1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), INT(i2)); + irgen(r1, i2); } static void -s390_format_RIL_RP(const HChar *(*irgen)(UChar r1, UInt i2), +s390_format_RIL_RP(void (*irgen)(UChar r1, UInt i2), UChar r1, UInt i2) { - const HChar *mnm = irgen(r1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), PCREL(i2)); + irgen(r1, i2); } static void -s390_format_RIL_UP(const HChar *(*irgen)(void), - UChar r1, UInt i2) +s390_format_RIL_UP(void (*irgen)(void), + UChar r1 __attribute__((unused)), + UInt i2 __attribute__((unused))) { - const HChar *mnm = irgen(); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UINT(r1), PCREL(i2)); + irgen(); } static void -s390_format_RIS_RURDI(const HChar *(*irgen)(UChar r1, UChar m3, UChar i2, - IRTemp op4addr), +s390_format_RIS_RURDI(void (*irgen)(UChar r1, UChar m3, UChar i2, + IRTemp op4addr), UChar r1, UChar m3, UChar b4, UShort d4, UChar i2) { - const HChar *mnm; IRTemp op4addr = newTemp(Ity_I64); assign(op4addr, binop(Iop_Add64, mkU64(d4), b4 != 0 ? get_gpr_dw0(b4) : mkU64(0))); - mnm = irgen(r1, m3, i2, op4addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), INT((Int)(Char)i2), MASK(m3), UDXB(d4, 0, b4)); + irgen(r1, m3, i2, op4addr); } static void -s390_format_RIS_RURDU(const HChar *(*irgen)(UChar r1, UChar m3, UChar i2, - IRTemp op4addr), +s390_format_RIS_RURDU(void (*irgen)(UChar r1, UChar m3, UChar i2, + IRTemp op4addr), UChar r1, UChar m3, UChar b4, UShort d4, UChar i2) { - const HChar *mnm; IRTemp op4addr = newTemp(Ity_I64); assign(op4addr, binop(Iop_Add64, mkU64(d4), b4 != 0 ? get_gpr_dw0(b4) : mkU64(0))); - mnm = irgen(r1, m3, i2, op4addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), UINT(i2), MASK(m3), UDXB(d4, 0, b4)); + irgen(r1, m3, i2, op4addr); } static void -s390_format_RR(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RR(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { irgen(r1, r2); } static void -s390_format_RR_RR(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RR_RR(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { - const HChar *mnm = irgen(r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r2)); + irgen(r1, r2); } static void -s390_format_RR_FF(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RR_FF(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { - const HChar *mnm = irgen(r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r2)); + irgen(r1, r2); } static void -s390_format_RRE(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RRE(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { irgen(r1, r2); } static void -s390_format_RRE_RR(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RRE_RR(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { - const HChar *mnm = irgen(r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r2)); + irgen(r1, r2); } static void -s390_format_RRE_FF(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RRE_FF(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { - const HChar *mnm = irgen(r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r2)); + irgen(r1, r2); } static void -s390_format_RRE_RF(const HChar *(*irgen)(UChar, UChar), +s390_format_RRE_RF(void (*irgen)(UChar, UChar), UChar r1, UChar r2) { - const HChar *mnm = irgen(r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), FPR(r2)); + irgen(r1, r2); } static void -s390_format_RRE_FR(const HChar *(*irgen)(UChar r1, UChar r2), +s390_format_RRE_FR(void (*irgen)(UChar r1, UChar r2), UChar r1, UChar r2) { - const HChar *mnm = irgen(r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), GPR(r2)); + irgen(r1, r2); } static void -s390_format_RRE_R0(const HChar *(*irgen)(UChar r1), +s390_format_RRE_R0(void (*irgen)(UChar r1), UChar r1) { - const HChar *mnm = irgen(r1); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1)); + irgen(r1); } static void -s390_format_RRE_F0(const HChar *(*irgen)(UChar r1), +s390_format_RRE_F0(void (*irgen)(UChar r1), UChar r1) { - const HChar *mnm = irgen(r1); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1)); + irgen(r1); } static void -s390_format_RRF_M0RERE(const HChar *(*irgen)(UChar m3, UChar r1, UChar r2), +s390_format_RRF_M0RERE(void (*irgen)(UChar m3, UChar r1, UChar r2), UChar m3, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, mask0_disasm), GPR(r1), GPR(r2), MASK(m3)); + irgen(m3, r1, r2); } static void -s390_format_RRF_F0FF(const HChar *(*irgen)(UChar, UChar, UChar), +s390_format_RRF_F0FF(void (*irgen)(UChar, UChar, UChar), UChar r1, UChar r3, UChar r2) { - const HChar *mnm = irgen(r1, r3, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r3), FPR(r2)); + irgen(r1, r3, r2); } static void -s390_format_RRF_F0FR(const HChar *(*irgen)(UChar, UChar, UChar), +s390_format_RRF_F0FR(void (*irgen)(UChar, UChar, UChar), UChar r3, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r3), GPR(r2)); + irgen(r3, r1, r2); } static void -s390_format_RRF_UUFF(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1, - UChar r2), +s390_format_RRF_UUFF(void (*irgen)(UChar m3, UChar m4, UChar r1, UChar r2), UChar m3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); + irgen(m3, m4, r1, r2); } static void -s390_format_RRF_UUFF2(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1, - UChar r2), +s390_format_RRF_UUFF2(void (*irgen)(UChar m3, UChar m4, UChar r1, UChar r2), UChar m3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); + irgen(m3, m4, r1, r2); } static void -s390_format_RRF_0UFF(const HChar *(*irgen)(UChar m4, UChar r1, UChar r2), +s390_format_RRF_0UFF(void (*irgen)(UChar m4, UChar r1, UChar r2), UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r2), UINT(m4)); + irgen(m4, r1, r2); } static void -s390_format_RRF_UUFR(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1, - UChar r2), +s390_format_RRF_UUFR(void (*irgen)(UChar m3, UChar m4, UChar r1, UChar r2), UChar m3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); + irgen(m3, m4, r1, r2); } static void -s390_format_RRF_UURF(const HChar *(*irgen)(UChar m3, UChar m4, UChar r1, - UChar r2), +s390_format_RRF_UURF(void (*irgen)(UChar m3, UChar m4, UChar r1, UChar r2), UChar m3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); + irgen(m3, m4, r1, r2); } static void -s390_format_RRF_U0RR(const HChar *(*irgen)(UChar m3, UChar r1, UChar r2), - UChar m3, UChar r1, UChar r2, HChar *(*handler)(const s390_opnd *, HChar *)) +s390_format_RRF_U0RR(void (*irgen)(UChar m3, UChar r1, UChar r2), + UChar m3, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, handler), GPR(r1), GPR(r2), MASK(m3)); + irgen(m3, r1, r2); } static void -s390_format_RRFa_U0RR(const HChar *(*irgen)(UChar m3, UChar r1, UChar r2), +s390_format_RRFa_U0RR(void (*irgen)(UChar m3, UChar r1, UChar r2), UChar m3, UChar r1, UChar r2) { - const HChar *mnm = irgen(m3, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) { - if (m3 != 0) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r2), UINT(m3)); - else - S390_DISASM(MNM(mnm), GPR(r1), GPR(r2)); - } + irgen(m3, r1, r2); } static void -s390_format_RRF_F0FF2(const HChar *(*irgen)(UChar, UChar, UChar), +s390_format_RRF_F0FF2(void (*irgen)(UChar, UChar, UChar), UChar r3, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r3), FPR(r2)); + irgen(r3, r1, r2); } static void -s390_format_RRF_FFRU(const HChar *(*irgen)(UChar, UChar, UChar, UChar), +s390_format_RRF_FFRU(void (*irgen)(UChar, UChar, UChar, UChar), UChar r3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r3), GPR(r2), UINT(m4)); + irgen(r3, m4, r1, r2); } static void -s390_format_RRF_FUFF(const HChar *(*irgen)(UChar, UChar, UChar, UChar), +s390_format_RRF_FUFF(void (*irgen)(UChar, UChar, UChar, UChar), UChar r3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r3), FPR(r2), UINT(m4)); + irgen(r3, m4, r1, r2); } static void -s390_format_RRF_FUFF2(const HChar *(*irgen)(UChar, UChar, UChar, UChar), +s390_format_RRF_FUFF2(void (*irgen)(UChar, UChar, UChar, UChar), UChar r3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); + irgen(r3, m4, r1, r2); } static void -s390_format_RRF_RURR(const HChar *(*irgen)(UChar, UChar, UChar, UChar), +s390_format_RRF_RURR(void (*irgen)(UChar, UChar, UChar, UChar), UChar r3, UChar m4, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, m4, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cls_disasm), GPR(r1), GPR(r2), GPR(r3), MASK(m4)); + irgen(r3, m4, r1, r2); } static void -s390_format_RRF_R0RR2(const HChar *(*irgen)(UChar r3, UChar r1, UChar r2), +s390_format_RRF_R0RR2(void (*irgen)(UChar r3, UChar r1, UChar r2), UChar r3, UChar r1, UChar r2) { - const HChar *mnm = irgen(r3, r1, r2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) { - if (irgen == s390_irgen_KMA || irgen == s390_irgen_KMCTR) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), GPR(r2)); - else - S390_DISASM(MNM(mnm), GPR(r1), GPR(r2), GPR(r3)); - } + irgen(r3, r1, r2); } static void -s390_format_RRS(const HChar *(*irgen)(UChar r1, UChar r2, UChar m3, - IRTemp op4addr), +s390_format_RRS(void (*irgen)(UChar r1, UChar r2, UChar m3, IRTemp op4addr), UChar r1, UChar r2, UChar b4, UShort d4, UChar m3) { - const HChar *mnm; IRTemp op4addr = newTemp(Ity_I64); assign(op4addr, binop(Iop_Add64, mkU64(d4), b4 != 0 ? get_gpr_dw0(b4) : mkU64(0))); - mnm = irgen(r1, r2, m3, op4addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), GPR(r2), MASK(m3), UDXB(d4, 0, b4)); + irgen(r1, r2, m3, op4addr); } static void -s390_format_RS_R0RD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RS_R0RD(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UDXB(d2, 0, b2)); + irgen(r1, op2addr); } static void -s390_format_RS_RRRD(const HChar *(*irgen)(UChar r1, UChar r3, IRTemp op2addr), +s390_format_RS_RRRD(void (*irgen)(UChar r1, UChar r3, IRTemp op2addr), UChar r1, UChar r3, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, r3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), UDXB(d2, 0, b2)); + irgen(r1, r3, op2addr); } static void -s390_format_RS_RURD(const HChar *(*irgen)(UChar r1, UChar r3, IRTemp op2addr), +s390_format_RS_RURD(void (*irgen)(UChar r1, UChar r3, IRTemp op2addr), UChar r1, UChar r3, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, r3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UINT(r3), UDXB(d2, 0, b2)); + irgen(r1, r3, op2addr); } static void -s390_format_RS_AARD(const HChar *(*irgen)(UChar, UChar, IRTemp), +s390_format_RS_AARD(void (*irgen)(UChar, UChar, IRTemp), UChar r1, UChar r3, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, r3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), AR(r1), AR(r3), UDXB(d2, 0, b2)); + irgen(r1, r3, op2addr); } static void -s390_format_RSI_RRP(const HChar *(*irgen)(UChar r1, UChar r3, UShort i2), +s390_format_RSI_RRP(void (*irgen)(UChar r1, UChar r3, UShort i2), UChar r1, UChar r3, UShort i2) { - const HChar *mnm = irgen(r1, r3, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), PCREL((Int)(Short)i2)); + irgen(r1, r3, i2); } static void -s390_format_RSY_RRRD(const HChar *(*irgen)(UChar r1, UChar r3, IRTemp op2addr), +s390_format_RSY_RRRD(void (*irgen)(UChar r1, UChar r3, IRTemp op2addr), UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); IRTemp d2 = newTemp(Ity_I64); @@ -3339,17 +3146,13 @@ s390_format_RSY_RRRD(const HChar *(*irgen)(UChar r1, UChar r3, IRTemp op2addr), assign(op2addr, binop(Iop_Add64, mkexpr(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, r3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); + irgen(r1, r3, op2addr); } static void -s390_format_RSY_AARD(const HChar *(*irgen)(UChar, UChar, IRTemp), +s390_format_RSY_AARD(void (*irgen)(UChar, UChar, IRTemp), UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); IRTemp d2 = newTemp(Ity_I64); @@ -3357,17 +3160,13 @@ s390_format_RSY_AARD(const HChar *(*irgen)(UChar, UChar, IRTemp), assign(op2addr, binop(Iop_Add64, mkexpr(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, r3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), AR(r1), AR(r3), SDXB(dh2, dl2, 0, b2)); + irgen(r1, r3, op2addr); } static void -s390_format_RSY_RURD(const HChar *(*irgen)(UChar r1, UChar m3, IRTemp op2addr), +s390_format_RSY_RURD(void (*irgen)(UChar r1, UChar m3, IRTemp op2addr), UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); IRTemp d2 = newTemp(Ity_I64); @@ -3375,17 +3174,13 @@ s390_format_RSY_RURD(const HChar *(*irgen)(UChar r1, UChar m3, IRTemp op2addr), assign(op2addr, binop(Iop_Add64, mkexpr(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, m3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UINT(m3), SDXB(dh2, dl2, 0, b2)); + irgen(r1, m3, op2addr); } static void -s390_format_RSY_R0RD(const HChar *(*irgen)(UChar r1, UChar m3, IRTemp op2addr), +s390_format_RSY_R0RD(void (*irgen)(UChar r1, UChar m3, IRTemp op2addr), UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); IRTemp d2 = newTemp(Ity_I64); @@ -3393,14 +3188,11 @@ s390_format_RSY_R0RD(const HChar *(*irgen)(UChar r1, UChar m3, IRTemp op2addr), assign(op2addr, binop(Iop_Add64, mkexpr(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(r1, m3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cabt_disasm), GPR(r1), MASK(m3), SDXB(dh2, dl2, 0, b2)); + irgen(r1, m3, op2addr); } static void -s390_format_RSY_RDRM(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RSY_RDRM(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) { IRTemp op2addr = newTemp(Ity_I64); @@ -3412,17 +3204,14 @@ s390_format_RSY_RDRM(const HChar *(*irgen)(UChar r1, IRTemp op2addr), assign(op2addr, binop(Iop_Add64, mkexpr(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - const HChar *mnm = irgen(r1, op2addr); + irgen(r1, op2addr); vassert(dis_res->whatNext == Dis_Continue); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, cls_disasm), GPR(r1), SDXB(dh2, dl2, 0, b2), MASK(m3)); } static void -s390_format_RX(const HChar *(*irgen)(UChar r1, UChar x2, UChar b2, UShort d2, - IRTemp op2addr), +s390_format_RX(void (*irgen)(UChar r1, UChar x2, UChar b2, UShort d2, + IRTemp op2addr), UChar r1, UChar x2, UChar b2, UShort d2) { IRTemp op2addr = newTemp(Ity_I64); @@ -3435,95 +3224,74 @@ s390_format_RX(const HChar *(*irgen)(UChar r1, UChar x2, UChar b2, UShort d2, } static void -s390_format_RX_RRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RX_RRRD(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar x2, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UDXB(d2, x2, b2)); + irgen(r1, op2addr); } static void -s390_format_RX_FRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RX_FRRD(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar x2, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), UDXB(d2, x2, b2)); + irgen(r1, op2addr); } static void -s390_format_RXE_FRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RXE_FRRD(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar x2, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), UDXB(d2, x2, b2)); + irgen(r1, op2addr); } static void -s390_format_RXE_RRRDR(const HChar *(*irgen)(UChar r1, IRTemp op2addr, UChar m3), - UChar r1, UChar x2, UChar b2, UShort d2, UChar m3) +s390_format_RXE_RRRDR(void (*irgen)(UChar r1, IRTemp op2addr, UChar m3), + UChar r1, UChar x2, UChar b2, UShort d2, UChar m3) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r1, op2addr, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), GPR(r1), UDXB(d2, x2, b2), UINT(m3)); + irgen(r1, op2addr, m3); } static void -s390_format_RXF_FRRDF(const HChar *(*irgen)(UChar, IRTemp, UChar), +s390_format_RXF_FRRDF(void (*irgen)(UChar, IRTemp, UChar), UChar r3, UChar x2, UChar b2, UShort d2, UChar r1) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r3, op2addr, r1); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), FPR(r3), UDXB(d2, x2, b2)); + irgen(r3, op2addr, r1); } static void -s390_format_RXY_RRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RXY_RRRD(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); IRTemp d2 = newTemp(Ity_I64); @@ -3532,21 +3300,13 @@ s390_format_RXY_RRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) { - if (irgen == s390_irgen_BIC) - S390_DISASM(XMNM(mnm, bic_disasm), MASK(r1), SDXB(dh2, dl2, x2, b2)); - else - S390_DISASM(MNM(mnm), GPR(r1), SDXB(dh2, dl2, x2, b2)); - } + irgen(r1, op2addr); } static void -s390_format_RXY_FRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), +s390_format_RXY_FRRD(void (*irgen)(UChar r1, IRTemp op2addr), UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); IRTemp d2 = newTemp(Ity_I64); @@ -3555,80 +3315,55 @@ s390_format_RXY_FRRD(const HChar *(*irgen)(UChar r1, IRTemp op2addr), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : mkU64(0))); - mnm = irgen(r1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), FPR(r1), SDXB(dh2, dl2, x2, b2)); + irgen(r1, op2addr); } static void -s390_format_RXY_URRD(const HChar *(*irgen)(void), - UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) +s390_format_RXY_URRD(void (*irgen)(void), + UChar r1 __attribute__((unused)), + UChar x2 __attribute__((unused)), + UChar b2 __attribute__((unused)), + UShort dl2 __attribute__((unused)), + UChar dh2 __attribute__((unused))) { - const HChar *mnm; - IRTemp op2addr = newTemp(Ity_I64); - IRTemp d2 = newTemp(Ity_I64); - - assign(d2, mkU64(((ULong)(Long)(Char)dh2 << 12) | ((ULong)dl2))); - assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkexpr(d2), - b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2 != 0 ? get_gpr_dw0(x2) : - mkU64(0))); - - mnm = irgen(); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UINT(r1), SDXB(dh2, dl2, x2, b2)); + irgen(); } static void -s390_format_S_RD(const HChar *(*irgen)(IRTemp op2addr), +s390_format_S_RD(void (*irgen)(IRTemp op2addr), UChar b2, UShort d2) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDXB(d2, 0, b2)); + irgen(op2addr); } static void -s390_format_S_RD_raw(const HChar *(*irgen)(UChar b2, UShort d2), +s390_format_S_RD_raw(void (*irgen)(UChar b2, UShort d2), UChar b2, UShort d2) { - const HChar *mnm; - - mnm = irgen(b2, d2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDXB(d2, 0, b2)); + irgen(b2, d2); } static void -s390_format_SI_URD(const HChar *(*irgen)(UChar i2, IRTemp op1addr), +s390_format_SI_URD(void (*irgen)(UChar i2, IRTemp op1addr), UChar i2, UChar b1, UShort d1) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); assign(op1addr, binop(Iop_Add64, mkU64(d1), b1 != 0 ? get_gpr_dw0(b1) : mkU64(0))); - mnm = irgen(i2, op1addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDXB(d1, 0, b1), UINT(i2)); + irgen(i2, op1addr); } static void -s390_format_SIY_URD(const HChar *(*irgen)(UChar i2, IRTemp op1addr), +s390_format_SIY_URD(void (*irgen)(UChar i2, IRTemp op1addr), UChar i2, UChar b1, UShort dl1, UChar dh1) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); IRTemp d1 = newTemp(Ity_I64); @@ -3636,17 +3371,13 @@ s390_format_SIY_URD(const HChar *(*irgen)(UChar i2, IRTemp op1addr), assign(op1addr, binop(Iop_Add64, mkexpr(d1), b1 != 0 ? get_gpr_dw0(b1) : mkU64(0))); - mnm = irgen(i2, op1addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), SDXB(dh1, dl1, 0, b1), UINT(i2)); + irgen(i2, op1addr); } static void -s390_format_SIY_IRD(const HChar *(*irgen)(UChar i2, IRTemp op1addr), +s390_format_SIY_IRD(void (*irgen)(UChar i2, IRTemp op1addr), UChar i2, UChar b1, UShort dl1, UChar dh1) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); IRTemp d1 = newTemp(Ity_I64); @@ -3654,33 +3385,25 @@ s390_format_SIY_IRD(const HChar *(*irgen)(UChar i2, IRTemp op1addr), assign(op1addr, binop(Iop_Add64, mkexpr(d1), b1 != 0 ? get_gpr_dw0(b1) : mkU64(0))); - mnm = irgen(i2, op1addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), SDXB(dh1, dl1, 0, b1), INT((Int)(Char)i2)); + irgen(i2, op1addr); } static void -s390_format_SMI_U0RDP(const HChar *(*irgen)(UChar m1, UShort i2, IRTemp op3addr), +s390_format_SMI_U0RDP(void (*irgen)(UChar m1, UShort i2, IRTemp op3addr), UChar m1, UShort i2, UChar b3, UShort d3) { - const HChar *mnm; IRTemp op3addr = newTemp(Ity_I64); assign(op3addr, binop(Iop_Add64, mkU64(d3), b3 != 0 ? get_gpr_dw0(b3) : mkU64(0))); - mnm = irgen(m1, i2, op3addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UINT(m1), PCREL((Int)(Short)i2), UDXB(d3, 0, b3)); + irgen(m1, i2, op3addr); } static void -s390_format_SS_L0RDRD(const HChar *(*irgen)(UChar, IRTemp, IRTemp), +s390_format_SS_L0RDRD(void (*irgen)(UChar, IRTemp, IRTemp), UChar l, UChar b1, UShort d1, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); IRTemp op2addr = newTemp(Ity_I64); @@ -3689,17 +3412,13 @@ s390_format_SS_L0RDRD(const HChar *(*irgen)(UChar, IRTemp, IRTemp), assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(l, op1addr, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDLB(d1, l, b1), UDXB(d2, 0, b2)); + irgen(l, op1addr, op2addr); } static void -s390_format_SSE_RDRD(const HChar *(*irgen)(IRTemp, IRTemp), +s390_format_SSE_RDRD(void (*irgen)(IRTemp, IRTemp), UChar b1, UShort d1, UChar b2, UShort d2) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); IRTemp op2addr = newTemp(Ity_I64); @@ -3708,49 +3427,37 @@ s390_format_SSE_RDRD(const HChar *(*irgen)(IRTemp, IRTemp), assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(op1addr, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDXB(d1, 0, b1), UDXB(d2, 0, b2)); + irgen(op1addr, op2addr); } static void -s390_format_SIL_RDI(const HChar *(*irgen)(UShort i2, IRTemp op1addr), +s390_format_SIL_RDI(void (*irgen)(UShort i2, IRTemp op1addr), UChar b1, UShort d1, UShort i2) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); assign(op1addr, binop(Iop_Add64, mkU64(d1), b1 != 0 ? get_gpr_dw0(b1) : mkU64(0))); - mnm = irgen(i2, op1addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDXB(d1, 0, b1), INT((Int)(Short)i2)); + irgen(i2, op1addr); } static void -s390_format_SIL_RDU(const HChar *(*irgen)(UShort i2, IRTemp op1addr), +s390_format_SIL_RDU(void (*irgen)(UShort i2, IRTemp op1addr), UChar b1, UShort d1, UShort i2) { - const HChar *mnm; IRTemp op1addr = newTemp(Ity_I64); assign(op1addr, binop(Iop_Add64, mkU64(d1), b1 != 0 ? get_gpr_dw0(b1) : mkU64(0))); - mnm = irgen(i2, op1addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), UDXB(d1, 0, b1), UINT(i2)); + irgen(i2, op1addr); } static void -s390_format_VRX_VRRD(const HChar *(*irgen)(UChar v1, IRTemp op2addr), +s390_format_VRX_VRRD(void (*irgen)(UChar v1, IRTemp op2addr), UChar v1, UChar x2, UChar b2, UShort d2, UChar m3, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -3763,19 +3470,15 @@ s390_format_VRX_VRRD(const HChar *(*irgen)(UChar v1, IRTemp op2addr), mkU64(0))); v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, mask0_disasm), VR(v1), UDXB(d2, x2, b2), MASK(m3)); + irgen(v1, op2addr); } static void -s390_format_VRX_VRRDM(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar m3), - UChar v1, UChar x2, UChar b2, UShort d2, UChar m3, UChar rxb, - HChar *(*handler)(const s390_opnd *, HChar *)) +s390_format_VRX_VRRDM(void (*irgen)(UChar v1, IRTemp op2addr, UChar m3), + UChar v1, UChar x2, UChar b2, UShort d2, UChar m3, + UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -3788,23 +3491,14 @@ s390_format_VRX_VRRDM(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar m3), mkU64(0))); v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, op2addr, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) { - if (handler) - S390_DISASM(XMNM(mnm, handler), VR(v1), UDXB(d2, x2, b2), MASK(m3)); - else - S390_DISASM(MNM(mnm), VR(v1), UDXB(d2, x2, b2), UINT(m3)); - } + irgen(v1, op2addr, m3); } static void -s390_format_VRR_VV(const HChar *(*irgen)(UChar v1, UChar v2), - UChar v1, UChar v2, UChar rxb) +s390_format_VRR_VV(void (*irgen)(UChar v1, UChar v2), + UChar v1, UChar v2, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -3812,19 +3506,14 @@ s390_format_VRR_VV(const HChar *(*irgen)(UChar v1, UChar v2), v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); - mnm = irgen(v1, v2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), VR(v2)); + irgen(v1, v2); } static void -s390_format_VRR_VVV(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3), +s390_format_VRR_VVV(void (*irgen)(UChar v1, UChar v2, UChar v3), UChar v1, UChar v2, UChar v3, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -3833,19 +3522,14 @@ s390_format_VRR_VVV(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3), v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), VR(v2), VR(v3)); + irgen(v1, v2, v3); } static void -s390_format_VRR_VVVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, UChar m4), - UChar v1, UChar v2, UChar v3, UChar m4, UChar rxb) +s390_format_VRR_VVVM(void (*irgen)(UChar v1, UChar v2, UChar v3, UChar m4), + UChar v1, UChar v2, UChar v3, UChar m4, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -3854,24 +3538,14 @@ s390_format_VRR_VVVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, UChar m v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, m4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) { - if (irgen == s390_irgen_VPDI) - S390_DISASM(MNM(mnm), VR(v1), VR(v2), VR(v3), UINT(m4)); - else - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - } + irgen(v1, v2, v3, m4); } static void -s390_format_VRR_VVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5), - UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar rxb, - HChar *(*handler)(const s390_opnd *, HChar *)) +s390_format_VRR_VVVMM(void (*irgen)(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5), + UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -3880,19 +3554,14 @@ s390_format_VRR_VVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, UChar v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, m4, m5); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, handler), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5)); + irgen(v1, v2, v3, m4, m5); } static void -s390_format_VRR_VVVV(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, UChar v4), - UChar v1, UChar v2, UChar v3, UChar v4, UChar rxb) +s390_format_VRR_VVVV(void (*irgen)(UChar v1, UChar v2, UChar v3, UChar v4), + UChar v1, UChar v2, UChar v3, UChar v4, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -3902,38 +3571,28 @@ s390_format_VRR_VVVV(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, UChar v v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); v4 = s390_vr_getVRindex(v4, 4, rxb); - mnm = irgen(v1, v2, v3, v4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), VR(v2), VR(v3), VR(v4)); + irgen(v1, v2, v3, v4); } static void -s390_format_VRR_VRR(const HChar *(*irgen)(UChar v1, UChar r2, UChar r3), +s390_format_VRR_VRR(void (*irgen)(UChar v1, UChar r2, UChar r3), UChar v1, UChar r2, UChar r3, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; } v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, r2, r3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), GPR(r2), GPR(r3)); + irgen(v1, r2, r3); } static void -s390_format_VRR_VVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3), +s390_format_VRR_VVM(void (*irgen)(UChar v1, UChar v2, UChar m3), UChar v1, UChar v2, UChar m3, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -3941,97 +3600,70 @@ s390_format_VRR_VVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3), v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); - mnm = irgen(v1, v2, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), VR(v2), MASK(m3)); + irgen(v1, v2, m3); } static void -s390_format_VRI_V0U(const HChar *(*irgen)(UChar v1, UShort i2), - UChar v1, UShort i2, UChar rxb, - HChar *(*handler)(const s390_opnd *, HChar *)) +s390_format_VRI_V0U(void (*irgen)(UChar v1, UShort i2), + UChar v1, UShort i2, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; } v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, i2); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, handler), VR(v1), UINT(i2)); + irgen(v1, i2); } static void -s390_format_VRI_V0UUU(const HChar *(*irgen)(UChar v1, UChar i2, UChar i3, - UChar m4), +s390_format_VRI_V0UUU(void (*irgen)(UChar v1, UChar i2, UChar i3, UChar m4), UChar v1, UChar i2, UChar i3, UChar m4, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; } v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, i2, i3, m4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), UINT(i2), UINT(i3), MASK(m4)); + irgen(v1, i2, i3, m4); } static void -s390_format_VRI_V0IU(const HChar *(*irgen)(UChar v1, UShort i2, UChar m3), +s390_format_VRI_V0IU(void (*irgen)(UChar v1, UShort i2, UChar m3), UChar v1, UShort i2, UChar m3, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; } v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, i2, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), INT((Short)i2), MASK(m3)); + irgen(v1, i2, m3); } static void -s390_format_VRI_VIM(const HChar *(*irgen)(UChar v1, UShort i2, UChar m3), +s390_format_VRI_VIM(void (*irgen)(UChar v1, UShort i2, UChar m3), UChar v1, UShort i2, UChar m3, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; } v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, i2, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), INT((Short)i2), UINT(m3)); + irgen(v1, i2, m3); } static void -s390_format_VRI_VVIM(const HChar *(*irgen)(UChar v1, UChar v3, UShort i2, UChar m4), - UChar v1, UChar v3, UShort i2, UChar m4, UChar rxb) +s390_format_VRI_VVIM(void (*irgen)(UChar v1, UChar v3, UShort i2, UChar m4), + UChar v1, UChar v3, UShort i2, UChar m4, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4039,20 +3671,15 @@ s390_format_VRI_VVIM(const HChar *(*irgen)(UChar v1, UChar v3, UShort i2, UChar v1 = s390_vr_getVRindex(v1, 1, rxb); v3 = s390_vr_getVRindex(v3, 2, rxb); - mnm = irgen(v1, v3, i2, m4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), VR(v3), UINT(i2), MASK(m4)); + irgen(v1, v3, i2, m4); } static void -s390_format_VRI_VVIMM(const HChar *(*irgen)(UChar v1, UChar v2, UShort i3, - UChar m4, UChar m5), +s390_format_VRI_VVIMM(void (*irgen)(UChar v1, UChar v2, UShort i3, + UChar m4, UChar m5), UChar v1, UChar v2, UShort i3, UChar m4, UChar m5, UChar rxb) { - const HChar *mnm; - if (!s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4060,18 +3687,14 @@ s390_format_VRI_VVIMM(const HChar *(*irgen)(UChar v1, UChar v2, UShort i3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); - mnm = irgen(v1, v2, i3, m4, m5); - - if (vex_traceflags & VEX_TRACE_FE) - S390_DISASM(XMNM(mnm, vfmix_like_disasm), VR(v1), VR(v2), UINT(i3), MASK(m4), MASK(m5)); + irgen(v1, v2, i3, m4, m5); } static void -s390_format_VRS_RRDVM(const HChar *(*irgen)(UChar r1, IRTemp op2addr, UChar v3, +s390_format_VRS_RRDVM(void (*irgen)(UChar r1, IRTemp op2addr, UChar v3, UChar m4), UChar r1, UChar b2, UShort d2, UChar v3, UChar m4, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4083,17 +3706,13 @@ s390_format_VRS_RRDVM(const HChar *(*irgen)(UChar r1, IRTemp op2addr, UChar v3, mkU64(0))); v3 = s390_vr_getVRindex(v3, 2, rxb); - mnm = irgen(r1, op2addr, v3, m4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), GPR(r1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); + irgen(r1, op2addr, v3, m4); } static void -s390_format_VRS_RRDV(const HChar *(*irgen)(UChar v1, UChar r3, IRTemp op2addr), +s390_format_VRS_RRDV(void (*irgen)(UChar v1, UChar r3, IRTemp op2addr), UChar v1, UChar r3, UChar b2, UShort d2, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4105,19 +3724,15 @@ s390_format_VRS_RRDV(const HChar *(*irgen)(UChar v1, UChar r3, IRTemp op2addr), mkU64(0))); v1 = s390_vr_getVRindex(v1, 4, rxb); - mnm = irgen(v1, r3, op2addr); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), GPR(r3), UDXB(d2, 0, b2)); + irgen(v1, r3, op2addr); } static void -s390_format_VRS_VRDVM(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar v3, +s390_format_VRS_VRDVM(void (*irgen)(UChar v1, IRTemp op2addr, UChar v3, UChar m4), UChar v1, UChar b2, UShort d2, UChar v3, UChar m4, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4130,18 +3745,14 @@ s390_format_VRS_VRDVM(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar v3, v1 = s390_vr_getVRindex(v1, 1, rxb); v3 = s390_vr_getVRindex(v3, 2, rxb); - mnm = irgen(v1, op2addr, v3, m4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); + irgen(v1, op2addr, v3, m4); } static void -s390_format_VRS_VRDV(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar v3), +s390_format_VRS_VRDV(void (*irgen)(UChar v1, IRTemp op2addr, UChar v3), UChar v1, UChar b2, UShort d2, UChar v3, UChar m4, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4154,19 +3765,15 @@ s390_format_VRS_VRDV(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar v3), v1 = s390_vr_getVRindex(v1, 1, rxb); v3 = s390_vr_getVRindex(v3, 2, rxb); - mnm = irgen(v1, op2addr, v3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, mask0_disasm), VR(v1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); + irgen(v1, op2addr, v3); } static void -s390_format_VRS_VRRDM(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar r3, - UChar m4), - UChar v1, UChar b2, UShort d2, UChar r3, UChar m4, UChar rxb) +s390_format_VRS_VRRDM(void (*irgen)(UChar v1, IRTemp op2addr, UChar r3, + UChar m4), + UChar v1, UChar b2, UShort d2, UChar r3, UChar m4, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4178,18 +3785,14 @@ s390_format_VRS_VRRDM(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar r3, mkU64(0))); v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, op2addr, r3, m4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), GPR(r3), UDXB(d2, 0, b2), MASK(m4)); + irgen(v1, op2addr, r3, m4); } static void -s390_format_VRS_VRRD(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar r3), +s390_format_VRS_VRRD(void (*irgen)(UChar v1, IRTemp op2addr, UChar r3), UChar v1, UChar b2, UShort d2, UChar r3, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4201,19 +3804,15 @@ s390_format_VRS_VRRD(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar r3), mkU64(0))); v1 = s390_vr_getVRindex(v1, 1, rxb); - mnm = irgen(v1, op2addr, r3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), GPR(r3), UDXB(d2, 0, b2)); + irgen(v1, op2addr, r3); } static void -s390_format_VRV_VVRDMT(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar m3), +s390_format_VRV_VVRDMT(void (*irgen)(UChar v1, IRTemp op2addr, UChar m3), UChar v1, UChar v2, UChar b2, UShort d2, UChar m3, UChar rxb, IRType type) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (! s390_host_has_vx) { @@ -4235,22 +3834,16 @@ s390_format_VRV_VVRDMT(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar m3) assign(op2addr, binop(Iop_Add64, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0)), x2)); - mnm = irgen(v1, op2addr, m3); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), UDVB(d2, v2, b2), UINT(m3)); + irgen(v1, op2addr, m3); } static void -s390_format_VRR_VVVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar v4, UChar m5, UChar m6), +s390_format_VRR_VVVVMM(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar v4, UChar m5, UChar m6), UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, - UChar m6, UChar rxb, - HChar *(*handler)(const s390_opnd *, HChar *)) + UChar m6, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4260,20 +3853,15 @@ s390_format_VRR_VVVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); v4 = s390_vr_getVRindex(v4, 4, rxb); - mnm = irgen(v1, v2, v3, v4, m5, m6); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, handler), VR(v1), VR(v2), VR(v3), VR(v4), MASK(m5), MASK(m6)); + irgen(v1, v2, v3, v4, m5, m6); } static void -s390_format_VRR_VVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3, - UChar m5), +s390_format_VRR_VVMM(void (*irgen)(UChar v1, UChar v2, UChar m3, + UChar m5), UChar v1, UChar v2, UChar m3, UChar m5, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4281,21 +3869,16 @@ s390_format_VRR_VVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); - mnm = irgen(v1, v2, m3, m5); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, vch_like_disasm), VR(v1), VR(v2), MASK(m3), MASK(m5)); + irgen(v1, v2, m3, m5); } static void -s390_format_VRId_VVVIM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar i4, UChar m5), +s390_format_VRId_VVVIM(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar i4, UChar m5), UChar v1, UChar v2, UChar v3, UChar i4, UChar m5, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4304,20 +3887,15 @@ s390_format_VRId_VVVIM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, i4, m5); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), VR(v2), VR(v3), UINT(i4), MASK(m5)); + irgen(v1, v2, v3, i4, m5); } static void -s390_format_VRId_VVVI(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar i4), +s390_format_VRId_VVVI(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar i4), UChar v1, UChar v2, UChar v3, UChar i4, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4326,21 +3904,16 @@ s390_format_VRId_VVVI(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, i4); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM(mnm), VR(v1), VR(v2), VR(v3), UINT(i4)); + irgen(v1, v2, v3, i4); } static void -s390_format_VRRd_VVVVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar v4, UChar m5), +s390_format_VRRd_VVVVM(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar v4, UChar m5), UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar rxb) { - const HChar *mnm; - if (! s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4350,21 +3923,16 @@ s390_format_VRRd_VVVVM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); v4 = s390_vr_getVRindex(v4, 4, rxb); - mnm = irgen(v1, v2, v3, v4, m5); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM(mnm, va_like_disasm), VR(v1), VR(v2), VR(v3), VR(v4), MASK(m5)); + irgen(v1, v2, v3, v4, m5); } static void -s390_format_VRRa_VVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3, - UChar m4, UChar m5), +s390_format_VRRa_VVMMM(void (*irgen)(UChar v1, UChar v2, UChar m3, + UChar m4, UChar m5), UChar v1, UChar v2, UChar m3, UChar m4, UChar m5, UChar rxb) { - const HChar *mnm; - if (!s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4372,36 +3940,15 @@ s390_format_VRRa_VVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); - mnm = irgen(v1, v2, m3, m4, m5); - - if (vex_traceflags & VEX_TRACE_FE) { - if (irgen == s390_irgen_VFLR) - S390_DISASM(XMNM(mnm, vflr_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), UINT(m5)); - else if (irgen == s390_irgen_VFI) - S390_DISASM(XMNM(mnm, vfi_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), UINT(m5)); - else if (irgen == s390_irgen_VFPSO) - S390_DISASM(XMNM(mnm, vfpso_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), MASK(m5)); - else if (irgen == s390_irgen_VCGD) - S390_DISASM(XMNM(mnm, vcgd_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), MASK(m5)); - else if (irgen == s390_irgen_VCDG) - S390_DISASM(XMNM(mnm, vcdg_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), MASK(m5)); - else if (irgen == s390_irgen_VCLGD) - S390_DISASM(XMNM(mnm, vclgd_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), MASK(m5)); - else if (irgen == s390_irgen_VCDLG) - S390_DISASM(XMNM(mnm, vcgld_disasm), VR(v1), VR(v2), MASK(m3), MASK(m4), MASK(m5)); - else - S390_DISASM(MNM(mnm), VR(v1), VR(v2), UINT(m3), UINT(m4), UINT(m5)); - } + irgen(v1, v2, m3, m4, m5); } static void -s390_format_VRRa_VVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar m4, UChar m5), +s390_format_VRRa_VVVMM(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar m4, UChar m5), UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, - UChar rxb, HChar *(*handler)(const s390_opnd *, HChar *)) + UChar rxb) { - const HChar *mnm; - if (!s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4410,24 +3957,14 @@ s390_format_VRRa_VVVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, m4, m5); - - if (vex_traceflags & VEX_TRACE_FE) { - if (handler) - S390_DISASM(XMNM(mnm, handler), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5)); - else - S390_DISASM(MNM(mnm), VR(v1), VR(v2), VR(v3), UINT(m4), UINT(m5)); - } + irgen(v1, v2, v3, m4, m5); } static void -s390_format_VRRa_VVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3, +s390_format_VRRa_VVMM(void (*irgen)(UChar v1, UChar v2, UChar m3, UChar m4), - UChar v1, UChar v2, UChar m3, UChar m4, UChar rxb, - HChar *(*handler)(const s390_opnd *, HChar *)) + UChar v1, UChar v2, UChar m3, UChar m4, UChar rxb) { - const HChar *mnm; - if (!s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4435,24 +3972,15 @@ s390_format_VRRa_VVMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar m3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); - mnm = irgen(v1, v2, m3, m4); - - if (vex_traceflags & VEX_TRACE_FE) { - if (handler) - S390_DISASM(XMNM(mnm, handler), VR(v1), VR(v2), MASK(m3), MASK(m4)); - else - S390_DISASM(MNM(mnm), VR(v1), VR(v2), UINT(m3), UINT(m4)); - } + irgen(v1, v2, m3, m4); } static void -s390_format_VRRa_VVVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar m4, UChar m5, UChar m6), +s390_format_VRRa_VVVMMM(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar m4, UChar m5, UChar m6), UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6, UChar rxb) { - const HChar *mnm; - if (!s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4461,21 +3989,16 @@ s390_format_VRRa_VVVMMM(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, m4, m5, m6); - - if (vex_traceflags & VEX_TRACE_FE) - S390_DISASM(XMNM(mnm, vfce_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5), MASK(m6)); + irgen(v1, v2, v3, m4, m5, m6); } static void -s390_format_VRRa_VVVMMM2(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, - UChar m4, UChar m5, UChar m6), +s390_format_VRRa_VVVMMM2(void (*irgen)(UChar v1, UChar v2, UChar v3, + UChar m4, UChar m5, UChar m6), UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6, UChar rxb) { - const HChar *mnm; - if (!s390_host_has_vx) { emulation_failure(EmFail_S390X_vx); return; @@ -4484,17 +4007,13 @@ s390_format_VRRa_VVVMMM2(const HChar *(*irgen)(UChar v1, UChar v2, UChar v3, v1 = s390_vr_getVRindex(v1, 1, rxb); v2 = s390_vr_getVRindex(v2, 2, rxb); v3 = s390_vr_getVRindex(v3, 3, rxb); - mnm = irgen(v1, v2, v3, m4, m5, m6); - - if (vex_traceflags & VEX_TRACE_FE) - S390_DISASM(XMNM(mnm, vfmix_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5), UINT(m6)); + irgen(v1, v2, v3, m4, m5, m6); } static void -s390_format_VSI_URDV(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar i3), +s390_format_VSI_URDV(void (*irgen)(UChar v1, IRTemp op2addr, UChar i3), UChar v1, UChar b2, UShort d2, UChar i3, UChar rxb) { - const HChar *mnm; IRTemp op2addr = newTemp(Ity_I64); if (!s390_host_has_vx) { @@ -4507,17 +4026,14 @@ s390_format_VSI_URDV(const HChar *(*irgen)(UChar v1, IRTemp op2addr, UChar i3), assign(op2addr, binop(Iop_Add64, mkU64(d2), b2 != 0 ? get_gpr_dw0(b2) : mkU64(0))); - mnm = irgen(v1, op2addr, i3); - - if (vex_traceflags & VEX_TRACE_FE) - S390_DISASM(MNM(mnm), VR(v1), UDXB(d2, 0, b2), UINT(i3)); + irgen(v1, op2addr, i3); } /*------------------------------------------------------------*/ /*--- Build IR for opcodes ---*/ /*------------------------------------------------------------*/ -static const HChar * +static void s390_irgen_AR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -4529,11 +4045,9 @@ s390_irgen_AR(UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "ar"; } -static const HChar * +static void s390_irgen_AGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -4545,11 +4059,9 @@ s390_irgen_AGR(UChar r1, UChar r2) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "agr"; } -static const HChar * +static void s390_irgen_AGFR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -4561,11 +4073,9 @@ s390_irgen_AGFR(UChar r1, UChar r2) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "agfr"; } -static const HChar * +static void s390_irgen_ARK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -4577,11 +4087,9 @@ s390_irgen_ARK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op2, op3); put_gpr_w1(r1, mkexpr(result)); - - return "ark"; } -static const HChar * +static void s390_irgen_AGRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -4593,11 +4101,9 @@ s390_irgen_AGRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add64, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op2, op3); put_gpr_dw0(r1, mkexpr(result)); - - return "agrk"; } -static const HChar * +static void s390_irgen_A(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -4609,11 +4115,9 @@ s390_irgen_A(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "a"; } -static const HChar * +static void s390_irgen_AY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -4625,11 +4129,9 @@ s390_irgen_AY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "ay"; } -static const HChar * +static void s390_irgen_AG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -4641,11 +4143,9 @@ s390_irgen_AG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "ag"; } -static const HChar * +static void s390_irgen_AGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -4657,11 +4157,9 @@ s390_irgen_AGF(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "agf"; } -static const HChar * +static void s390_irgen_AFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -4674,11 +4172,9 @@ s390_irgen_AFI(UChar r1, UInt i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32((UInt)op2))); put_gpr_w1(r1, mkexpr(result)); - - return "afi"; } -static const HChar * +static void s390_irgen_AGFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -4691,11 +4187,9 @@ s390_irgen_AGFI(UChar r1, UInt i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, mktemp(Ity_I64, mkU64((ULong)op2))); put_gpr_dw0(r1, mkexpr(result)); - - return "agfi"; } -static const HChar * +static void s390_irgen_AHIK(UChar r1, UChar r3, UShort i2) { Int op2; @@ -4708,11 +4202,9 @@ s390_irgen_AHIK(UChar r1, UChar r3, UShort i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, mktemp(Ity_I32, mkU32((UInt) op2)), op3); put_gpr_w1(r1, mkexpr(result)); - - return "ahik"; } -static const HChar * +static void s390_irgen_AGH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -4724,11 +4216,9 @@ s390_irgen_AGH(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "agh"; } -static const HChar * +static void s390_irgen_AGHIK(UChar r1, UChar r3, UShort i2) { Long op2; @@ -4741,11 +4231,9 @@ s390_irgen_AGHIK(UChar r1, UChar r3, UShort i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, mktemp(Ity_I64, mkU64((ULong) op2)), op3); put_gpr_dw0(r1, mkexpr(result)); - - return "aghik"; } -static const HChar * +static void s390_irgen_ASI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I32); @@ -4758,11 +4246,9 @@ s390_irgen_ASI(UChar i2, IRTemp op1addr) store(mkexpr(op1addr), mkexpr(result)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32((UInt)op2))); - - return "asi"; } -static const HChar * +static void s390_irgen_AGSI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I64); @@ -4775,11 +4261,9 @@ s390_irgen_AGSI(UChar i2, IRTemp op1addr) store(mkexpr(op1addr), mkexpr(result)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, mktemp(Ity_I64, mkU64((ULong)op2))); - - return "agsi"; } -static const HChar * +static void s390_irgen_AH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -4791,11 +4275,9 @@ s390_irgen_AH(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "ah"; } -static const HChar * +static void s390_irgen_AHY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -4807,11 +4289,9 @@ s390_irgen_AHY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "ahy"; } -static const HChar * +static void s390_irgen_AHI(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I32); @@ -4824,11 +4304,9 @@ s390_irgen_AHI(UChar r1, UShort i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32((UInt)op2))); put_gpr_w1(r1, mkexpr(result)); - - return "ahi"; } -static const HChar * +static void s390_irgen_AGHI(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I64); @@ -4841,11 +4319,9 @@ s390_irgen_AGHI(UChar r1, UShort i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_64, op1, mktemp(Ity_I64, mkU64((ULong)op2))); put_gpr_dw0(r1, mkexpr(result)); - - return "aghi"; } -static const HChar * +static void s390_irgen_AHHHR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -4857,11 +4333,9 @@ s390_irgen_AHHHR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "ahhhr"; } -static const HChar * +static void s390_irgen_AHHLR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -4873,11 +4347,9 @@ s390_irgen_AHHLR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "ahhlr"; } -static const HChar * +static void s390_irgen_AIH(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -4890,11 +4362,9 @@ s390_irgen_AIH(UChar r1, UInt i2) s390_cc_thunk_putSS(S390_CC_OP_SIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32((UInt)op2))); put_gpr_w0(r1, mkexpr(result)); - - return "aih"; } -static const HChar * +static void s390_irgen_ALR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -4906,11 +4376,9 @@ s390_irgen_ALR(UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "alr"; } -static const HChar * +static void s390_irgen_ALGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -4922,11 +4390,9 @@ s390_irgen_ALGR(UChar r1, UChar r2) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "algr"; } -static const HChar * +static void s390_irgen_ALGFR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -4938,11 +4404,9 @@ s390_irgen_ALGFR(UChar r1, UChar r2) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "algfr"; } -static const HChar * +static void s390_irgen_ALRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -4954,11 +4418,9 @@ s390_irgen_ALRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op2, op3); put_gpr_w1(r1, mkexpr(result)); - - return "alrk"; } -static const HChar * +static void s390_irgen_ALGRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -4970,11 +4432,9 @@ s390_irgen_ALGRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add64, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op2, op3); put_gpr_dw0(r1, mkexpr(result)); - - return "algrk"; } -static const HChar * +static void s390_irgen_AL(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -4986,11 +4446,9 @@ s390_irgen_AL(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "al"; } -static const HChar * +static void s390_irgen_ALY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5002,11 +4460,9 @@ s390_irgen_ALY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "aly"; } -static const HChar * +static void s390_irgen_ALG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5018,11 +4474,9 @@ s390_irgen_ALG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "alg"; } -static const HChar * +static void s390_irgen_ALGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5034,11 +4488,9 @@ s390_irgen_ALGF(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Add64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "algf"; } -static const HChar * +static void s390_irgen_ALFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -5051,11 +4503,9 @@ s390_irgen_ALFI(UChar r1, UInt i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32(op2))); put_gpr_w1(r1, mkexpr(result)); - - return "alfi"; } -static const HChar * +static void s390_irgen_ALGFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -5068,11 +4518,9 @@ s390_irgen_ALGFI(UChar r1, UInt i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op1, mktemp(Ity_I64, mkU64(op2))); put_gpr_dw0(r1, mkexpr(result)); - - return "algfi"; } -static const HChar * +static void s390_irgen_ALHHHR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -5084,11 +4532,9 @@ s390_irgen_ALHHHR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "alhhhr"; } -static const HChar * +static void s390_irgen_ALHHLR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -5100,11 +4546,9 @@ s390_irgen_ALHHLR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Add32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "alhhlr"; } -static const HChar * +static void s390_irgen_ALCR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -5119,11 +4563,9 @@ s390_irgen_ALCR(UChar r1, UChar r2) mkexpr(carry_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_ADDC_32, op1, op2, carry_in); put_gpr_w1(r1, mkexpr(result)); - - return "alcr"; } -static const HChar * +static void s390_irgen_ALCGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -5139,11 +4581,9 @@ s390_irgen_ALCGR(UChar r1, UChar r2) mkexpr(carry_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_ADDC_64, op1, op2, carry_in); put_gpr_dw0(r1, mkexpr(result)); - - return "alcgr"; } -static const HChar * +static void s390_irgen_ALC(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5158,11 +4598,9 @@ s390_irgen_ALC(UChar r1, IRTemp op2addr) mkexpr(carry_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_ADDC_32, op1, op2, carry_in); put_gpr_w1(r1, mkexpr(result)); - - return "alc"; } -static const HChar * +static void s390_irgen_ALCG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5178,11 +4616,9 @@ s390_irgen_ALCG(UChar r1, IRTemp op2addr) mkexpr(carry_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_ADDC_64, op1, op2, carry_in); put_gpr_dw0(r1, mkexpr(result)); - - return "alcg"; } -static const HChar * +static void s390_irgen_ALSI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5195,11 +4631,9 @@ s390_irgen_ALSI(UChar i2, IRTemp op1addr) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32(op2))); store(mkexpr(op1addr), mkexpr(result)); - - return "alsi"; } -static const HChar * +static void s390_irgen_ALGSI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5212,11 +4646,9 @@ s390_irgen_ALGSI(UChar i2, IRTemp op1addr) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, op1, mktemp(Ity_I64, mkU64(op2))); store(mkexpr(op1addr), mkexpr(result)); - - return "algsi"; } -static const HChar * +static void s390_irgen_ALHSIK(UChar r1, UChar r3, UShort i2) { UInt op2; @@ -5229,11 +4661,9 @@ s390_irgen_ALHSIK(UChar r1, UChar r3, UShort i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, mktemp(Ity_I32, mkU32(op2)), op3); put_gpr_w1(r1, mkexpr(result)); - - return "alhsik"; } -static const HChar * +static void s390_irgen_ALGHSIK(UChar r1, UChar r3, UShort i2) { ULong op2; @@ -5246,11 +4676,9 @@ s390_irgen_ALGHSIK(UChar r1, UChar r3, UShort i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_64, mktemp(Ity_I64, mkU64(op2)), op3); put_gpr_dw0(r1, mkexpr(result)); - - return "alghsik"; } -static const HChar * +static void s390_irgen_ALSIH(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -5263,11 +4691,9 @@ s390_irgen_ALSIH(UChar r1, UInt i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_ADD_32, op1, mktemp(Ity_I32, mkU32(op2))); put_gpr_w0(r1, mkexpr(result)); - - return "alsih"; } -static const HChar * +static void s390_irgen_ALSIHN(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -5278,11 +4704,9 @@ s390_irgen_ALSIHN(UChar r1, UInt i2) op2 = i2; assign(result, binop(Iop_Add32, mkexpr(op1), mkU32(op2))); put_gpr_w0(r1, mkexpr(result)); - - return "alsihn"; } -static const HChar * +static void s390_irgen_NR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -5294,11 +4718,9 @@ s390_irgen_NR(UChar r1, UChar r2) assign(result, binop(Iop_And32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "nr"; } -static const HChar * +static void s390_irgen_NGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -5310,16 +4732,14 @@ s390_irgen_NGR(UChar r1, UChar r2) assign(result, binop(Iop_And64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return "ngr"; } /* Helper for bitwise logical instructions with two 32-bit input operands and a 32-bit output operand. `inv3' and `inv' indicate whether to invert (build bitwise complement of) operand 3 or the result, respectively. */ -static const HChar * +static void s390_irgen_logicalK32(UChar r3, UChar r1, UChar r2, - const HChar *mnem, IROp op, Bool inv3, Bool inv) + IROp op, Bool inv3, Bool inv) { IRTemp op2 = newTemp(Ity_I32); IRTemp op3 = newTemp(Ity_I32); @@ -5332,14 +4752,12 @@ s390_irgen_logicalK32(UChar r3, UChar r1, UChar r2, assign(result, inv ? unop(Iop_Not32, tmp) : tmp); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return mnem; } /* Same as s390_irgen_logicalK32, but for 64-bit operands. */ -static const HChar * +static void s390_irgen_logicalK64(UChar r3, UChar r1, UChar r2, - const HChar *mnem, IROp op, Bool inv3, Bool inv) + IROp op, Bool inv3, Bool inv) { IRTemp op2 = newTemp(Ity_I64); IRTemp op3 = newTemp(Ity_I64); @@ -5352,47 +4770,45 @@ s390_irgen_logicalK64(UChar r3, UChar r1, UChar r2, assign(result, inv ? unop(Iop_Not64, tmp) : tmp); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return mnem; } -static const HChar * +static void s390_irgen_NRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "nrk", Iop_And32, False, False); + s390_irgen_logicalK32(r3, r1, r2, Iop_And32, False, False); } -static const HChar * +static void s390_irgen_NGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "ngrk", Iop_And64, False, False); + s390_irgen_logicalK64(r3, r1, r2, Iop_And64, False, False); } -static const HChar * +static void s390_irgen_NCRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "ncrk", Iop_And32, True, False); + s390_irgen_logicalK32(r3, r1, r2, Iop_And32, True, False); } -static const HChar * +static void s390_irgen_NCGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "ncgrk", Iop_And64, True, False); + s390_irgen_logicalK64(r3, r1, r2, Iop_And64, True, False); } -static const HChar * +static void s390_irgen_NNRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "nnrk", Iop_And32, False, True); + s390_irgen_logicalK32(r3, r1, r2, Iop_And32, False, True); } -static const HChar * +static void s390_irgen_NNGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "nngrk", Iop_And64, False, True); + s390_irgen_logicalK64(r3, r1, r2, Iop_And64, False, True); } -static const HChar * +static void s390_irgen_N(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5404,11 +4820,9 @@ s390_irgen_N(UChar r1, IRTemp op2addr) assign(result, binop(Iop_And32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "n"; } -static const HChar * +static void s390_irgen_NY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5420,11 +4834,9 @@ s390_irgen_NY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_And32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "ny"; } -static const HChar * +static void s390_irgen_NG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5436,11 +4848,9 @@ s390_irgen_NG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_And64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return "ng"; } -static const HChar * +static void s390_irgen_NI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -5452,11 +4862,9 @@ s390_irgen_NI(UChar i2, IRTemp op1addr) assign(result, binop(Iop_And8, mkexpr(op1), mkU8(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); store(mkexpr(op1addr), mkexpr(result)); - - return "ni"; } -static const HChar * +static void s390_irgen_NIY(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -5468,11 +4876,9 @@ s390_irgen_NIY(UChar i2, IRTemp op1addr) assign(result, binop(Iop_And8, mkexpr(op1), mkU8(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); store(mkexpr(op1addr), mkexpr(result)); - - return "niy"; } -static const HChar * +static void s390_irgen_NIHF(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -5484,11 +4890,9 @@ s390_irgen_NIHF(UChar r1, UInt i2) assign(result, binop(Iop_And32, mkexpr(op1), mkU32(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w0(r1, mkexpr(result)); - - return "nihf"; } -static const HChar * +static void s390_irgen_NIHH(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -5500,11 +4904,9 @@ s390_irgen_NIHH(UChar r1, UShort i2) assign(result, binop(Iop_And16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw0(r1, mkexpr(result)); - - return "nihh"; } -static const HChar * +static void s390_irgen_NIHL(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -5516,11 +4918,9 @@ s390_irgen_NIHL(UChar r1, UShort i2) assign(result, binop(Iop_And16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw1(r1, mkexpr(result)); - - return "nihl"; } -static const HChar * +static void s390_irgen_NILF(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -5532,11 +4932,9 @@ s390_irgen_NILF(UChar r1, UInt i2) assign(result, binop(Iop_And32, mkexpr(op1), mkU32(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "nilf"; } -static const HChar * +static void s390_irgen_NILH(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -5548,11 +4946,9 @@ s390_irgen_NILH(UChar r1, UShort i2) assign(result, binop(Iop_And16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw2(r1, mkexpr(result)); - - return "nilh"; } -static const HChar * +static void s390_irgen_NILL(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -5564,11 +4960,9 @@ s390_irgen_NILL(UChar r1, UShort i2) assign(result, binop(Iop_And16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw3(r1, mkexpr(result)); - - return "nill"; } -static const HChar * +static void s390_irgen_BASR(UChar r1, UChar r2) { IRTemp target = newTemp(Ity_I64); @@ -5585,11 +4979,9 @@ s390_irgen_BASR(UChar r1, UChar r2) call_function(mkexpr(target)); } } - - return "basr"; } -static const HChar * +static void s390_irgen_BAS(UChar r1, IRTemp op2addr) { IRTemp target = newTemp(Ity_I64); @@ -5597,11 +4989,9 @@ s390_irgen_BAS(UChar r1, IRTemp op2addr) put_gpr_dw0(r1, mkU64(guest_IA_next_instr)); assign(target, mkexpr(op2addr)); call_function(mkexpr(target)); - - return "bas"; } -static const HChar * +static void s390_irgen_BCR(UChar m1, UChar r2) { IRTemp cond = newTemp(Ity_I32); @@ -5620,13 +5010,9 @@ s390_irgen_BCR(UChar m1, UChar r2) get_gpr_dw0(r2)); } } - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM("bcr", bcr_disasm), MASK(m1), GPR(r2)); - - return "bcr"; } -static const HChar * +static void s390_irgen_BC(UChar m1, UChar x2, UChar b2, UShort d2, IRTemp op2addr) { IRTemp cond = newTemp(Ity_I32); @@ -5641,13 +5027,9 @@ s390_irgen_BC(UChar m1, UChar x2, UChar b2, UShort d2, IRTemp op2addr) mkexpr(op2addr)); } } - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM("bc", bc_disasm), MASK(m1), UDXB(d2, x2, b2)); - - return "bc"; } -static const HChar * +static void s390_irgen_BCTR(UChar r1, UChar r2) { put_gpr_w1(r1, binop(Iop_Sub32, get_gpr_w1(r1), mkU32(1))); @@ -5655,11 +5037,9 @@ s390_irgen_BCTR(UChar r1, UChar r2) if_condition_goto_computed(binop(Iop_CmpNE32, get_gpr_w1(r1), mkU32(0)), get_gpr_dw0(r2)); } - - return "bctr"; } -static const HChar * +static void s390_irgen_BCTGR(UChar r1, UChar r2) { put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1))); @@ -5667,31 +5047,25 @@ s390_irgen_BCTGR(UChar r1, UChar r2) if_condition_goto_computed(binop(Iop_CmpNE64, get_gpr_dw0(r1), mkU64(0)), get_gpr_dw0(r2)); } - - return "bctgr"; } -static const HChar * +static void s390_irgen_BCT(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, binop(Iop_Sub32, get_gpr_w1(r1), mkU32(1))); if_condition_goto_computed(binop(Iop_CmpNE32, get_gpr_w1(r1), mkU32(0)), mkexpr(op2addr)); - - return "bct"; } -static const HChar * +static void s390_irgen_BCTG(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1))); if_condition_goto_computed(binop(Iop_CmpNE64, get_gpr_dw0(r1), mkU64(0)), mkexpr(op2addr)); - - return "bctg"; } -static const HChar * +static void s390_irgen_BIC(UChar r1, IRTemp op2addr) { IRTemp cond = newTemp(Ity_I32); @@ -5705,11 +5079,9 @@ s390_irgen_BIC(UChar r1, IRTemp op2addr) if_condition_goto_computed(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), load(Ity_I64, mkexpr(op2addr))); } - - return "bic"; } -static const HChar * +static void s390_irgen_BXH(UChar r1, UChar r3, IRTemp op2addr) { IRTemp value = newTemp(Ity_I32); @@ -5718,11 +5090,9 @@ s390_irgen_BXH(UChar r1, UChar r3, IRTemp op2addr) put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3))); if_condition_goto_computed(binop(Iop_CmpLT32S, mkexpr(value), get_gpr_w1(r1)), mkexpr(op2addr)); - - return "bxh"; } -static const HChar * +static void s390_irgen_BXHG(UChar r1, UChar r3, IRTemp op2addr) { IRTemp value = newTemp(Ity_I64); @@ -5731,11 +5101,9 @@ s390_irgen_BXHG(UChar r1, UChar r3, IRTemp op2addr) put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3))); if_condition_goto_computed(binop(Iop_CmpLT64S, mkexpr(value), get_gpr_dw0(r1)), mkexpr(op2addr)); - - return "bxhg"; } -static const HChar * +static void s390_irgen_BXLE(UChar r1, UChar r3, IRTemp op2addr) { IRTemp value = newTemp(Ity_I32); @@ -5744,11 +5112,9 @@ s390_irgen_BXLE(UChar r1, UChar r3, IRTemp op2addr) put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3))); if_condition_goto_computed(binop(Iop_CmpLE32S, get_gpr_w1(r1), mkexpr(value)), mkexpr(op2addr)); - - return "bxle"; } -static const HChar * +static void s390_irgen_BXLEG(UChar r1, UChar r3, IRTemp op2addr) { IRTemp value = newTemp(Ity_I64); @@ -5757,29 +5123,23 @@ s390_irgen_BXLEG(UChar r1, UChar r3, IRTemp op2addr) put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3))); if_condition_goto_computed(binop(Iop_CmpLE64S, get_gpr_dw0(r1), mkexpr(value)), mkexpr(op2addr)); - - return "bxleg"; } -static const HChar * +static void s390_irgen_BRAS(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64(guest_IA_next_instr)); call_function(mkaddr_expr(addr_relative(i2))); - - return "bras"; } -static const HChar * +static void s390_irgen_BRASL(UChar r1, UInt i2) { put_gpr_dw0(r1, mkU64(guest_IA_next_instr)); call_function(mkaddr_expr(addr_rel_long(i2))); - - return "brasl"; } -static const HChar * +static void s390_irgen_BRC(UChar m1, UShort i2) { IRTemp cond = newTemp(Ity_I32); @@ -5795,13 +5155,9 @@ s390_irgen_BRC(UChar m1, UShort i2) } } - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM("brc", brc_disasm), MASK(m1), PCREL((Int)(Short)i2)); - - return "brc"; } -static const HChar * +static void s390_irgen_BRCL(UChar m1, UInt i2) { IRTemp cond = newTemp(Ity_I32); @@ -5816,43 +5172,33 @@ s390_irgen_BRCL(UChar m1, UInt i2) addr_rel_long(i2)); } } - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(XMNM("brcl", brcl_disasm), MASK(m1), PCREL(i2)); - - return "brcl"; } -static const HChar * +static void s390_irgen_BRCT(UChar r1, UShort i2) { put_gpr_w1(r1, binop(Iop_Sub32, get_gpr_w1(r1), mkU32(1))); if_condition_goto(binop(Iop_CmpNE32, get_gpr_w1(r1), mkU32(0)), addr_relative(i2)); - - return "brct"; } -static const HChar * +static void s390_irgen_BRCTH(UChar r1, UInt i2) { put_gpr_w0(r1, binop(Iop_Sub32, get_gpr_w0(r1), mkU32(1))); if_condition_goto(binop(Iop_CmpNE32, get_gpr_w0(r1), mkU32(0)), addr_relative(i2)); - - return "brcth"; } -static const HChar * +static void s390_irgen_BRCTG(UChar r1, UShort i2) { put_gpr_dw0(r1, binop(Iop_Sub64, get_gpr_dw0(r1), mkU64(1))); if_condition_goto(binop(Iop_CmpNE64, get_gpr_dw0(r1), mkU64(0)), addr_relative(i2)); - - return "brctg"; } -static const HChar * +static void s390_irgen_BRXH(UChar r1, UChar r3, UShort i2) { IRTemp value = newTemp(Ity_I32); @@ -5861,11 +5207,9 @@ s390_irgen_BRXH(UChar r1, UChar r3, UShort i2) put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3))); if_condition_goto(binop(Iop_CmpLT32S, mkexpr(value), get_gpr_w1(r1)), addr_relative(i2)); - - return "brxh"; } -static const HChar * +static void s390_irgen_BRXHG(UChar r1, UChar r3, UShort i2) { IRTemp value = newTemp(Ity_I64); @@ -5874,11 +5218,9 @@ s390_irgen_BRXHG(UChar r1, UChar r3, UShort i2) put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3))); if_condition_goto(binop(Iop_CmpLT64S, mkexpr(value), get_gpr_dw0(r1)), addr_relative(i2)); - - return "brxhg"; } -static const HChar * +static void s390_irgen_BRXLE(UChar r1, UChar r3, UShort i2) { IRTemp value = newTemp(Ity_I32); @@ -5887,11 +5229,9 @@ s390_irgen_BRXLE(UChar r1, UChar r3, UShort i2) put_gpr_w1(r1, binop(Iop_Add32, get_gpr_w1(r1), get_gpr_w1(r3))); if_condition_goto(binop(Iop_CmpLE32S, get_gpr_w1(r1), mkexpr(value)), addr_relative(i2)); - - return "brxle"; } -static const HChar * +static void s390_irgen_BRXLG(UChar r1, UChar r3, UShort i2) { IRTemp value = newTemp(Ity_I64); @@ -5900,11 +5240,9 @@ s390_irgen_BRXLG(UChar r1, UChar r3, UShort i2) put_gpr_dw0(r1, binop(Iop_Add64, get_gpr_dw0(r1), get_gpr_dw0(r3))); if_condition_goto(binop(Iop_CmpLE64S, get_gpr_dw0(r1), mkexpr(value)), addr_relative(i2)); - - return "brxlg"; } -static const HChar * +static void s390_irgen_CR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -5913,11 +5251,9 @@ s390_irgen_CR(UChar r1, UChar r2) assign(op1, get_gpr_w1(r1)); assign(op2, get_gpr_w1(r2)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cr"; } -static const HChar * +static void s390_irgen_CGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -5926,11 +5262,9 @@ s390_irgen_CGR(UChar r1, UChar r2) assign(op1, get_gpr_dw0(r1)); assign(op2, get_gpr_dw0(r2)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cgr"; } -static const HChar * +static void s390_irgen_CGFR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -5939,11 +5273,9 @@ s390_irgen_CGFR(UChar r1, UChar r2) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_32Sto64, get_gpr_w1(r2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cgfr"; } -static const HChar * +static void s390_irgen_C(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5952,11 +5284,9 @@ s390_irgen_C(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w1(r1)); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "c"; } -static const HChar * +static void s390_irgen_CY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -5965,11 +5295,9 @@ s390_irgen_CY(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w1(r1)); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cy"; } -static const HChar * +static void s390_irgen_CG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5978,11 +5306,9 @@ s390_irgen_CG(UChar r1, IRTemp op2addr) assign(op1, get_gpr_dw0(r1)); assign(op2, load(Ity_I64, mkexpr(op2addr))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cg"; } -static const HChar * +static void s390_irgen_CGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -5991,11 +5317,9 @@ s390_irgen_CGF(UChar r1, IRTemp op2addr) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_32Sto64, load(Ity_I32, mkexpr(op2addr)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cgf"; } -static const HChar * +static void s390_irgen_CFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6005,11 +5329,9 @@ s390_irgen_CFI(UChar r1, UInt i2) op2 = (Int)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32((UInt)op2))); - - return "cfi"; } -static const HChar * +static void s390_irgen_CGFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6019,11 +5341,9 @@ s390_irgen_CGFI(UChar r1, UInt i2) op2 = (Long)(Int)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64((ULong)op2))); - - return "cgfi"; } -static const HChar * +static void s390_irgen_CRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6032,11 +5352,9 @@ s390_irgen_CRL(UChar r1, UInt i2) assign(op1, get_gpr_w1(r1)); assign(op2, load(Ity_I32, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "crl"; } -static const HChar * +static void s390_irgen_CGRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6045,11 +5363,9 @@ s390_irgen_CGRL(UChar r1, UInt i2) assign(op1, get_gpr_dw0(r1)); assign(op2, load(Ity_I64, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cgrl"; } -static const HChar * +static void s390_irgen_CGFRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6058,11 +5374,9 @@ s390_irgen_CGFRL(UChar r1, UInt i2) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_32Sto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cgfrl"; } -static const HChar * +static void s390_irgen_CRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6082,11 +5396,9 @@ s390_irgen_CRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) mkU32(0)), mkexpr(op4addr)); } } - - return "crb"; } -static const HChar * +static void s390_irgen_CGRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6106,11 +5418,9 @@ s390_irgen_CGRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) mkU32(0)), mkexpr(op4addr)); } } - - return "cgrb"; } -static const HChar * +static void s390_irgen_CRJ(UChar r1, UChar r2, UShort i4, UChar m3) { IRTemp op1 = newTemp(Ity_I32); @@ -6128,14 +5438,11 @@ s390_irgen_CRJ(UChar r1, UChar r2, UShort i4, UChar m3) op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "crj"; } -static const HChar * +static void s390_irgen_CGRJ(UChar r1, UChar r2, UShort i4, UChar m3) { IRTemp op1 = newTemp(Ity_I64); @@ -6153,14 +5460,11 @@ s390_irgen_CGRJ(UChar r1, UChar r2, UShort i4, UChar m3) op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "cgrj"; } -static const HChar * +static void s390_irgen_CIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6180,11 +5484,9 @@ s390_irgen_CIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) mkexpr(op4addr)); } } - - return "cib"; } -static const HChar * +static void s390_irgen_CGIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6204,11 +5506,9 @@ s390_irgen_CGIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) mkexpr(op4addr)); } } - - return "cgib"; } -static const HChar * +static void s390_irgen_CIJ(UChar r1, UChar m3, UShort i4, UChar i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6226,14 +5526,11 @@ s390_irgen_CIJ(UChar r1, UChar m3, UShort i4, UChar i2) mktemp(Ity_I32, mkU32((UInt)op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "cij"; } -static const HChar * +static void s390_irgen_CGIJ(UChar r1, UChar m3, UShort i4, UChar i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6251,14 +5548,11 @@ s390_irgen_CGIJ(UChar r1, UChar m3, UShort i4, UChar i2) mktemp(Ity_I64, mkU64((ULong)op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "cgij"; } -static const HChar * +static void s390_irgen_CH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6267,11 +5561,9 @@ s390_irgen_CH(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w1(r1)); assign(op2, unop(Iop_16Sto32, load(Ity_I16, mkexpr(op2addr)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "ch"; } -static const HChar * +static void s390_irgen_CHY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6280,11 +5572,9 @@ s390_irgen_CHY(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w1(r1)); assign(op2, unop(Iop_16Sto32, load(Ity_I16, mkexpr(op2addr)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "chy"; } -static const HChar * +static void s390_irgen_CGH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6293,11 +5583,9 @@ s390_irgen_CGH(UChar r1, IRTemp op2addr) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_16Sto64, load(Ity_I16, mkexpr(op2addr)))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cgh"; } -static const HChar * +static void s390_irgen_CHI(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6307,11 +5595,9 @@ s390_irgen_CHI(UChar r1, UShort i2) op2 = (Int)(Short)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32((UInt)op2))); - - return "chi"; } -static const HChar * +static void s390_irgen_CGHI(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6321,11 +5607,9 @@ s390_irgen_CGHI(UChar r1, UShort i2) op2 = (Long)(Short)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64((ULong)op2))); - - return "cghi"; } -static const HChar * +static void s390_irgen_CHHSI(UShort i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I16); @@ -6335,11 +5619,9 @@ s390_irgen_CHHSI(UShort i2, IRTemp op1addr) op2 = (Short)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I16, mkU16((UShort)op2))); - - return "chhsi"; } -static const HChar * +static void s390_irgen_CHSI(UShort i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6349,11 +5631,9 @@ s390_irgen_CHSI(UShort i2, IRTemp op1addr) op2 = (Int)(Short)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32((UInt)op2))); - - return "chsi"; } -static const HChar * +static void s390_irgen_CGHSI(UShort i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6363,11 +5643,9 @@ s390_irgen_CGHSI(UShort i2, IRTemp op1addr) op2 = (Long)(Short)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64((ULong)op2))); - - return "cghsi"; } -static const HChar * +static void s390_irgen_CHRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6376,11 +5654,9 @@ s390_irgen_CHRL(UChar r1, UInt i2) assign(op1, get_gpr_w1(r1)); assign(op2, unop(Iop_16Sto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "chrl"; } -static const HChar * +static void s390_irgen_CGHRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6389,11 +5665,9 @@ s390_irgen_CGHRL(UChar r1, UInt i2) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_16Sto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "cghrl"; } -static const HChar * +static void s390_irgen_CHHR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -6402,11 +5676,9 @@ s390_irgen_CHHR(UChar r1, UChar r2) assign(op1, get_gpr_w0(r1)); assign(op2, get_gpr_w0(r2)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "chhr"; } -static const HChar * +static void s390_irgen_CHLR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -6415,11 +5687,9 @@ s390_irgen_CHLR(UChar r1, UChar r2) assign(op1, get_gpr_w0(r1)); assign(op2, get_gpr_w1(r2)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "chlr"; } -static const HChar * +static void s390_irgen_CHF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6428,11 +5698,9 @@ s390_irgen_CHF(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w0(r1)); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "chf"; } -static const HChar * +static void s390_irgen_CIH(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6442,11 +5710,9 @@ s390_irgen_CIH(UChar r1, UInt i2) op2 = (Int)i2; s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32((UInt)op2))); - - return "cih"; } -static const HChar * +static void s390_irgen_CLR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -6455,11 +5721,9 @@ s390_irgen_CLR(UChar r1, UChar r2) assign(op1, get_gpr_w1(r1)); assign(op2, get_gpr_w1(r2)); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clr"; } -static const HChar * +static void s390_irgen_CLGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -6468,11 +5732,9 @@ s390_irgen_CLGR(UChar r1, UChar r2) assign(op1, get_gpr_dw0(r1)); assign(op2, get_gpr_dw0(r2)); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clgr"; } -static const HChar * +static void s390_irgen_CLGFR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -6481,11 +5743,9 @@ s390_irgen_CLGFR(UChar r1, UChar r2) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_32Uto64, get_gpr_w1(r2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clgfr"; } -static const HChar * +static void s390_irgen_CL(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6494,11 +5754,9 @@ s390_irgen_CL(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w1(r1)); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "cl"; } -static const HChar * +static void s390_irgen_CLY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6507,11 +5765,9 @@ s390_irgen_CLY(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w1(r1)); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "cly"; } -static const HChar * +static void s390_irgen_CLG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6520,11 +5776,9 @@ s390_irgen_CLG(UChar r1, IRTemp op2addr) assign(op1, get_gpr_dw0(r1)); assign(op2, load(Ity_I64, mkexpr(op2addr))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clg"; } -static const HChar * +static void s390_irgen_CLGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6533,11 +5787,9 @@ s390_irgen_CLGF(UChar r1, IRTemp op2addr) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_32Uto64, load(Ity_I32, mkexpr(op2addr)))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clgf"; } -static const HChar * +static void s390_irgen_CLFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6547,11 +5799,9 @@ s390_irgen_CLFI(UChar r1, UInt i2) op2 = i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32(op2))); - - return "clfi"; } -static const HChar * +static void s390_irgen_CLGFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6561,11 +5811,9 @@ s390_irgen_CLGFI(UChar r1, UInt i2) op2 = (ULong)i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64(op2))); - - return "clgfi"; } -static const HChar * +static void s390_irgen_CLI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -6575,11 +5823,9 @@ s390_irgen_CLI(UChar i2, IRTemp op1addr) op2 = i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I8, mkU8(op2))); - - return "cli"; } -static const HChar * +static void s390_irgen_CLIY(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -6589,11 +5835,9 @@ s390_irgen_CLIY(UChar i2, IRTemp op1addr) op2 = i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I8, mkU8(op2))); - - return "cliy"; } -static const HChar * +static void s390_irgen_CLFHSI(UShort i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6603,11 +5847,9 @@ s390_irgen_CLFHSI(UShort i2, IRTemp op1addr) op2 = (UInt)i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32(op2))); - - return "clfhsi"; } -static const HChar * +static void s390_irgen_CLGHSI(UShort i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6617,11 +5859,9 @@ s390_irgen_CLGHSI(UShort i2, IRTemp op1addr) op2 = (ULong)i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I64, mkU64(op2))); - - return "clghsi"; } -static const HChar * +static void s390_irgen_CLHHSI(UShort i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I16); @@ -6631,11 +5871,9 @@ s390_irgen_CLHHSI(UShort i2, IRTemp op1addr) op2 = i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I16, mkU16(op2))); - - return "clhhsi"; } -static const HChar * +static void s390_irgen_CLRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6644,11 +5882,9 @@ s390_irgen_CLRL(UChar r1, UInt i2) assign(op1, get_gpr_w1(r1)); assign(op2, load(Ity_I32, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clrl"; } -static const HChar * +static void s390_irgen_CLGRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6657,11 +5893,9 @@ s390_irgen_CLGRL(UChar r1, UInt i2) assign(op1, get_gpr_dw0(r1)); assign(op2, load(Ity_I64, mkU64(addr_rel_long(i2)))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clgrl"; } -static const HChar * +static void s390_irgen_CLGFRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6670,11 +5904,9 @@ s390_irgen_CLGFRL(UChar r1, UInt i2) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_32Uto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clgfrl"; } -static const HChar * +static void s390_irgen_CLHRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -6683,11 +5915,9 @@ s390_irgen_CLHRL(UChar r1, UInt i2) assign(op1, get_gpr_w1(r1)); assign(op2, unop(Iop_16Uto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clhrl"; } -static const HChar * +static void s390_irgen_CLGHRL(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -6696,11 +5926,9 @@ s390_irgen_CLGHRL(UChar r1, UInt i2) assign(op1, get_gpr_dw0(r1)); assign(op2, unop(Iop_16Uto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clghrl"; } -static const HChar * +static void s390_irgen_CLRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I32); @@ -6720,11 +5948,9 @@ s390_irgen_CLRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) mkexpr(op4addr)); } } - - return "clrb"; } -static const HChar * +static void s390_irgen_CLGRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I64); @@ -6744,8 +5970,6 @@ s390_irgen_CLGRB(UChar r1, UChar r2, UChar m3, IRTemp op4addr) mkexpr(op4addr)); } } - - return "clgrb"; } /* Raise the appropriate signal for a compare-and-trap-instruction data @@ -6781,32 +6005,28 @@ s390_irgen_CxRT(UChar m3, UChar r1, UChar r2, IRType type, UInt opc) s390_trap_on_condition(cond); } -static const HChar * +static void s390_irgen_CGRT(UChar m3, UChar r1, UChar r2) { s390_irgen_CxRT(m3, r1, r2, Ity_I64, S390_CC_OP_SIGNED_COMPARE); - return "cgrt"; } -static const HChar * +static void s390_irgen_CRT(UChar m3, UChar r1, UChar r2) { s390_irgen_CxRT(m3, r1, r2, Ity_I32, S390_CC_OP_SIGNED_COMPARE); - return "crt"; } -static const HChar * +static void s390_irgen_CLGRT(UChar m3, UChar r1, UChar r2) { s390_irgen_CxRT(m3, r1, r2, Ity_I64, S390_CC_OP_UNSIGNED_COMPARE); - return "clgrt"; } -static const HChar * +static void s390_irgen_CLRT(UChar m3, UChar r1, UChar r2) { s390_irgen_CxRT(m3, r1, r2, Ity_I32, S390_CC_OP_UNSIGNED_COMPARE); - return "clrt"; } /* Handle the various flavors of compare (logical) immediate and trap. */ @@ -6839,32 +6059,28 @@ s390_irgen_CxIT(UChar m3, UChar r1, UShort i2, IRType type, UInt opc) s390_trap_on_condition(cond); } -static const HChar * +static void s390_irgen_CGIT(UChar r1, UShort i2, UChar m3) { s390_irgen_CxIT(m3, r1, i2, Ity_I64, S390_CC_OP_SIGNED_COMPARE); - return "cgit"; } -static const HChar * +static void s390_irgen_CIT(UChar r1, UShort i2, UChar m3) { s390_irgen_CxIT(m3, r1, i2, Ity_I32, S390_CC_OP_SIGNED_COMPARE); - return "cit"; } -static const HChar * +static void s390_irgen_CLGIT(UChar r1, UShort i2, UChar m3) { s390_irgen_CxIT(m3, r1, i2, Ity_I64, S390_CC_OP_UNSIGNED_COMPARE); - return "clgit"; } -static const HChar * +static void s390_irgen_CLFIT(UChar r1, UShort i2, UChar m3) { s390_irgen_CxIT(m3, r1, i2, Ity_I32, S390_CC_OP_UNSIGNED_COMPARE); - return "clfit"; } /* Handle the variants of compare logical and trap with memory operand. */ @@ -6891,61 +6107,55 @@ s390_irgen_CLxT(UChar r1, UChar m3, IRTemp op2addr, IRType type, UInt opc) s390_trap_on_condition(cond); } -static const HChar * +static void s390_irgen_CLT(UChar r1, UChar m3, IRTemp op2addr) { s390_irgen_CLxT(r1, m3, op2addr, Ity_I32, S390_CC_OP_UNSIGNED_COMPARE); - return "clt"; } -static const HChar * +static void s390_irgen_CLGT(UChar r1, UChar m3, IRTemp op2addr) { s390_irgen_CLxT(r1, m3, op2addr, Ity_I64, S390_CC_OP_UNSIGNED_COMPARE); - return "clgt"; } -static const HChar * +static void s390_irgen_LAT(UChar r1, IRTemp op2addr) { IRTemp val = newTemp(Ity_I32); assign(val, load(Ity_I32, mkexpr(op2addr))); put_gpr_w1(r1, mkexpr(val)); s390_trap_on_condition(binop(Iop_CmpEQ32, mkexpr(val), mkU32(0))); - return "lat"; } -static const HChar * +static void s390_irgen_LGAT(UChar r1, IRTemp op2addr) { IRTemp val = newTemp(Ity_I64); assign(val, load(Ity_I64, mkexpr(op2addr))); put_gpr_dw0(r1, mkexpr(val)); s390_trap_on_condition(binop(Iop_CmpEQ64, mkexpr(val), mkU64(0))); - return "lgat"; } -static const HChar * +static void s390_irgen_LFHAT(UChar r1, IRTemp op2addr) { IRTemp val = newTemp(Ity_I32); assign(val, load(Ity_I32, mkexpr(op2addr))); put_gpr_w0(r1, mkexpr(val)); s390_trap_on_condition(binop(Iop_CmpEQ32, mkexpr(val), mkU32(0))); - return "lfhat"; } -static const HChar * +static void s390_irgen_LLGFAT(UChar r1, IRTemp op2addr) { IRTemp val = newTemp(Ity_I64); assign(val, unop(Iop_32Uto64, load(Ity_I32, mkexpr(op2addr)))); put_gpr_dw0(r1, mkexpr(val)); s390_trap_on_condition(binop(Iop_CmpEQ64, mkexpr(val), mkU64(0))); - return "llgfat"; } -static const HChar * +static void s390_irgen_LLGTAT(UChar r1, IRTemp op2addr) { IRTemp val = newTemp(Ity_I64); @@ -6953,10 +6163,9 @@ s390_irgen_LLGTAT(UChar r1, IRTemp op2addr) unop(Iop_32Uto64, load(Ity_I32, mkexpr(op2addr))))); put_gpr_dw0(r1, mkexpr(val)); s390_trap_on_condition(binop(Iop_CmpEQ64, mkexpr(val), mkU64(0))); - return "llgtat"; } -static const HChar * +static void s390_irgen_CLRJ(UChar r1, UChar r2, UShort i4, UChar m3) { IRTemp op1 = newTemp(Ity_I32); @@ -6974,14 +6183,11 @@ s390_irgen_CLRJ(UChar r1, UChar r2, UShort i4, UChar m3) op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "clrj"; } -static const HChar * +static void s390_irgen_CLGRJ(UChar r1, UChar r2, UShort i4, UChar m3) { IRTemp op1 = newTemp(Ity_I64); @@ -6999,14 +6205,11 @@ s390_irgen_CLGRJ(UChar r1, UChar r2, UShort i4, UChar m3) op1, op2)); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "clgrj"; } -static const HChar * +static void s390_irgen_CLIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7026,11 +6229,9 @@ s390_irgen_CLIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) mkexpr(op4addr)); } } - - return "clib"; } -static const HChar * +static void s390_irgen_CLGIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) { IRTemp op1 = newTemp(Ity_I64); @@ -7050,11 +6251,9 @@ s390_irgen_CLGIB(UChar r1, UChar m3, UChar i2, IRTemp op4addr) mkexpr(op4addr)); } } - - return "clgib"; } -static const HChar * +static void s390_irgen_CLIJ(UChar r1, UChar m3, UShort i4, UChar i2) { IRTemp op1 = newTemp(Ity_I32); @@ -7072,14 +6271,11 @@ s390_irgen_CLIJ(UChar r1, UChar m3, UShort i4, UChar i2) mktemp(Ity_I32, mkU32(op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "clij"; } -static const HChar * +static void s390_irgen_CLGIJ(UChar r1, UChar m3, UShort i4, UChar i2) { IRTemp op1 = newTemp(Ity_I64); @@ -7097,14 +6293,11 @@ s390_irgen_CLGIJ(UChar r1, UChar m3, UShort i4, UChar i2) mktemp(Ity_I64, mkU64(op2)))); if_condition_goto(binop(Iop_CmpNE32, mkexpr(cond), mkU32(0)), addr_relative(i4)); - } } - - return "clgij"; } -static const HChar * +static void s390_irgen_CLM(UChar r1, UChar r3, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7162,11 +6355,9 @@ s390_irgen_CLM(UChar r1, UChar r3, IRTemp op2addr) mkexpr(c0), mkU8(24)), binop(Iop_Shl32, mkexpr(c1), mkU8(16))), binop(Iop_Shl32, mkexpr(c2), mkU8(8))), mkexpr(c3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clm"; } -static const HChar * +static void s390_irgen_CLMY(UChar r1, UChar r3, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7224,11 +6415,9 @@ s390_irgen_CLMY(UChar r1, UChar r3, IRTemp op2addr) mkexpr(c0), mkU8(24)), binop(Iop_Shl32, mkexpr(c1), mkU8(16))), binop(Iop_Shl32, mkexpr(c2), mkU8(8))), mkexpr(c3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clmy"; } -static const HChar * +static void s390_irgen_CLMH(UChar r1, UChar r3, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7286,11 +6475,9 @@ s390_irgen_CLMH(UChar r1, UChar r3, IRTemp op2addr) mkexpr(c0), mkU8(24)), binop(Iop_Shl32, mkexpr(c1), mkU8(16))), binop(Iop_Shl32, mkexpr(c2), mkU8(8))), mkexpr(c3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clmh"; } -static const HChar * +static void s390_irgen_CLHHR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -7299,11 +6486,9 @@ s390_irgen_CLHHR(UChar r1, UChar r2) assign(op1, get_gpr_w0(r1)); assign(op2, get_gpr_w0(r2)); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clhhr"; } -static const HChar * +static void s390_irgen_CLHLR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -7312,11 +6497,9 @@ s390_irgen_CLHLR(UChar r1, UChar r2) assign(op1, get_gpr_w0(r1)); assign(op2, get_gpr_w1(r2)); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clhlr"; } -static const HChar * +static void s390_irgen_CLHF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7325,11 +6508,9 @@ s390_irgen_CLHF(UChar r1, IRTemp op2addr) assign(op1, get_gpr_w0(r1)); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "clhf"; } -static const HChar * +static void s390_irgen_CLIH(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -7339,21 +6520,15 @@ s390_irgen_CLIH(UChar r1, UInt i2) op2 = i2; s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, mktemp(Ity_I32, mkU32(op2))); - - return "clih"; } -static const HChar * +static void s390_irgen_CPYA(UChar r1, UChar r2) { put_ar_w0(r1, get_ar_w0(r2)); - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM("cpya"), AR(r1), AR(r2)); - - return "cpya"; } -static const HChar * +static void s390_irgen_XR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -7369,11 +6544,9 @@ s390_irgen_XR(UChar r1, UChar r2) } s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "xr"; } -static const HChar * +static void s390_irgen_XGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -7389,35 +6562,33 @@ s390_irgen_XGR(UChar r1, UChar r2) } s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return "xgr"; } -static const HChar * +static void s390_irgen_XRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "xrk", Iop_Xor32, False, False); + s390_irgen_logicalK32(r3, r1, r2, Iop_Xor32, False, False); } -static const HChar * +static void s390_irgen_XGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "xgrk", Iop_Xor64, False, False); + s390_irgen_logicalK64(r3, r1, r2, Iop_Xor64, False, False); } -static const HChar * +static void s390_irgen_NXRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "nxrk", Iop_Xor32, False, True); + s390_irgen_logicalK32(r3, r1, r2, Iop_Xor32, False, True); } -static const HChar * +static void s390_irgen_NXGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "nxgrk", Iop_Xor64, False, True); + s390_irgen_logicalK64(r3, r1, r2, Iop_Xor64, False, True); } -static const HChar * +static void s390_irgen_X(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7429,11 +6600,9 @@ s390_irgen_X(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Xor32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "x"; } -static const HChar * +static void s390_irgen_XY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -7445,11 +6614,9 @@ s390_irgen_XY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Xor32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "xy"; } -static const HChar * +static void s390_irgen_XG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -7461,11 +6628,9 @@ s390_irgen_XG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Xor64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return "xg"; } -static const HChar * +static void s390_irgen_XI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -7477,11 +6642,9 @@ s390_irgen_XI(UChar i2, IRTemp op1addr) assign(result, binop(Iop_Xor8, mkexpr(op1), mkU8(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); store(mkexpr(op1addr), mkexpr(result)); - - return "xi"; } -static const HChar * +static void s390_irgen_XIY(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -7493,11 +6656,9 @@ s390_irgen_XIY(UChar i2, IRTemp op1addr) assign(result, binop(Iop_Xor8, mkexpr(op1), mkU8(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); store(mkexpr(op1addr), mkexpr(result)); - - return "xiy"; } -static const HChar * +static void s390_irgen_XIHF(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -7509,11 +6670,9 @@ s390_irgen_XIHF(UChar r1, UInt i2) assign(result, binop(Iop_Xor32, mkexpr(op1), mkU32(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w0(r1, mkexpr(result)); - - return "xihf"; } -static const HChar * +static void s390_irgen_XILF(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -7525,37 +6684,27 @@ s390_irgen_XILF(UChar r1, UInt i2) assign(result, binop(Iop_Xor32, mkexpr(op1), mkU32(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "xilf"; } -static const HChar * +static void s390_irgen_EAR(UChar r1, UChar r2) { put_gpr_w1(r1, get_ar_w0(r2)); - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM("ear"), GPR(r1), AR(r2)); - - return "ear"; } -static const HChar * +static void s390_irgen_IC(UChar r1, IRTemp op2addr) { put_gpr_b7(r1, load(Ity_I8, mkexpr(op2addr))); - - return "ic"; } -static const HChar * +static void s390_irgen_ICY(UChar r1, IRTemp op2addr) { put_gpr_b7(r1, load(Ity_I8, mkexpr(op2addr))); - - return "icy"; } -static const HChar * +static void s390_irgen_ICM(UChar r1, UChar r3, IRTemp op2addr) { UChar n; @@ -7586,11 +6735,9 @@ s390_irgen_ICM(UChar r1, UChar r3, IRTemp op2addr) assign(result, get_gpr_w1(r1)); s390_cc_thunk_putZZ(S390_CC_OP_INSERT_CHAR_MASK_32, result, mktemp(Ity_I32, mkU32(mask))); - - return "icm"; } -static const HChar * +static void s390_irgen_ICMY(UChar r1, UChar r3, IRTemp op2addr) { UChar n; @@ -7621,11 +6768,9 @@ s390_irgen_ICMY(UChar r1, UChar r3, IRTemp op2addr) assign(result, get_gpr_w1(r1)); s390_cc_thunk_putZZ(S390_CC_OP_INSERT_CHAR_MASK_32, result, mktemp(Ity_I32, mkU32(mask))); - - return "icmy"; } -static const HChar * +static void s390_irgen_ICMH(UChar r1, UChar r3, IRTemp op2addr) { UChar n; @@ -7656,184 +6801,138 @@ s390_irgen_ICMH(UChar r1, UChar r3, IRTemp op2addr) assign(result, get_gpr_w0(r1)); s390_cc_thunk_putZZ(S390_CC_OP_INSERT_CHAR_MASK_32, result, mktemp(Ity_I32, mkU32(mask))); - - return "icmh"; } -static const HChar * +static void s390_irgen_IIHF(UChar r1, UInt i2) { put_gpr_w0(r1, mkU32(i2)); - - return "iihf"; } -static const HChar * +static void s390_irgen_IIHH(UChar r1, UShort i2) { put_gpr_hw0(r1, mkU16(i2)); - - return "iihh"; } -static const HChar * +static void s390_irgen_IIHL(UChar r1, UShort i2) { put_gpr_hw1(r1, mkU16(i2)); - - return "iihl"; } -static const HChar * +static void s390_irgen_IILF(UChar r1, UInt i2) { put_gpr_w1(r1, mkU32(i2)); - - return "iilf"; } -static const HChar * +static void s390_irgen_IILH(UChar r1, UShort i2) { put_gpr_hw2(r1, mkU16(i2)); - - return "iilh"; } -static const HChar * +static void s390_irgen_IILL(UChar r1, UShort i2) { put_gpr_hw3(r1, mkU16(i2)); - - return "iill"; } -static const HChar * +static void s390_irgen_LR(UChar r1, UChar r2) { put_gpr_w1(r1, get_gpr_w1(r2)); - - return "lr"; } -static const HChar * +static void s390_irgen_LGR(UChar r1, UChar r2) { put_gpr_dw0(r1, get_gpr_dw0(r2)); - - return "lgr"; } -static const HChar * +static void s390_irgen_LGFR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_32Sto64, get_gpr_w1(r2))); - - return "lgfr"; } -static const HChar * +static void s390_irgen_L(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, load(Ity_I32, mkexpr(op2addr))); - - return "l"; } -static const HChar * +static void s390_irgen_LY(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, load(Ity_I32, mkexpr(op2addr))); - - return "ly"; } -static const HChar * +static void s390_irgen_LG(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, load(Ity_I64, mkexpr(op2addr))); - - return "lg"; } -static const HChar * +static void s390_irgen_LGF(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_32Sto64, load(Ity_I32, mkexpr(op2addr)))); - - return "lgf"; } -static const HChar * +static void s390_irgen_LGFI(UChar r1, UInt i2) { put_gpr_dw0(r1, mkU64((ULong)(Long)(Int)i2)); - - return "lgfi"; } -static const HChar * +static void s390_irgen_LRL(UChar r1, UInt i2) { put_gpr_w1(r1, load(Ity_I32, mkU64(addr_rel_long(i2)))); - - return "lrl"; } -static const HChar * +static void s390_irgen_LGRL(UChar r1, UInt i2) { put_gpr_dw0(r1, load(Ity_I64, mkU64(addr_rel_long(i2)))); - - return "lgrl"; } -static const HChar * +static void s390_irgen_LGFRL(UChar r1, UInt i2) { put_gpr_dw0(r1, unop(Iop_32Sto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); - - return "lgfrl"; } -static const HChar * +static void s390_irgen_LA(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, mkexpr(op2addr)); - - return "la"; } -static const HChar * +static void s390_irgen_LAY(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, mkexpr(op2addr)); - - return "lay"; } -static const HChar * +static void s390_irgen_LAE(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, mkexpr(op2addr)); - - return "lae"; } -static const HChar * +static void s390_irgen_LAEY(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, mkexpr(op2addr)); - - return "laey"; } -static const HChar * +static void s390_irgen_LARL(UChar r1, UInt i2) { put_gpr_dw0(r1, mkU64(addr_rel_long(i2))); - - return "larl"; } /* The IR representation of LAA and friends is an approximation of what @@ -7969,87 +7068,67 @@ s390_irgen_load_and_bitwise64(UChar r1, UChar r3, IRTemp op2addr, IROp op) put_gpr_dw0(r1, mkexpr(old_mem)); } -static const HChar * +static void s390_irgen_LAA(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_add32(r1, r3, op2addr, True /* is_signed */); - - return "laa"; } -static const HChar * +static void s390_irgen_LAAG(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_add64(r1, r3, op2addr, True /* is_signed */); - - return "laag"; } -static const HChar * +static void s390_irgen_LAAL(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_add32(r1, r3, op2addr, False /* is_signed */); - - return "laal"; } -static const HChar * +static void s390_irgen_LAALG(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_add64(r1, r3, op2addr, False /* is_signed */); - - return "laalg"; } -static const HChar * +static void s390_irgen_LAN(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_bitwise32(r1, r3, op2addr, Iop_And32); - - return "lan"; } -static const HChar * +static void s390_irgen_LANG(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_bitwise64(r1, r3, op2addr, Iop_And64); - - return "lang"; } -static const HChar * +static void s390_irgen_LAX(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_bitwise32(r1, r3, op2addr, Iop_Xor32); - - return "lax"; } -static const HChar * +static void s390_irgen_LAXG(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_bitwise64(r1, r3, op2addr, Iop_Xor64); - - return "laxg"; } -static const HChar * +static void s390_irgen_LAO(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_bitwise32(r1, r3, op2addr, Iop_Or32); - - return "lao"; } -static const HChar * +static void s390_irgen_LAOG(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_and_bitwise64(r1, r3, op2addr, Iop_Or64); - - return "laog"; } -static const HChar * +static void s390_irgen_LTR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -8057,11 +7136,9 @@ s390_irgen_LTR(UChar r1, UChar r2) assign(op2, get_gpr_w1(r2)); put_gpr_w1(r1, mkexpr(op2)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); - - return "ltr"; } -static const HChar * +static void s390_irgen_LTGR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -8069,11 +7146,9 @@ s390_irgen_LTGR(UChar r1, UChar r2) assign(op2, get_gpr_dw0(r2)); put_gpr_dw0(r1, mkexpr(op2)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); - - return "ltgr"; } -static const HChar * +static void s390_irgen_LTGFR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -8081,11 +7156,9 @@ s390_irgen_LTGFR(UChar r1, UChar r2) assign(op2, unop(Iop_32Sto64, get_gpr_w1(r2))); put_gpr_dw0(r1, mkexpr(op2)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); - - return "ltgfr"; } -static const HChar * +static void s390_irgen_LT(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I32); @@ -8093,11 +7166,9 @@ s390_irgen_LT(UChar r1, IRTemp op2addr) assign(op2, load(Ity_I32, mkexpr(op2addr))); put_gpr_w1(r1, mkexpr(op2)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); - - return "lt"; } -static const HChar * +static void s390_irgen_LTG(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I64); @@ -8105,11 +7176,9 @@ s390_irgen_LTG(UChar r1, IRTemp op2addr) assign(op2, load(Ity_I64, mkexpr(op2addr))); put_gpr_dw0(r1, mkexpr(op2)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); - - return "ltg"; } -static const HChar * +static void s390_irgen_LTGF(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I64); @@ -8117,51 +7186,39 @@ s390_irgen_LTGF(UChar r1, IRTemp op2addr) assign(op2, unop(Iop_32Sto64, load(Ity_I32, mkexpr(op2addr)))); put_gpr_dw0(r1, mkexpr(op2)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, op2); - - return "ltgf"; } -static const HChar * +static void s390_irgen_LBR(UChar r1, UChar r2) { put_gpr_w1(r1, unop(Iop_8Sto32, get_gpr_b7(r2))); - - return "lbr"; } -static const HChar * +static void s390_irgen_LGBR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_8Sto64, get_gpr_b7(r2))); - - return "lgbr"; } -static const HChar * +static void s390_irgen_LB(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, unop(Iop_8Sto32, load(Ity_I8, mkexpr(op2addr)))); - - return "lb"; } -static const HChar * +static void s390_irgen_LGB(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_8Sto64, load(Ity_I8, mkexpr(op2addr)))); - - return "lgb"; } -static const HChar * +static void s390_irgen_LBH(UChar r1, IRTemp op2addr) { put_gpr_w0(r1, unop(Iop_8Sto32, load(Ity_I8, mkexpr(op2addr)))); - - return "lbh"; } -static const HChar * +static void s390_irgen_LCR(UChar r1, UChar r2) { Int op1; @@ -8174,11 +7231,9 @@ s390_irgen_LCR(UChar r1, UChar r2) put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, mktemp(Ity_I32, mkU32((UInt) op1)), op2); - - return "lcr"; } -static const HChar * +static void s390_irgen_LCGR(UChar r1, UChar r2) { Long op1; @@ -8191,11 +7246,9 @@ s390_irgen_LCGR(UChar r1, UChar r2) put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, mktemp(Ity_I64, mkU64((ULong) op1)), op2); - - return "lcgr"; } -static const HChar * +static void s390_irgen_LCGFR(UChar r1, UChar r2) { Long op1; @@ -8208,285 +7261,215 @@ s390_irgen_LCGFR(UChar r1, UChar r2) put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, mktemp(Ity_I64, mkU64((ULong) op1)), op2); - - return "lcgfr"; } -static const HChar * +static void s390_irgen_LHR(UChar r1, UChar r2) { put_gpr_w1(r1, unop(Iop_16Sto32, get_gpr_hw3(r2))); - - return "lhr"; } -static const HChar * +static void s390_irgen_LGHR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_16Sto64, get_gpr_hw3(r2))); - - return "lghr"; } -static const HChar * +static void s390_irgen_LH(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, unop(Iop_16Sto32, load(Ity_I16, mkexpr(op2addr)))); - - return "lh"; } -static const HChar * +static void s390_irgen_LHY(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, unop(Iop_16Sto32, load(Ity_I16, mkexpr(op2addr)))); - - return "lhy"; } -static const HChar * +static void s390_irgen_LGH(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_16Sto64, load(Ity_I16, mkexpr(op2addr)))); - - return "lgh"; } -static const HChar * +static void s390_irgen_LHI(UChar r1, UShort i2) { put_gpr_w1(r1, mkU32((UInt)(Int)(Short)i2)); - - return "lhi"; } -static const HChar * +static void s390_irgen_LGHI(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64((ULong)(Long)(Short)i2)); - - return "lghi"; } -static const HChar * +static void s390_irgen_LHRL(UChar r1, UInt i2) { put_gpr_w1(r1, unop(Iop_16Sto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); - - return "lhrl"; } -static const HChar * +static void s390_irgen_LGHRL(UChar r1, UInt i2) { put_gpr_dw0(r1, unop(Iop_16Sto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); - - return "lghrl"; } -static const HChar * +static void s390_irgen_LHH(UChar r1, IRTemp op2addr) { put_gpr_w0(r1, unop(Iop_16Sto32, load(Ity_I16, mkexpr(op2addr)))); - - return "lhh"; } -static const HChar * +static void s390_irgen_LFH(UChar r1, IRTemp op2addr) { put_gpr_w0(r1, load(Ity_I32, mkexpr(op2addr))); - - return "lfh"; } -static const HChar * +static void s390_irgen_LLGFR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_32Uto64, get_gpr_w1(r2))); - - return "llgfr"; } -static const HChar * +static void s390_irgen_LLGF(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_32Uto64, load(Ity_I32, mkexpr(op2addr)))); - - return "llgf"; } -static const HChar * +static void s390_irgen_LLGFRL(UChar r1, UInt i2) { put_gpr_dw0(r1, unop(Iop_32Uto64, load(Ity_I32, mkU64(addr_rel_long(i2))))); - - return "llgfrl"; } -static const HChar * +static void s390_irgen_LLCR(UChar r1, UChar r2) { put_gpr_w1(r1, unop(Iop_8Uto32, get_gpr_b7(r2))); - - return "llcr"; } -static const HChar * +static void s390_irgen_LLGCR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_8Uto64, get_gpr_b7(r2))); - - return "llgcr"; } -static const HChar * +static void s390_irgen_LLC(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, unop(Iop_8Uto32, load(Ity_I8, mkexpr(op2addr)))); - - return "llc"; } -static const HChar * +static void s390_irgen_LLGC(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_8Uto64, load(Ity_I8, mkexpr(op2addr)))); - - return "llgc"; } -static const HChar * +static void s390_irgen_LLCH(UChar r1, IRTemp op2addr) { put_gpr_w0(r1, unop(Iop_8Uto32, load(Ity_I8, mkexpr(op2addr)))); - - return "llch"; } -static const HChar * +static void s390_irgen_LLHR(UChar r1, UChar r2) { put_gpr_w1(r1, unop(Iop_16Uto32, get_gpr_hw3(r2))); - - return "llhr"; } -static const HChar * +static void s390_irgen_LLGHR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_16Uto64, get_gpr_hw3(r2))); - - return "llghr"; } -static const HChar * +static void s390_irgen_LLH(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(op2addr)))); - - return "llh"; } -static const HChar * +static void s390_irgen_LLGH(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_16Uto64, load(Ity_I16, mkexpr(op2addr)))); - - return "llgh"; } -static const HChar * +static void s390_irgen_LLHRL(UChar r1, UInt i2) { put_gpr_w1(r1, unop(Iop_16Uto32, load(Ity_I16, mkU64(addr_rel_long(i2))))); - - return "llhrl"; } -static const HChar * +static void s390_irgen_LLGHRL(UChar r1, UInt i2) { put_gpr_dw0(r1, unop(Iop_16Uto64, load(Ity_I16, mkU64(addr_rel_long(i2))))); - - return "llghrl"; } -static const HChar * +static void s390_irgen_LLHH(UChar r1, IRTemp op2addr) { put_gpr_w0(r1, unop(Iop_16Uto32, load(Ity_I16, mkexpr(op2addr)))); - - return "llhh"; } -static const HChar * +static void s390_irgen_LLIHF(UChar r1, UInt i2) { put_gpr_dw0(r1, mkU64(((ULong)i2) << 32)); - - return "llihf"; } -static const HChar * +static void s390_irgen_LLIHH(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64(((ULong)i2) << 48)); - - return "llihh"; } -static const HChar * +static void s390_irgen_LLIHL(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64(((ULong)i2) << 32)); - - return "llihl"; } -static const HChar * +static void s390_irgen_LLILF(UChar r1, UInt i2) { put_gpr_dw0(r1, mkU64(i2)); - - return "llilf"; } -static const HChar * +static void s390_irgen_LLILH(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64(((ULong)i2) << 16)); - - return "llilh"; } -static const HChar * +static void s390_irgen_LLILL(UChar r1, UShort i2) { put_gpr_dw0(r1, mkU64(i2)); - - return "llill"; } -static const HChar * +static void s390_irgen_LLGTR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_32Uto64, binop(Iop_And32, get_gpr_w1(r2), mkU32(2147483647)))); - - return "llgtr"; } -static const HChar * +static void s390_irgen_LLGT(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, unop(Iop_32Uto64, binop(Iop_And32, load(Ity_I32, mkexpr(op2addr)), mkU32(2147483647)))); - - return "llgt"; } -static const HChar * +static void s390_irgen_LNR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -8497,11 +7480,9 @@ s390_irgen_LNR(UChar r1, UChar r2) binop(Iop_Sub32, mkU32(0), mkexpr(op2)))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_BITWISE, result); - - return "lnr"; } -static const HChar * +static void s390_irgen_LNGR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -8512,11 +7493,9 @@ s390_irgen_LNGR(UChar r1, UChar r2) binop(Iop_Sub64, mkU64(0), mkexpr(op2)))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_BITWISE, result); - - return "lngr"; } -static const HChar * +static void s390_irgen_LNGFR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -8527,59 +7506,47 @@ s390_irgen_LNGFR(UChar r1, UChar r2) binop(Iop_Sub64, mkU64(0), mkexpr(op2)))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_BITWISE, result); - - return "lngfr"; } -static const HChar * +static void s390_irgen_LOCR(UChar m3, UChar r1, UChar r2) { next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0))); put_gpr_w1(r1, get_gpr_w1(r2)); - - return "locr"; } -static const HChar * +static void s390_irgen_LOCGR(UChar m3, UChar r1, UChar r2) { next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0))); put_gpr_dw0(r1, get_gpr_dw0(r2)); - - return "locgr"; } -static const HChar * +static void s390_irgen_LOC(UChar r1, IRTemp op2addr) { /* condition is checked in format handler */ put_gpr_w1(r1, load(Ity_I32, mkexpr(op2addr))); - - return "loc"; } -static const HChar * +static void s390_irgen_LOCG(UChar r1, IRTemp op2addr) { /* condition is checked in format handler */ put_gpr_dw0(r1, load(Ity_I64, mkexpr(op2addr))); - - return "locg"; } -static const HChar * +static void s390_irgen_LPQ(UChar r1, IRTemp op2addr) { - s390_insn_assert("lpq", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); put_gpr_dw0(r1, load(Ity_I64, mkexpr(op2addr))); put_gpr_dw0(r1 + 1, load(Ity_I64, binop(Iop_Add64, mkexpr(op2addr), mkU64(8)) )); - - return "lpq"; } -static const HChar * +static void s390_irgen_LPR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -8590,11 +7557,9 @@ s390_irgen_LPR(UChar r1, UChar r2) binop(Iop_Sub32, mkU32(0), mkexpr(op2)), mkexpr(op2))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_LOAD_POSITIVE_32, op2); - - return "lpr"; } -static const HChar * +static void s390_irgen_LPGR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -8605,11 +7570,9 @@ s390_irgen_LPGR(UChar r1, UChar r2) binop(Iop_Sub64, mkU64(0), mkexpr(op2)), mkexpr(op2))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_LOAD_POSITIVE_64, op2); - - return "lpgr"; } -static const HChar * +static void s390_irgen_LPGFR(UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -8620,11 +7583,9 @@ s390_irgen_LPGFR(UChar r1, UChar r2) binop(Iop_Sub64, mkU64(0), mkexpr(op2)), mkexpr(op2))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_LOAD_POSITIVE_64, op2); - - return "lpgfr"; } -static const HChar * +static void s390_irgen_LRVR(UChar r1, UChar r2) { IRTemp b0 = newTemp(Ity_I8); @@ -8640,11 +7601,9 @@ s390_irgen_LRVR(UChar r1, UChar r2) put_gpr_b5(r1, mkexpr(b2)); put_gpr_b6(r1, mkexpr(b1)); put_gpr_b7(r1, mkexpr(b0)); - - return "lrvr"; } -static const HChar * +static void s390_irgen_LRVGR(UChar r1, UChar r2) { IRTemp b0 = newTemp(Ity_I8); @@ -8672,11 +7631,9 @@ s390_irgen_LRVGR(UChar r1, UChar r2) put_gpr_b5(r1, mkexpr(b2)); put_gpr_b6(r1, mkexpr(b1)); put_gpr_b7(r1, mkexpr(b0)); - - return "lrvgr"; } -static const HChar * +static void s390_irgen_LRVH(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I16); @@ -8684,11 +7641,9 @@ s390_irgen_LRVH(UChar r1, IRTemp op2addr) assign(op2, load(Ity_I16, mkexpr(op2addr))); put_gpr_b6(r1, unop(Iop_16to8, mkexpr(op2))); put_gpr_b7(r1, unop(Iop_16HIto8, mkexpr(op2))); - - return "lrvh"; } -static const HChar * +static void s390_irgen_LRV(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I32); @@ -8701,11 +7656,9 @@ s390_irgen_LRV(UChar r1, IRTemp op2addr) mkU8(16)), mkU32(255)))); put_gpr_b7(r1, unop(Iop_32to8, binop(Iop_And32, binop(Iop_Shr32, mkexpr(op2), mkU8(24)), mkU32(255)))); - - return "lrv"; } -static const HChar * +static void s390_irgen_LRVG(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I64); @@ -8726,54 +7679,42 @@ s390_irgen_LRVG(UChar r1, IRTemp op2addr) mkU8(48)), mkU64(255)))); put_gpr_b7(r1, unop(Iop_64to8, binop(Iop_And64, binop(Iop_Shr64, mkexpr(op2), mkU8(56)), mkU64(255)))); - - return "lrvg"; } -static const HChar * +static void s390_irgen_MVHHI(UShort i2, IRTemp op1addr) { store(mkexpr(op1addr), mkU16(i2)); - - return "mvhhi"; } -static const HChar * +static void s390_irgen_MVHI(UShort i2, IRTemp op1addr) { store(mkexpr(op1addr), mkU32((UInt)(Int)(Short)i2)); - - return "mvhi"; } -static const HChar * +static void s390_irgen_MVGHI(UShort i2, IRTemp op1addr) { store(mkexpr(op1addr), mkU64((ULong)(Long)(Short)i2)); - - return "mvghi"; } -static const HChar * +static void s390_irgen_MVI(UChar i2, IRTemp op1addr) { store(mkexpr(op1addr), mkU8(i2)); - - return "mvi"; } -static const HChar * +static void s390_irgen_MVIY(UChar i2, IRTemp op1addr) { store(mkexpr(op1addr), mkU8(i2)); - - return "mviy"; } -static const HChar * +static void s390_irgen_MR(UChar r1, UChar r2) { - s390_insn_assert("mr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I32); IRTemp op2 = newTemp(Ity_I32); @@ -8784,14 +7725,12 @@ s390_irgen_MR(UChar r1, UChar r2) assign(result, binop(Iop_MullS32, mkexpr(op1), mkexpr(op2))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "mr"; } -static const HChar * +static void s390_irgen_M(UChar r1, IRTemp op2addr) { - s390_insn_assert("m", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I32); IRTemp op2 = newTemp(Ity_I32); @@ -8802,14 +7741,12 @@ s390_irgen_M(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullS32, mkexpr(op1), mkexpr(op2))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "m"; } -static const HChar * +static void s390_irgen_MFY(UChar r1, IRTemp op2addr) { - s390_insn_assert("mfy", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I32); IRTemp op2 = newTemp(Ity_I32); @@ -8820,14 +7757,12 @@ s390_irgen_MFY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullS32, mkexpr(op1), mkexpr(op2))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "mfy"; } -static const HChar * +static void s390_irgen_MG(UChar r1, IRTemp op2addr) { - s390_insn_assert("mg", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I64); IRTemp op2 = newTemp(Ity_I64); @@ -8838,11 +7773,9 @@ s390_irgen_MG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullS64, mkexpr(op1), mkexpr(op2))); put_gpr_dw0(r1, unop(Iop_128HIto64, mkexpr(result))); put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); - - return "mg"; } -static const HChar * +static void s390_irgen_MGH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -8854,14 +7787,12 @@ s390_irgen_MGH(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullS64, mkexpr(op1), unop(Iop_16Sto64, mkexpr(op2)) )); put_gpr_dw0(r1, unop(Iop_128to64, mkexpr(result))); - - return "mgh"; } -static const HChar * +static void s390_irgen_MGRK(UChar r3, UChar r1, UChar r2) { - s390_insn_assert("mgrk", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); IRTemp op3 = newTemp(Ity_I64); @@ -8872,11 +7803,9 @@ s390_irgen_MGRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_MullS64, mkexpr(op2), mkexpr(op3))); put_gpr_dw0(r1, unop(Iop_128HIto64, mkexpr(result))); put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); - - return "mgrk"; } -static const HChar * +static void s390_irgen_MH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -8888,11 +7817,9 @@ s390_irgen_MH(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullS32, mkexpr(op1), unop(Iop_16Sto32, mkexpr(op2)) )); put_gpr_w1(r1, unop(Iop_64to32, mkexpr(result))); - - return "mh"; } -static const HChar * +static void s390_irgen_MHY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -8904,11 +7831,9 @@ s390_irgen_MHY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullS32, mkexpr(op1), unop(Iop_16Sto32, mkexpr(op2)) )); put_gpr_w1(r1, unop(Iop_64to32, mkexpr(result))); - - return "mhy"; } -static const HChar * +static void s390_irgen_MHI(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I32); @@ -8920,11 +7845,9 @@ s390_irgen_MHI(UChar r1, UShort i2) assign(result, binop(Iop_MullS32, mkexpr(op1), unop(Iop_16Sto32, mkU16((UShort)op2)))); put_gpr_w1(r1, unop(Iop_64to32, mkexpr(result))); - - return "mhi"; } -static const HChar * +static void s390_irgen_MGHI(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I64); @@ -8936,14 +7859,12 @@ s390_irgen_MGHI(UChar r1, UShort i2) assign(result, binop(Iop_MullS64, mkexpr(op1), unop(Iop_16Sto64, mkU16((UShort)op2)))); put_gpr_dw0(r1, unop(Iop_128to64, mkexpr(result))); - - return "mghi"; } -static const HChar * +static void s390_irgen_MLR(UChar r1, UChar r2) { - s390_insn_assert("mlr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I32); IRTemp op2 = newTemp(Ity_I32); @@ -8954,14 +7875,12 @@ s390_irgen_MLR(UChar r1, UChar r2) assign(result, binop(Iop_MullU32, mkexpr(op1), mkexpr(op2))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "mlr"; } -static const HChar * +static void s390_irgen_MLGR(UChar r1, UChar r2) { - s390_insn_assert("mlgr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I64); IRTemp op2 = newTemp(Ity_I64); @@ -8972,14 +7891,12 @@ s390_irgen_MLGR(UChar r1, UChar r2) assign(result, binop(Iop_MullU64, mkexpr(op1), mkexpr(op2))); put_gpr_dw0(r1, unop(Iop_128HIto64, mkexpr(result))); put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); - - return "mlgr"; } -static const HChar * +static void s390_irgen_ML(UChar r1, IRTemp op2addr) { - s390_insn_assert("ml", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I32); IRTemp op2 = newTemp(Ity_I32); @@ -8990,14 +7907,12 @@ s390_irgen_ML(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullU32, mkexpr(op1), mkexpr(op2))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "ml"; } -static const HChar * +static void s390_irgen_MLG(UChar r1, IRTemp op2addr) { - s390_insn_assert("mlg", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op1 = newTemp(Ity_I64); IRTemp op2 = newTemp(Ity_I64); @@ -9008,45 +7923,35 @@ s390_irgen_MLG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_MullU64, mkexpr(op1), mkexpr(op2))); put_gpr_dw0(r1, unop(Iop_128HIto64, mkexpr(result))); put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); - - return "mlg"; } -static const HChar * +static void s390_irgen_MSR(UChar r1, UChar r2) { put_gpr_w1(r1, binop(Iop_Mul32, get_gpr_w1(r1), get_gpr_w1(r2))); - - return "msr"; } -static const HChar * +static void s390_irgen_MSGR(UChar r1, UChar r2) { put_gpr_dw0(r1, binop(Iop_Mul64, get_gpr_dw0(r1), get_gpr_dw0(r2))); - - return "msgr"; } -static const HChar * +static void s390_irgen_MSGFR(UChar r1, UChar r2) { put_gpr_dw0( r1, binop(Iop_Mul64, get_gpr_dw0(r1), unop(Iop_32Sto64, get_gpr_w1(r2)))); - - return "msgfr"; } -static const HChar * +static void s390_irgen_MS(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, binop(Iop_Mul32, get_gpr_w1(r1), load(Ity_I32, mkexpr(op2addr)))); - - return "ms"; } -static const HChar * +static void s390_irgen_MSC(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -9056,11 +7961,9 @@ s390_irgen_MSC(UChar r1, IRTemp op2addr) assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_cc_thunk_putSS(S390_CC_OP_MUL_32, op1, op2); put_gpr_w1(r1, binop(Iop_Mul32, mkexpr(op1), mkexpr(op2))); - - return "msc"; } -static const HChar * +static void s390_irgen_MSRKC(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -9070,29 +7973,23 @@ s390_irgen_MSRKC(UChar r3, UChar r1, UChar r2) assign(op3, get_gpr_w1(r3)); s390_cc_thunk_putSS(S390_CC_OP_MUL_32, op2, op3); put_gpr_w1(r1, binop(Iop_Mul32, mkexpr(op2), mkexpr(op3))); - - return "msrkc"; } -static const HChar * +static void s390_irgen_MSY(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, binop(Iop_Mul32, get_gpr_w1(r1), load(Ity_I32, mkexpr(op2addr)))); - - return "msy"; } -static const HChar * +static void s390_irgen_MSG(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, binop(Iop_Mul64, get_gpr_dw0(r1), load(Ity_I64, mkexpr(op2addr)))); - - return "msg"; } -static const HChar * +static void s390_irgen_MSGC(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -9102,37 +7999,29 @@ s390_irgen_MSGC(UChar r1, IRTemp op2addr) assign(op2, load(Ity_I64, mkexpr(op2addr))); s390_cc_thunk_putSS(S390_CC_OP_MUL_64, op1, op2); put_gpr_dw0(r1, binop(Iop_Mul64, mkexpr(op1), mkexpr(op2))); - - return "msgc"; } -static const HChar * +static void s390_irgen_MSGF(UChar r1, IRTemp op2addr) { put_gpr_dw0(r1, binop(Iop_Mul64, get_gpr_dw0(r1), unop(Iop_32Sto64, load(Ity_I32, mkexpr(op2addr))))); - - return "msgf"; } -static const HChar * +static void s390_irgen_MSFI(UChar r1, UInt i2) { put_gpr_w1(r1, binop(Iop_Mul32, get_gpr_w1(r1), mkU32(i2))); - - return "msfi"; } -static const HChar * +static void s390_irgen_MSGFI(UChar r1, UInt i2) { ULong op2 = (ULong)i2 - (((ULong)i2 & (1 << 31)) << 1); put_gpr_dw0(r1, binop(Iop_Mul64, get_gpr_dw0(r1), mkU64(op2))); - - return "msgfi"; } -static const HChar * +static void s390_irgen_MSGRKC(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -9142,11 +8031,9 @@ s390_irgen_MSGRKC(UChar r3, UChar r1, UChar r2) assign(op3, get_gpr_dw0(r3)); s390_cc_thunk_putSS(S390_CC_OP_MUL_64, op2, op3); put_gpr_dw0(r1, binop(Iop_Mul64, mkexpr(op2), mkexpr(op3))); - - return "msgrkc"; } -static const HChar * +static void s390_irgen_OR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -9158,11 +8045,9 @@ s390_irgen_OR(UChar r1, UChar r2) assign(result, binop(Iop_Or32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "or"; } -static const HChar * +static void s390_irgen_OGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -9174,47 +8059,45 @@ s390_irgen_OGR(UChar r1, UChar r2) assign(result, binop(Iop_Or64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return "ogr"; } -static const HChar * +static void s390_irgen_ORK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "ork", Iop_Or32, False, False); + s390_irgen_logicalK32(r3, r1, r2, Iop_Or32, False, False); } -static const HChar * +static void s390_irgen_OGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "ogrk", Iop_Or64, False, False); + s390_irgen_logicalK64(r3, r1, r2, Iop_Or64, False, False); } -static const HChar * +static void s390_irgen_OCRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "ocrk", Iop_Or32, True, False); + s390_irgen_logicalK32(r3, r1, r2, Iop_Or32, True, False); } -static const HChar * +static void s390_irgen_OCGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "ocgrk", Iop_Or64, True, False); + s390_irgen_logicalK64(r3, r1, r2, Iop_Or64, True, False); } -static const HChar * +static void s390_irgen_NORK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK32(r3, r1, r2, "nork", Iop_Or32, False, True); + s390_irgen_logicalK32(r3, r1, r2, Iop_Or32, False, True); } -static const HChar * +static void s390_irgen_NOGRK(UChar r3, UChar r1, UChar r2) { - return s390_irgen_logicalK64(r3, r1, r2, "nogrk", Iop_Or64, False, True); + s390_irgen_logicalK64(r3, r1, r2, Iop_Or64, False, True); } -static const HChar * +static void s390_irgen_O(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -9226,11 +8109,9 @@ s390_irgen_O(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Or32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "o"; } -static const HChar * +static void s390_irgen_OY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -9242,11 +8123,9 @@ s390_irgen_OY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Or32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "oy"; } -static const HChar * +static void s390_irgen_OG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -9258,11 +8137,9 @@ s390_irgen_OG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Or64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_dw0(r1, mkexpr(result)); - - return "og"; } -static const HChar * +static void s390_irgen_OI(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -9274,11 +8151,9 @@ s390_irgen_OI(UChar i2, IRTemp op1addr) assign(result, binop(Iop_Or8, mkexpr(op1), mkU8(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); store(mkexpr(op1addr), mkexpr(result)); - - return "oi"; } -static const HChar * +static void s390_irgen_OIY(UChar i2, IRTemp op1addr) { IRTemp op1 = newTemp(Ity_I8); @@ -9290,11 +8165,9 @@ s390_irgen_OIY(UChar i2, IRTemp op1addr) assign(result, binop(Iop_Or8, mkexpr(op1), mkU8(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); store(mkexpr(op1addr), mkexpr(result)); - - return "oiy"; } -static const HChar * +static void s390_irgen_OIHF(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -9306,11 +8179,9 @@ s390_irgen_OIHF(UChar r1, UInt i2) assign(result, binop(Iop_Or32, mkexpr(op1), mkU32(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w0(r1, mkexpr(result)); - - return "oihf"; } -static const HChar * +static void s390_irgen_OIHH(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -9322,11 +8193,9 @@ s390_irgen_OIHH(UChar r1, UShort i2) assign(result, binop(Iop_Or16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw0(r1, mkexpr(result)); - - return "oihh"; } -static const HChar * +static void s390_irgen_OIHL(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -9338,11 +8207,9 @@ s390_irgen_OIHL(UChar r1, UShort i2) assign(result, binop(Iop_Or16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw1(r1, mkexpr(result)); - - return "oihl"; } -static const HChar * +static void s390_irgen_OILF(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -9354,11 +8221,9 @@ s390_irgen_OILF(UChar r1, UInt i2) assign(result, binop(Iop_Or32, mkexpr(op1), mkU32(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_w1(r1, mkexpr(result)); - - return "oilf"; } -static const HChar * +static void s390_irgen_OILH(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -9370,11 +8235,9 @@ s390_irgen_OILH(UChar r1, UShort i2) assign(result, binop(Iop_Or16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw2(r1, mkexpr(result)); - - return "oilh"; } -static const HChar * +static void s390_irgen_OILL(UChar r1, UShort i2) { IRTemp op1 = newTemp(Ity_I16); @@ -9386,22 +8249,18 @@ s390_irgen_OILL(UChar r1, UShort i2) assign(result, binop(Iop_Or16, mkexpr(op1), mkU16(op2))); s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); put_gpr_hw3(r1, mkexpr(result)); - - return "oill"; } -static const HChar * +static void s390_irgen_PFD(void) { - - return "pfd"; + /* Treat as a no-op */ } -static const HChar * +static void s390_irgen_PFDRL(void) { - - return "pfdrl"; + /* Treat as a no-op */ } static IRExpr * @@ -9459,7 +8318,7 @@ s390_call_pfpo_helper(IRExpr *gr0) return call; } -static const HChar * +static void s390_irgen_PFPO(void) { IRTemp gr0 = newTemp(Ity_I32); /* word 1 [32:63] of GR 0 */ @@ -9680,11 +8539,9 @@ s390_irgen_PFPO(void) put_gpr_w1(1, mkU32(0x0)); s390_cc_thunk_put1d128Z(S390_CC_OP_PFPO_128, src18, gr0); next_insn_if(binop(Iop_CmpEQ32, mkexpr(fn), mkU32(S390_PFPO_D128_TO_F128))); - - return "pfpo"; } -static const HChar * +static void s390_irgen_RLL(UChar r1, UChar r3, IRTemp op2addr) { IRTemp amount = newTemp(Ity_I64); @@ -9695,11 +8552,9 @@ s390_irgen_RLL(UChar r1, UChar r3, IRTemp op2addr) put_gpr_w1(r1, binop(Iop_Or32, binop(Iop_Shl32, mkexpr(op), unop(Iop_64to8, mkexpr(amount))), binop(Iop_Shr32, mkexpr(op), unop(Iop_64to8, binop(Iop_Sub64, mkU64(32), mkexpr(amount)))))); - - return "rll"; } -static const HChar * +static void s390_irgen_RLLG(UChar r1, UChar r3, IRTemp op2addr) { IRTemp amount = newTemp(Ity_I64); @@ -9710,11 +8565,9 @@ s390_irgen_RLLG(UChar r1, UChar r3, IRTemp op2addr) put_gpr_dw0(r1, binop(Iop_Or64, binop(Iop_Shl64, mkexpr(op), unop(Iop_64to8, mkexpr(amount))), binop(Iop_Shr64, mkexpr(op), unop(Iop_64to8, binop(Iop_Sub64, mkU64(64), mkexpr(amount)))))); - - return "rllg"; } -static const HChar * +static void s390_irgen_RNSBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { UChar from; @@ -9749,11 +8602,9 @@ s390_irgen_RNSBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) mkU64(maskc)), mkexpr(result))); } s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); - - return "rnsbg"; } -static const HChar * +static void s390_irgen_RXSBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { UChar from; @@ -9788,11 +8639,9 @@ s390_irgen_RXSBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) mkU64(maskc)), mkexpr(result))); } s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); - - return "rxsbg"; } -static const HChar * +static void s390_irgen_ROSBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { UChar from; @@ -9827,11 +8676,9 @@ s390_irgen_ROSBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) mkU64(maskc)), mkexpr(result))); } s390_cc_thunk_putZ(S390_CC_OP_BITWISE, result); - - return "rosbg"; } -static const HChar * +static void s390_irgen_RISBGx(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5, Bool set_cc) { @@ -9869,22 +8716,19 @@ s390_irgen_RISBGx(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5, assign(result, get_gpr_dw0(r1)); if (set_cc) { s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - return "risbg"; - } - - return "risbgn"; + } } -static const HChar * +static void s390_irgen_RISBG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { - return s390_irgen_RISBGx(r1, r2, i3, i4, i5, True); + s390_irgen_RISBGx(r1, r2, i3, i4, i5, True); } -static const HChar * +static void s390_irgen_RISBGN(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { - return s390_irgen_RISBGx(r1, r2, i3, i4, i5, False); + s390_irgen_RISBGx(r1, r2, i3, i4, i5, False); } static IRExpr * @@ -9932,34 +8776,28 @@ s390_irgen_RISBxG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5, binop(Iop_And32, mkexpr(op2), mkU32(mask))); } -static const HChar * +static void s390_irgen_RISBHG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { put_gpr_w0(r1, s390_irgen_RISBxG(r1, r2, i3, i4, i5, True)); - return "risbhg"; } -static const HChar * +static void s390_irgen_RISBLG(UChar r1, UChar r2, UChar i3, UChar i4, UChar i5) { put_gpr_w1(r1, s390_irgen_RISBxG(r1, r2, i3, i4, i5, False)); - return "risblg"; } -static const HChar * +static void s390_irgen_SAR(UChar r1, UChar r2) { put_ar_w0(r1, get_gpr_w1(r2)); - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM("sar"), AR(r1), GPR(r2)); - - return "sar"; } -static const HChar * +static void s390_irgen_SLDA(UChar r1, IRTemp op2addr) { - s390_insn_assert("slda", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp p1 = newTemp(Ity_I64); IRTemp p2 = newTemp(Ity_I64); @@ -9980,14 +8818,12 @@ s390_irgen_SLDA(UChar r1, IRTemp op2addr) put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); s390_cc_thunk_putZZ(S390_CC_OP_SHIFT_LEFT_64, op, shift_amount); - - return "slda"; } -static const HChar * +static void s390_irgen_SLDL(UChar r1, IRTemp op2addr) { - s390_insn_assert("sldl", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp p1 = newTemp(Ity_I64); IRTemp p2 = newTemp(Ity_I64); @@ -10000,11 +8836,9 @@ s390_irgen_SLDL(UChar r1, IRTemp op2addr) mkexpr(op2addr), mkU64(63))))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "sldl"; } -static const HChar * +static void s390_irgen_SLA(UChar r1, IRTemp op2addr) { IRTemp uop = newTemp(Ity_I32); @@ -10022,11 +8856,9 @@ s390_irgen_SLA(UChar r1, IRTemp op2addr) binop(Iop_And32, mkexpr(uop), mkU32(sign_mask)))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putZZ(S390_CC_OP_SHIFT_LEFT_32, op, shift_amount); - - return "sla"; } -static const HChar * +static void s390_irgen_SLAK(UChar r1, UChar r3, IRTemp op2addr) { IRTemp uop = newTemp(Ity_I32); @@ -10044,11 +8876,9 @@ s390_irgen_SLAK(UChar r1, UChar r3, IRTemp op2addr) binop(Iop_And32, mkexpr(uop), mkU32(sign_mask)))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putZZ(S390_CC_OP_SHIFT_LEFT_32, op, shift_amount); - - return "slak"; } -static const HChar * +static void s390_irgen_SLAG(UChar r1, UChar r3, IRTemp op2addr) { IRTemp uop = newTemp(Ity_I64); @@ -10066,41 +8896,33 @@ s390_irgen_SLAG(UChar r1, UChar r3, IRTemp op2addr) binop(Iop_And64, mkexpr(uop), mkU64(sign_mask)))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putZZ(S390_CC_OP_SHIFT_LEFT_64, op, shift_amount); - - return "slag"; } -static const HChar * +static void s390_irgen_SLL(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, binop(Iop_Shl32, get_gpr_w1(r1), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - - return "sll"; } -static const HChar * +static void s390_irgen_SLLK(UChar r1, UChar r3, IRTemp op2addr) { put_gpr_w1(r1, binop(Iop_Shl32, get_gpr_w1(r3), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - - return "sllk"; } -static const HChar * +static void s390_irgen_SLLG(UChar r1, UChar r3, IRTemp op2addr) { put_gpr_dw0(r1, binop(Iop_Shl64, get_gpr_dw0(r3), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - - return "sllg"; } -static const HChar * +static void s390_irgen_SRDA(UChar r1, IRTemp op2addr) { - s390_insn_assert("srda", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp p1 = newTemp(Ity_I64); IRTemp p2 = newTemp(Ity_I64); @@ -10114,14 +8936,12 @@ s390_irgen_SRDA(UChar r1, IRTemp op2addr) put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - - return "srda"; } -static const HChar * +static void s390_irgen_SRDL(UChar r1, IRTemp op2addr) { - s390_insn_assert("srdl", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp p1 = newTemp(Ity_I64); IRTemp p2 = newTemp(Ity_I64); @@ -10134,11 +8954,9 @@ s390_irgen_SRDL(UChar r1, IRTemp op2addr) mkexpr(op2addr), mkU64(63))))); put_gpr_w1(r1, unop(Iop_64HIto32, mkexpr(result))); put_gpr_w1(r1 + 1, unop(Iop_64to32, mkexpr(result))); - - return "srdl"; } -static const HChar * +static void s390_irgen_SRA(UChar r1, IRTemp op2addr) { IRTemp result = newTemp(Ity_I32); @@ -10149,11 +8967,9 @@ s390_irgen_SRA(UChar r1, IRTemp op2addr) mkexpr(op2addr), mkU64(63))))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - - return "sra"; } -static const HChar * +static void s390_irgen_SRAK(UChar r1, UChar r3, IRTemp op2addr) { IRTemp result = newTemp(Ity_I32); @@ -10164,11 +8980,9 @@ s390_irgen_SRAK(UChar r1, UChar r3, IRTemp op2addr) mkexpr(op2addr), mkU64(63))))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - - return "srak"; } -static const HChar * +static void s390_irgen_SRAG(UChar r1, UChar r3, IRTemp op2addr) { IRTemp result = newTemp(Ity_I64); @@ -10179,11 +8993,9 @@ s390_irgen_SRAG(UChar r1, UChar r3, IRTemp op2addr) mkexpr(op2addr), mkU64(63))))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putS(S390_CC_OP_LOAD_AND_TEST, result); - - return "srag"; } -static const HChar * +static void s390_irgen_SRL(UChar r1, IRTemp op2addr) { IRTemp op = newTemp(Ity_I32); @@ -10191,11 +9003,9 @@ s390_irgen_SRL(UChar r1, IRTemp op2addr) assign(op, get_gpr_w1(r1)); put_gpr_w1(r1, binop(Iop_Shr32, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - - return "srl"; } -static const HChar * +static void s390_irgen_SRLK(UChar r1, UChar r3, IRTemp op2addr) { IRTemp op = newTemp(Ity_I32); @@ -10203,11 +9013,9 @@ s390_irgen_SRLK(UChar r1, UChar r3, IRTemp op2addr) assign(op, get_gpr_w1(r3)); put_gpr_w1(r1, binop(Iop_Shr32, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - - return "srlk"; } -static const HChar * +static void s390_irgen_SRLG(UChar r1, UChar r3, IRTemp op2addr) { IRTemp op = newTemp(Ity_I64); @@ -10215,75 +9023,57 @@ s390_irgen_SRLG(UChar r1, UChar r3, IRTemp op2addr) assign(op, get_gpr_dw0(r3)); put_gpr_dw0(r1, binop(Iop_Shr64, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - - return "srlg"; } -static const HChar * +static void s390_irgen_ST(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_w1(r1)); - - return "st"; } -static const HChar * +static void s390_irgen_STY(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_w1(r1)); - - return "sty"; } -static const HChar * +static void s390_irgen_STG(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_dw0(r1)); - - return "stg"; } -static const HChar * +static void s390_irgen_STRL(UChar r1, UInt i2) { store(mkU64(addr_rel_long(i2)), get_gpr_w1(r1)); - - return "strl"; } -static const HChar * +static void s390_irgen_STGRL(UChar r1, UInt i2) { store(mkU64(addr_rel_long(i2)), get_gpr_dw0(r1)); - - return "stgrl"; } -static const HChar * +static void s390_irgen_STC(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_b7(r1)); - - return "stc"; } -static const HChar * +static void s390_irgen_STCY(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_b7(r1)); - - return "stcy"; } -static const HChar * +static void s390_irgen_STCH(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_b3(r1)); - - return "stch"; } -static const HChar * +static void s390_irgen_STCM(UChar r1, UChar r3, IRTemp op2addr) { UChar mask; @@ -10306,11 +9096,9 @@ s390_irgen_STCM(UChar r1, UChar r3, IRTemp op2addr) if ((mask & 1) != 0) { store(binop(Iop_Add64, mkexpr(op2addr), mkU64(n)), get_gpr_b7(r1)); } - - return "stcm"; } -static const HChar * +static void s390_irgen_STCMY(UChar r1, UChar r3, IRTemp op2addr) { UChar mask; @@ -10333,11 +9121,9 @@ s390_irgen_STCMY(UChar r1, UChar r3, IRTemp op2addr) if ((mask & 1) != 0) { store(binop(Iop_Add64, mkexpr(op2addr), mkU64(n)), get_gpr_b7(r1)); } - - return "stcmy"; } -static const HChar * +static void s390_irgen_STCMH(UChar r1, UChar r3, IRTemp op2addr) { UChar mask; @@ -10360,100 +9146,78 @@ s390_irgen_STCMH(UChar r1, UChar r3, IRTemp op2addr) if ((mask & 1) != 0) { store(binop(Iop_Add64, mkexpr(op2addr), mkU64(n)), get_gpr_b3(r1)); } - - return "stcmh"; } -static const HChar * +static void s390_irgen_STH(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_hw3(r1)); - - return "sth"; } -static const HChar * +static void s390_irgen_STHY(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_hw3(r1)); - - return "sthy"; } -static const HChar * +static void s390_irgen_STHRL(UChar r1, UInt i2) { store(mkU64(addr_rel_long(i2)), get_gpr_hw3(r1)); - - return "sthrl"; } -static const HChar * +static void s390_irgen_STHH(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_hw1(r1)); - - return "sthh"; } -static const HChar * +static void s390_irgen_STFH(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_w0(r1)); - - return "stfh"; } -static const HChar * +static void s390_irgen_STOC(UChar r1, IRTemp op2addr) { /* condition is checked in format handler */ store(mkexpr(op2addr), get_gpr_w1(r1)); - - return "stoc"; } -static const HChar * +static void s390_irgen_STOCG(UChar r1, IRTemp op2addr) { /* condition is checked in format handler */ store(mkexpr(op2addr), get_gpr_dw0(r1)); - - return "stocg"; } -static const HChar * +static void s390_irgen_STPQ(UChar r1, IRTemp op2addr) { - s390_insn_assert("stpq", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); store(mkexpr(op2addr), get_gpr_dw0(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(8)), get_gpr_dw0(r1 + 1)); - - return "stpq"; } -static const HChar * +static void s390_irgen_STRVH(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_b7(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(1)), get_gpr_b6(r1)); - - return "strvh"; } -static const HChar * +static void s390_irgen_STRV(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_b7(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(1)), get_gpr_b6(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(2)), get_gpr_b5(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(3)), get_gpr_b4(r1)); - - return "strv"; } -static const HChar * +static void s390_irgen_STRVG(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_gpr_b7(r1)); @@ -10464,11 +9228,9 @@ s390_irgen_STRVG(UChar r1, IRTemp op2addr) store(binop(Iop_Add64, mkexpr(op2addr), mkU64(5)), get_gpr_b2(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(6)), get_gpr_b1(r1)); store(binop(Iop_Add64, mkexpr(op2addr), mkU64(7)), get_gpr_b0(r1)); - - return "strvg"; } -static const HChar * +static void s390_irgen_SR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -10480,11 +9242,9 @@ s390_irgen_SR(UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "sr"; } -static const HChar * +static void s390_irgen_SGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -10496,11 +9256,9 @@ s390_irgen_SGR(UChar r1, UChar r2) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "sgr"; } -static const HChar * +static void s390_irgen_SGFR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -10512,11 +9270,9 @@ s390_irgen_SGFR(UChar r1, UChar r2) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "sgfr"; } -static const HChar * +static void s390_irgen_SRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -10528,11 +9284,9 @@ s390_irgen_SRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op2, op3); put_gpr_w1(r1, mkexpr(result)); - - return "srk"; } -static const HChar * +static void s390_irgen_SGRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -10544,11 +9298,9 @@ s390_irgen_SGRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub64, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op2, op3); put_gpr_dw0(r1, mkexpr(result)); - - return "sgrk"; } -static const HChar * +static void s390_irgen_S(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10560,11 +9312,9 @@ s390_irgen_S(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "s"; } -static const HChar * +static void s390_irgen_SY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10576,11 +9326,9 @@ s390_irgen_SY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "sy"; } -static const HChar * +static void s390_irgen_SG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -10592,11 +9340,9 @@ s390_irgen_SG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "sg"; } -static const HChar * +static void s390_irgen_SGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -10608,11 +9354,9 @@ s390_irgen_SGF(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "sgf"; } -static const HChar * +static void s390_irgen_SGH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -10624,11 +9368,9 @@ s390_irgen_SGH(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "sgh"; } -static const HChar * +static void s390_irgen_SH(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10640,11 +9382,9 @@ s390_irgen_SH(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "sh"; } -static const HChar * +static void s390_irgen_SHY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10656,11 +9396,9 @@ s390_irgen_SHY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "shy"; } -static const HChar * +static void s390_irgen_SHHHR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -10672,11 +9410,9 @@ s390_irgen_SHHHR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "shhhr"; } -static const HChar * +static void s390_irgen_SHHLR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -10688,11 +9424,9 @@ s390_irgen_SHHLR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putSS(S390_CC_OP_SIGNED_SUB_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "shhlr"; } -static const HChar * +static void s390_irgen_SLR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -10704,11 +9438,9 @@ s390_irgen_SLR(UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "slr"; } -static const HChar * +static void s390_irgen_SLGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -10720,11 +9452,9 @@ s390_irgen_SLGR(UChar r1, UChar r2) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "slgr"; } -static const HChar * +static void s390_irgen_SLGFR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -10736,11 +9466,9 @@ s390_irgen_SLGFR(UChar r1, UChar r2) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "slgfr"; } -static const HChar * +static void s390_irgen_SLRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -10752,11 +9480,9 @@ s390_irgen_SLRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op2, op3); put_gpr_w1(r1, mkexpr(result)); - - return "slrk"; } -static const HChar * +static void s390_irgen_SLGRK(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -10768,11 +9494,9 @@ s390_irgen_SLGRK(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub64, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_64, op2, op3); put_gpr_dw0(r1, mkexpr(result)); - - return "slgrk"; } -static const HChar * +static void s390_irgen_SL(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10784,11 +9508,9 @@ s390_irgen_SL(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "sl"; } -static const HChar * +static void s390_irgen_SLY(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10800,11 +9522,9 @@ s390_irgen_SLY(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub32, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op1, op2); put_gpr_w1(r1, mkexpr(result)); - - return "sly"; } -static const HChar * +static void s390_irgen_SLG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -10816,11 +9536,9 @@ s390_irgen_SLG(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "slg"; } -static const HChar * +static void s390_irgen_SLGF(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -10832,11 +9550,9 @@ s390_irgen_SLGF(UChar r1, IRTemp op2addr) assign(result, binop(Iop_Sub64, mkexpr(op1), mkexpr(op2))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_64, op1, op2); put_gpr_dw0(r1, mkexpr(result)); - - return "slgf"; } -static const HChar * +static void s390_irgen_SLFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I32); @@ -10849,11 +9565,9 @@ s390_irgen_SLFI(UChar r1, UInt i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op1, mktemp(Ity_I32, mkU32(op2))); put_gpr_w1(r1, mkexpr(result)); - - return "slfi"; } -static const HChar * +static void s390_irgen_SLGFI(UChar r1, UInt i2) { IRTemp op1 = newTemp(Ity_I64); @@ -10866,11 +9580,9 @@ s390_irgen_SLGFI(UChar r1, UInt i2) s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_64, op1, mktemp(Ity_I64, mkU64(op2))); put_gpr_dw0(r1, mkexpr(result)); - - return "slgfi"; } -static const HChar * +static void s390_irgen_SLHHHR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -10882,11 +9594,9 @@ s390_irgen_SLHHHR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "slhhhr"; } -static const HChar * +static void s390_irgen_SLHHLR(UChar r3, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I32); @@ -10898,11 +9608,9 @@ s390_irgen_SLHHLR(UChar r3, UChar r1, UChar r2) assign(result, binop(Iop_Sub32, mkexpr(op2), mkexpr(op3))); s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_SUB_32, op2, op3); put_gpr_w0(r1, mkexpr(result)); - - return "slhhlr"; } -static const HChar * +static void s390_irgen_SLBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I32); @@ -10918,11 +9626,9 @@ s390_irgen_SLBR(UChar r1, UChar r2) mkexpr(borrow_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_SUBB_32, op1, op2, borrow_in); put_gpr_w1(r1, mkexpr(result)); - - return "slbr"; } -static const HChar * +static void s390_irgen_SLBGR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -10938,11 +9644,9 @@ s390_irgen_SLBGR(UChar r1, UChar r2) mkexpr(borrow_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_SUBB_64, op1, op2, borrow_in); put_gpr_dw0(r1, mkexpr(result)); - - return "slbgr"; } -static const HChar * +static void s390_irgen_SLB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I32); @@ -10958,11 +9662,9 @@ s390_irgen_SLB(UChar r1, IRTemp op2addr) mkexpr(borrow_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_SUBB_32, op1, op2, borrow_in); put_gpr_w1(r1, mkexpr(result)); - - return "slb"; } -static const HChar * +static void s390_irgen_SLBG(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_I64); @@ -10978,11 +9680,9 @@ s390_irgen_SLBG(UChar r1, IRTemp op2addr) mkexpr(borrow_in))); s390_cc_thunk_putZZZ(S390_CC_OP_UNSIGNED_SUBB_64, op1, op2, borrow_in); put_gpr_dw0(r1, mkexpr(result)); - - return "slbg"; } -static const HChar * +static void s390_irgen_SVC(UChar i) { IRTemp sysno = newTemp(Ity_I64); @@ -10993,39 +9693,36 @@ s390_irgen_SVC(UChar i) assign(sysno, unop(Iop_32Uto64, get_gpr_w1(1))); } system_call(mkexpr(sysno)); - - return "svc"; } -static const HChar * -s390_irgen_TMx(const HChar *mnem, UChar mask, IRTemp op1addr) +static void +s390_irgen_TMx(UChar mask, IRTemp op1addr) { IRTemp masked = newTemp(Ity_I8); assign(masked, binop(Iop_And8, load(Ity_I8, mkexpr(op1addr)), mkU8(mask))); s390_cc_thunk_putZZ(S390_CC_OP_TEST_UNDER_MASK_8, masked, mktemp(Ity_I8, mkU8(mask))); - return mnem; } -static const HChar * +static void s390_irgen_TM(UChar i2, IRTemp op1addr) { - return s390_irgen_TMx("tm", i2, op1addr); + s390_irgen_TMx(i2, op1addr); } -static const HChar * +static void s390_irgen_TMY(UChar i2, IRTemp op1addr) { - return s390_irgen_TMx("tmy", i2, op1addr); + s390_irgen_TMx( i2, op1addr); } -static const HChar * -s390_irgen_TMxx(const HChar *mnem, UChar r1, UShort mask, UChar offs) +static void +s390_irgen_TMxx(UChar r1, UShort mask, UChar offs) { if (mask == 0) { s390_cc_set_val(0); - return mnem; + return; } IRExpr* masked; @@ -11042,155 +9739,126 @@ s390_irgen_TMxx(const HChar *mnem, UChar r1, UShort mask, UChar offs) mktemp(Ity_I64, masked), mktemp(Ity_I64, mkU64(mask))); } - return mnem; } -static const HChar * +static void s390_irgen_TMHH(UChar r1, UShort i2) { - return s390_irgen_TMxx("tmhh", r1, i2, 48); + s390_irgen_TMxx( r1, i2, 48); } -static const HChar * +static void s390_irgen_TMHL(UChar r1, UShort i2) { - return s390_irgen_TMxx("tmhl", r1, i2, 32); + s390_irgen_TMxx(r1, i2, 32); } -static const HChar * +static void s390_irgen_TMLH(UChar r1, UShort i2) { - return s390_irgen_TMxx("tmlh", r1, i2, 16); + s390_irgen_TMxx(r1, i2, 16); } -static const HChar * +static void s390_irgen_TMLL(UChar r1, UShort i2) { - return s390_irgen_TMxx("tmll", r1, i2, 0); + s390_irgen_TMxx(r1, i2, 0); } -static const HChar * +static void s390_irgen_EFPC(UChar r1) { put_gpr_w1(r1, get_fpc_w0()); - - return "efpc"; } -static const HChar * +static void s390_irgen_LER(UChar r1, UChar r2) { put_fpr_w0(r1, get_fpr_w0(r2)); - - return "ler"; } -static const HChar * +static void s390_irgen_LDR(UChar r1, UChar r2) { put_fpr_dw0(r1, get_fpr_dw0(r2)); - - return "ldr"; } -static const HChar * +static void s390_irgen_LDER(UChar r1, UChar r2) { put_fpr_dw0(r1, mkF64i(0x0)); put_fpr_w0(r1, get_fpr_w0(r2)); - - return "lder"; } -static const HChar * +static void s390_irgen_LXR(UChar r1, UChar r2) { - s390_insn_assert("lxr", is_valid_fpr_pair(r1)); - s390_insn_assert("lxr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); put_fpr_dw0(r1, get_fpr_dw0(r2)); put_fpr_dw0(r1 + 2, get_fpr_dw0(r2 + 2)); - - return "lxr"; } -static const HChar * +static void s390_irgen_LE(UChar r1, IRTemp op2addr) { put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr))); - - return "le"; } -static const HChar * +static void s390_irgen_LD(UChar r1, IRTemp op2addr) { put_fpr_dw0(r1, load(Ity_F64, mkexpr(op2addr))); - - return "ld"; } -static const HChar * +static void s390_irgen_LDE(UChar r1, IRTemp op2addr) { put_fpr_dw0(r1, mkF64i(0x0)); put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr))); - - return "lde"; } -static const HChar * +static void s390_irgen_LEY(UChar r1, IRTemp op2addr) { put_fpr_w0(r1, load(Ity_F32, mkexpr(op2addr))); - - return "ley"; } -static const HChar * +static void s390_irgen_LDY(UChar r1, IRTemp op2addr) { put_fpr_dw0(r1, load(Ity_F64, mkexpr(op2addr))); - - return "ldy"; } -static const HChar * +static void s390_irgen_LFPC(IRTemp op2addr) { put_fpc_w0(load(Ity_I32, mkexpr(op2addr))); - - return "lfpc"; } -static const HChar * +static void s390_irgen_LZER(UChar r1) { put_fpr_w0(r1, mkF32i(0x0)); - - return "lzer"; } -static const HChar * +static void s390_irgen_LZDR(UChar r1) { put_fpr_dw0(r1, mkF64i(0x0)); - - return "lzdr"; } -static const HChar * +static void s390_irgen_LZXR(UChar r1) { - s390_insn_assert("lzxr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); put_fpr_dw0(r1, mkF64i(0x0)); put_fpr_dw0(r1 + 2, mkF64i(0x0)); - - return "lzxr"; } -static const HChar * +static void s390_irgen_SRNM(IRTemp op2addr) { UInt input_mask, fpc_mask; @@ -11202,15 +9870,14 @@ s390_irgen_SRNM(IRTemp op2addr) binop(Iop_And32, get_fpc_w0(), mkU32(~fpc_mask)), binop(Iop_And32, unop(Iop_64to32, mkexpr(op2addr)), mkU32(input_mask)))); - return "srnm"; } -static const HChar * +static void s390_irgen_SRNMB(UChar b2, UShort d2) { /* Can only check at IR generation time when b2 == 0 */ if (b2 == 0) { - s390_insn_assert("srnmb", d2 <= 3 || d2 == 7); // valid rounding mode + s390_insn_assert(d2 <= 3 || d2 == 7); // valid rounding mode } IRTemp op2addr = newTemp(Ity_I64); @@ -11224,12 +9891,11 @@ s390_irgen_SRNMB(UChar b2, UShort d2) binop(Iop_And32, get_fpc_w0(), mkU32(~fpc_mask)), binop(Iop_And32, unop(Iop_64to32, mkexpr(op2addr)), mkU32(input_mask)))); - return "srnmb"; } /* All 8 values in op2addr[61:63] correspond to a valid DFP rounding mode */ -static const HChar * +static void s390_irgen_SRNMT(IRTemp op2addr) { UInt input_mask, fpc_mask; @@ -11243,59 +9909,46 @@ s390_irgen_SRNMT(IRTemp op2addr) binop(Iop_Shl32, binop(Iop_And32, unop(Iop_64to32, mkexpr(op2addr)), mkU32(input_mask)), mkU8(4)))); - return "srnmt"; } -static const HChar * +static void s390_irgen_SFPC(UChar r1) { put_fpc_w0(get_gpr_w1(r1)); - - return "sfpc"; } -static const HChar * +static void s390_irgen_STE(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_fpr_w0(r1)); - - return "ste"; } -static const HChar * +static void s390_irgen_STD(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_fpr_dw0(r1)); - - return "std"; } -static const HChar * +static void s390_irgen_STEY(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_fpr_w0(r1)); - - return "stey"; } -static const HChar * +static void s390_irgen_STDY(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), get_fpr_dw0(r1)); - - return "stdy"; } -static const HChar * +static void s390_irgen_STFPC(IRTemp op2addr) { store(mkexpr(op2addr), get_fpc_w0()); - - return "stfpc"; } -static const HChar * +static void s390_irgen_AEBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F32); @@ -11309,11 +9962,9 @@ s390_irgen_AEBR(UChar r1, UChar r2) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_32, result); put_fpr_w0(r1, mkexpr(result)); - - return "aebr"; } -static const HChar * +static void s390_irgen_ADBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F64); @@ -11327,11 +9978,9 @@ s390_irgen_ADBR(UChar r1, UChar r2) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_64, result); put_fpr_dw0(r1, mkexpr(result)); - - return "adbr"; } -static const HChar * +static void s390_irgen_AEB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F32); @@ -11345,11 +9994,9 @@ s390_irgen_AEB(UChar r1, IRTemp op2addr) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_32, result); put_fpr_w0(r1, mkexpr(result)); - - return "aeb"; } -static const HChar * +static void s390_irgen_ADB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F64); @@ -11363,30 +10010,26 @@ s390_irgen_ADB(UChar r1, IRTemp op2addr) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_64, result); put_fpr_dw0(r1, mkexpr(result)); - - return "adb"; } -static const HChar * +static void s390_irgen_CEFBRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); - s390_insn_assert("cefbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); IRTemp op2 = newTemp(Ity_I32); assign(op2, get_gpr_w1(r2)); put_fpr_w0(r1, binop(Iop_I32StoF32, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op2))); - - return "cefbra"; } -static const HChar * +static void s390_irgen_CDFBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cdfbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11394,46 +10037,40 @@ s390_irgen_CDFBRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_w1(r2)); put_fpr_dw0(r1, unop(Iop_I32StoF64, mkexpr(op2))); - - return "cdfbra"; } -static const HChar * +static void s390_irgen_CEGBRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); - s390_insn_assert("cegbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); IRTemp op2 = newTemp(Ity_I64); assign(op2, get_gpr_dw0(r2)); put_fpr_w0(r1, binop(Iop_I64StoF32, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op2))); - - return "cegbra"; } -static const HChar * +static void s390_irgen_CDGBRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); - s390_insn_assert("cdgbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); IRTemp op2 = newTemp(Ity_I64); assign(op2, get_gpr_dw0(r2)); put_fpr_dw0(r1, binop(Iop_I64StoF64, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op2))); - - return "cdgbra"; } -static const HChar * +static void s390_irgen_CELFBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("celfbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11442,13 +10079,12 @@ s390_irgen_CELFBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_w1(r2)); put_fpr_w0(r1, binop(Iop_I32UtoF32, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op2))); - return "celfbr"; } -static const HChar * +static void s390_irgen_CDLFBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cdlfbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11456,13 +10092,12 @@ s390_irgen_CDLFBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_w1(r2)); put_fpr_dw0(r1, unop(Iop_I32UtoF64, mkexpr(op2))); - return "cdlfbr"; } -static const HChar * +static void s390_irgen_CELGBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("celgbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11471,13 +10106,12 @@ s390_irgen_CELGBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_dw0(r2)); put_fpr_w0(r1, binop(Iop_I64UtoF32, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op2))); - return "celgbr"; } -static const HChar * +static void s390_irgen_CDLGBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cdlgbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11487,13 +10121,12 @@ s390_irgen_CDLGBR(UChar m3, UChar m4, UChar r1, UChar r2) put_fpr_dw0(r1, binop(Iop_I64UtoF64, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op2))); - return "cdlgbr"; } -static const HChar * +static void s390_irgen_CLFEBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clfebr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11505,13 +10138,12 @@ s390_irgen_CLFEBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_F32toI32U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_32_TO_UINT_32, op, rounding_mode); - return "clfebr"; } -static const HChar * +static void s390_irgen_CLFDBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clfdbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11523,13 +10155,12 @@ s390_irgen_CLFDBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_F64toI32U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_64_TO_UINT_32, op, rounding_mode); - return "clfdbr"; } -static const HChar * +static void s390_irgen_CLGEBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clgebr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11541,13 +10172,12 @@ s390_irgen_CLGEBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_F32toI64U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_32_TO_UINT_64, op, rounding_mode); - return "clgebr"; } -static const HChar * +static void s390_irgen_CLGDBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clgdbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11560,13 +10190,12 @@ s390_irgen_CLGDBR(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_64_TO_UINT_64, op, rounding_mode); - return "clgdbr"; } -static const HChar * +static void s390_irgen_CFEBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cfebra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11579,14 +10208,12 @@ s390_irgen_CFEBRA(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_32_TO_INT_32, op, rounding_mode); - - return "cfebra"; } -static const HChar * +static void s390_irgen_CFDBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cfdbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11599,14 +10226,12 @@ s390_irgen_CFDBRA(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_64_TO_INT_32, op, rounding_mode); - - return "cfdbra"; } -static const HChar * +static void s390_irgen_CGEBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cgebra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11619,14 +10244,12 @@ s390_irgen_CGEBRA(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_32_TO_INT_64, op, rounding_mode); - - return "cgebra"; } -static const HChar * +static void s390_irgen_CGDBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cgdbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -11639,11 +10262,9 @@ s390_irgen_CGDBRA(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_64_TO_INT_64, op, rounding_mode); - - return "cgdbra"; } -static const HChar * +static void s390_irgen_DEBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F32); @@ -11656,11 +10277,9 @@ s390_irgen_DEBR(UChar r1, UChar r2) assign(result, triop(Iop_DivF32, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_w0(r1, mkexpr(result)); - - return "debr"; } -static const HChar * +static void s390_irgen_DDBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F64); @@ -11673,11 +10292,9 @@ s390_irgen_DDBR(UChar r1, UChar r2) assign(result, triop(Iop_DivF64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_dw0(r1, mkexpr(result)); - - return "ddbr"; } -static const HChar * +static void s390_irgen_DEB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F32); @@ -11690,11 +10307,9 @@ s390_irgen_DEB(UChar r1, IRTemp op2addr) assign(result, triop(Iop_DivF32, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_w0(r1, mkexpr(result)); - - return "deb"; } -static const HChar * +static void s390_irgen_DDB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F64); @@ -11707,11 +10322,9 @@ s390_irgen_DDB(UChar r1, IRTemp op2addr) assign(result, triop(Iop_DivF64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_dw0(r1, mkexpr(result)); - - return "ddb"; } -static const HChar * +static void s390_irgen_LTEBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F32); @@ -11719,11 +10332,9 @@ s390_irgen_LTEBR(UChar r1, UChar r2) assign(result, get_fpr_w0(r2)); put_fpr_w0(r1, mkexpr(result)); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_32, result); - - return "ltebr"; } -static const HChar * +static void s390_irgen_LTDBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); @@ -11731,11 +10342,9 @@ s390_irgen_LTDBR(UChar r1, UChar r2) assign(result, get_fpr_dw0(r2)); put_fpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_64, result); - - return "ltdbr"; } -static const HChar * +static void s390_irgen_LCEBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F32); @@ -11743,11 +10352,9 @@ s390_irgen_LCEBR(UChar r1, UChar r2) assign(result, unop(Iop_NegF32, get_fpr_w0(r2))); put_fpr_w0(r1, mkexpr(result)); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_32, result); - - return "lcebr"; } -static const HChar * +static void s390_irgen_LCDBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); @@ -11755,49 +10362,41 @@ s390_irgen_LCDBR(UChar r1, UChar r2) assign(result, unop(Iop_NegF64, get_fpr_dw0(r2))); put_fpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_64, result); - - return "lcdbr"; } -static const HChar * +static void s390_irgen_LDEBR(UChar r1, UChar r2) { IRTemp op = newTemp(Ity_F32); assign(op, get_fpr_w0(r2)); put_fpr_dw0(r1, unop(Iop_F32toF64, mkexpr(op))); - - return "ldebr"; } -static const HChar * +static void s390_irgen_LDEB(UChar r1, IRTemp op2addr) { IRTemp op = newTemp(Ity_F32); assign(op, load(Ity_F32, mkexpr(op2addr))); put_fpr_dw0(r1, unop(Iop_F32toF64, mkexpr(op))); - - return "ldeb"; } -static const HChar * +static void s390_irgen_LEDBRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); - s390_insn_assert("ledbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); IRTemp op = newTemp(Ity_F64); assign(op, get_fpr_dw0(r2)); put_fpr_w0(r1, binop(Iop_F64toF32, mkexpr(encode_bfp_rounding_mode(m3)), mkexpr(op))); - - return "ledbra"; } -static const HChar * +static void s390_irgen_MEEBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F32); @@ -11811,11 +10410,9 @@ s390_irgen_MEEBR(UChar r1, UChar r2) assign(result, triop(Iop_MulF32, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_w0(r1, mkexpr(result)); - - return "meebr"; } -static const HChar * +static void s390_irgen_MDBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F64); @@ -11828,11 +10425,9 @@ s390_irgen_MDBR(UChar r1, UChar r2) assign(result, triop(Iop_MulF64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_dw0(r1, mkexpr(result)); - - return "mdbr"; } -static const HChar * +static void s390_irgen_MEEB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F32); @@ -11845,11 +10440,9 @@ s390_irgen_MEEB(UChar r1, IRTemp op2addr) assign(result, triop(Iop_MulF32, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_w0(r1, mkexpr(result)); - - return "meeb"; } -static const HChar * +static void s390_irgen_MDB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F64); @@ -11862,11 +10455,9 @@ s390_irgen_MDB(UChar r1, IRTemp op2addr) assign(result, triop(Iop_MulF64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_dw0(r1, mkexpr(result)); - - return "mdb"; } -static const HChar * +static void s390_irgen_SEBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F32); @@ -11880,11 +10471,9 @@ s390_irgen_SEBR(UChar r1, UChar r2) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_32, result); put_fpr_w0(r1, mkexpr(result)); - - return "sebr"; } -static const HChar * +static void s390_irgen_SDBR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_F64); @@ -11898,11 +10487,9 @@ s390_irgen_SDBR(UChar r1, UChar r2) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_64, result); put_fpr_dw0(r1, mkexpr(result)); - - return "sdbr"; } -static const HChar * +static void s390_irgen_SEB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F32); @@ -11916,11 +10503,9 @@ s390_irgen_SEB(UChar r1, IRTemp op2addr) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_32, result); put_fpr_w0(r1, mkexpr(result)); - - return "seb"; } -static const HChar * +static void s390_irgen_SDB(UChar r1, IRTemp op2addr) { IRTemp op1 = newTemp(Ity_F64); @@ -11934,11 +10519,9 @@ s390_irgen_SDB(UChar r1, IRTemp op2addr) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_BFP_RESULT_64, result); put_fpr_dw0(r1, mkexpr(result)); - - return "sdb"; } -static const HChar * +static void s390_irgen_ADTRA(UChar r3, UChar m4, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -11953,15 +10536,14 @@ s390_irgen_ADTRA(UChar r3, UChar m4, UChar r1, UChar r2) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_DFP_RESULT_64, result); put_dpr_dw0(r1, mkexpr(result)); - return "adtra"; } -static const HChar * +static void s390_irgen_AXTRA(UChar r3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("axtra", is_valid_fpr_pair(r1)); - s390_insn_assert("axtra", is_valid_fpr_pair(r2)); - s390_insn_assert("axtra", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -11976,10 +10558,9 @@ s390_irgen_AXTRA(UChar r3, UChar m4, UChar r1, UChar r2) put_dpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1d128(S390_CC_OP_DFP_RESULT_128, result); - return "axtra"; } -static const HChar * +static void s390_irgen_CDTR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -11993,15 +10574,13 @@ s390_irgen_CDTR(UChar r1, UChar r2) assign(cc_s390, convert_vex_dfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - - return "cdtr"; } -static const HChar * +static void s390_irgen_CXTR(UChar r1, UChar r2) { - s390_insn_assert("cxtr", is_valid_fpr_pair(r1)); - s390_insn_assert("cxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -12014,11 +10593,9 @@ s390_irgen_CXTR(UChar r1, UChar r2) assign(cc_s390, convert_vex_dfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - - return "cxtr"; } -static const HChar * +static void s390_irgen_CDFTR(UChar m3 __attribute__((unused)), UChar m4, UChar r1, UChar r2) { @@ -12028,14 +10605,13 @@ s390_irgen_CDFTR(UChar m3 __attribute__((unused)), assign(op2, get_gpr_w1(r2)); put_dpr_dw0(r1, unop(Iop_I32StoD64, mkexpr(op2))); - return "cdftr"; } -static const HChar * +static void s390_irgen_CXFTR(UChar m3 __attribute__((unused)), UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxftr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12043,10 +10619,9 @@ s390_irgen_CXFTR(UChar m3 __attribute__((unused)), assign(op2, get_gpr_w1(r2)); put_dpr_pair(r1, unop(Iop_I32StoD128, mkexpr(op2))); - return "cxftr"; } -static const HChar * +static void s390_irgen_CDGTRA(UChar m3, UChar m4, UChar r1, UChar r2) { IRTemp op2 = newTemp(Ity_I64); @@ -12057,14 +10632,13 @@ s390_irgen_CDGTRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_dw0(r2)); put_dpr_dw0(r1, binop(Iop_I64StoD64, mkexpr(encode_dfp_rounding_mode(m3)), mkexpr(op2))); - return "cdgtra"; } -static const HChar * +static void s390_irgen_CXGTRA(UChar m3 __attribute__((unused)), UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxgtra", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12072,10 +10646,9 @@ s390_irgen_CXGTRA(UChar m3 __attribute__((unused)), assign(op2, get_gpr_dw0(r2)); put_dpr_pair(r1, unop(Iop_I64StoD128, mkexpr(op2))); - return "cxgtra"; } -static const HChar * +static void s390_irgen_CDLFTR(UChar m3 __attribute__((unused)), UChar m4, UChar r1, UChar r2) { @@ -12085,14 +10658,13 @@ s390_irgen_CDLFTR(UChar m3 __attribute__((unused)), assign(op2, get_gpr_w1(r2)); put_dpr_dw0(r1, unop(Iop_I32UtoD64, mkexpr(op2))); - return "cdlftr"; } -static const HChar * +static void s390_irgen_CXLFTR(UChar m3 __attribute__((unused)), UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxlftr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12100,10 +10672,9 @@ s390_irgen_CXLFTR(UChar m3 __attribute__((unused)), assign(op2, get_gpr_w1(r2)); put_dpr_pair(r1, unop(Iop_I32UtoD128, mkexpr(op2))); - return "cxlftr"; } -static const HChar * +static void s390_irgen_CDLGTR(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) @@ -12113,14 +10684,13 @@ s390_irgen_CDLGTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_dw0(r2)); put_dpr_dw0(r1, binop(Iop_I64UtoD64, mkexpr(encode_dfp_rounding_mode(m3)), mkexpr(op2))); - return "cdlgtr"; } -static const HChar * +static void s390_irgen_CXLGTR(UChar m3 __attribute__((unused)), UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxlgtr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12128,10 +10698,9 @@ s390_irgen_CXLGTR(UChar m3 __attribute__((unused)), assign(op2, get_gpr_dw0(r2)); put_dpr_pair(r1, unop(Iop_I64UtoD128, mkexpr(op2))); - return "cxlgtr"; } -static const HChar * +static void s390_irgen_CFDTR(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) @@ -12144,13 +10713,12 @@ s390_irgen_CFDTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D64toI32S, mkexpr(rounding_mode), mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_64_TO_INT_32, op, rounding_mode); - return "cfdtr"; } -static const HChar * +static void s390_irgen_CFXTR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cfxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r2)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12162,10 +10730,9 @@ s390_irgen_CFXTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D128toI32S, mkexpr(rounding_mode), mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_128_TO_INT_32, op, rounding_mode); - return "cfxtr"; } -static const HChar * +static void s390_irgen_CGDTRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) @@ -12176,13 +10743,12 @@ s390_irgen_CGDTRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(op, get_dpr_dw0(r2)); put_gpr_dw0(r1, binop(Iop_D64toI64S, mkexpr(rounding_mode), mkexpr(op))); s390_cc_thunk_putFZ(S390_CC_OP_DFP_64_TO_INT_64, op, rounding_mode); - return "cgdtra"; } -static const HChar * +static void s390_irgen_CGXTRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cgxtra", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r2)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12192,10 +10758,9 @@ s390_irgen_CGXTRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(op, get_dpr_pair(r2)); put_gpr_dw0(r1, binop(Iop_D128toI64S, mkexpr(rounding_mode), mkexpr(op))); s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_128_TO_INT_64, op, rounding_mode); - return "cgxtra"; } -static const HChar * +static void s390_irgen_CEDTR(UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -12209,14 +10774,13 @@ s390_irgen_CEDTR(UChar r1, UChar r2) assign(cc_s390, convert_vex_dfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - return "cedtr"; } -static const HChar * +static void s390_irgen_CEXTR(UChar r1, UChar r2) { - s390_insn_assert("cextr", is_valid_fpr_pair(r1)); - s390_insn_assert("cextr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -12229,10 +10793,9 @@ s390_irgen_CEXTR(UChar r1, UChar r2) assign(cc_s390, convert_vex_dfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - return "cextr"; } -static const HChar * +static void s390_irgen_CLFDTR(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) @@ -12245,13 +10808,12 @@ s390_irgen_CLFDTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D64toI32U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_64_TO_UINT_32, op, rounding_mode); - return "clfdtr"; } -static const HChar * +static void s390_irgen_CLFXTR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clfxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r2)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12263,10 +10825,9 @@ s390_irgen_CLFXTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D128toI32U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_128_TO_UINT_32, op, rounding_mode); - return "clfxtr"; } -static const HChar * +static void s390_irgen_CLGDTR(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) @@ -12279,13 +10840,12 @@ s390_irgen_CLGDTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D64toI64U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_64_TO_UINT_64, op, rounding_mode); - return "clgdtr"; } -static const HChar * +static void s390_irgen_CLGXTR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clgxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r2)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -12297,10 +10857,9 @@ s390_irgen_CLGXTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D128toI64U, mkexpr(rounding_mode), mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_128_TO_UINT_64, op, rounding_mode); - return "clgxtr"; } -static const HChar * +static void s390_irgen_DDTRA(UChar r3, UChar m4, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -12314,15 +10873,14 @@ s390_irgen_DDTRA(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_DivD64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_dw0(r1, mkexpr(result)); - return "ddtra"; } -static const HChar * +static void s390_irgen_DXTRA(UChar r3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("dxtra", is_valid_fpr_pair(r1)); - s390_insn_assert("dxtra", is_valid_fpr_pair(r2)); - s390_insn_assert("dxtra", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -12335,42 +10893,37 @@ s390_irgen_DXTRA(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_DivD128, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_pair(r1, mkexpr(result)); - return "dxtra"; } -static const HChar * +static void s390_irgen_EEDTR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_ExtractExpD64, get_dpr_dw0(r2))); - return "eedtr"; } -static const HChar * +static void s390_irgen_EEXTR(UChar r1, UChar r2) { - s390_insn_assert("eextr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r2)); put_gpr_dw0(r1, unop(Iop_ExtractExpD128, get_dpr_pair(r2))); - return "eextr"; } -static const HChar * +static void s390_irgen_ESDTR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_ExtractSigD64, get_dpr_dw0(r2))); - return "esdtr"; } -static const HChar * +static void s390_irgen_ESXTR(UChar r1, UChar r2) { - s390_insn_assert("esxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r2)); put_gpr_dw0(r1, unop(Iop_ExtractSigD128, get_dpr_pair(r2))); - return "esxtr"; } -static const HChar * +static void s390_irgen_IEDTR(UChar r3, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I64); @@ -12381,14 +10934,13 @@ s390_irgen_IEDTR(UChar r3, UChar r1, UChar r2) assign(op2, get_dpr_dw0(r3)); assign(result, binop(Iop_InsertExpD64, mkexpr(op1), mkexpr(op2))); put_dpr_dw0(r1, mkexpr(result)); - return "iedtr"; } -static const HChar * +static void s390_irgen_IEXTR(UChar r3, UChar r1, UChar r2) { - s390_insn_assert("iextr", is_valid_fpr_pair(r1)); - s390_insn_assert("iextr", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_I64); IRTemp op2 = newTemp(Ity_D128); @@ -12398,10 +10950,9 @@ s390_irgen_IEXTR(UChar r3, UChar r1, UChar r2) assign(op2, get_dpr_pair(r3)); assign(result, binop(Iop_InsertExpD128, mkexpr(op1), mkexpr(op2))); put_dpr_pair(r1, mkexpr(result)); - return "iextr"; } -static const HChar * +static void s390_irgen_LDETR(UChar m4, UChar r1, UChar r2) { if ((m4 & 0x8) != 0) @@ -12410,28 +10961,26 @@ s390_irgen_LDETR(UChar m4, UChar r1, UChar r2) assign(op, get_dpr_w0(r2)); put_dpr_dw0(r1, unop(Iop_D32toD64, mkexpr(op))); - return "ldetr"; } -static const HChar * +static void s390_irgen_LXDTR(UChar m4, UChar r1, UChar r2) { if ((m4 & 0x8) != 0) emulation_warning(EmWarn_S390X_XiC_not_zero); - s390_insn_assert("lxdtr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp op = newTemp(Ity_D64); assign(op, get_dpr_dw0(r2)); put_dpr_pair(r1, unop(Iop_D64toD128, mkexpr(op))); - return "lxdtr"; } -static const HChar * +static void s390_irgen_LDXTR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("ldxtr", is_valid_fpr_pair(r1)); - s390_insn_assert("ldxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); if ((m4 & 0x8) != 0) emulation_warning(EmWarn_S390X_XiC_not_zero); @@ -12442,10 +10991,9 @@ s390_irgen_LDXTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_D128toD64, mkexpr(encode_dfp_rounding_mode(m3)), get_dpr_pair(r2))); put_dpr_dw0(r1, mkexpr(result)); - return "ldxtr"; } -static const HChar * +static void s390_irgen_LEDTR(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x8) != 0) @@ -12457,10 +11005,9 @@ s390_irgen_LEDTR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op, get_dpr_dw0(r2)); put_dpr_w0(r1, binop(Iop_D64toD32, mkexpr(encode_dfp_rounding_mode(m3)), mkexpr(op))); - return "ledtr"; } -static const HChar * +static void s390_irgen_LTDTR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_D64); @@ -12468,24 +11015,22 @@ s390_irgen_LTDTR(UChar r1, UChar r2) assign(result, get_dpr_dw0(r2)); put_dpr_dw0(r1, mkexpr(result)); s390_cc_thunk_putF(S390_CC_OP_DFP_RESULT_64, result); - return "ltdtr"; } -static const HChar * +static void s390_irgen_LTXTR(UChar r1, UChar r2) { - s390_insn_assert("ltxtr", is_valid_fpr_pair(r1)); - s390_insn_assert("ltxtr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp result = newTemp(Ity_D128); assign(result, get_dpr_pair(r2)); put_dpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1d128(S390_CC_OP_DFP_RESULT_128, result); - return "ltxtr"; } -static const HChar * +static void s390_irgen_MDTRA(UChar r3, UChar m4, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -12499,15 +11044,14 @@ s390_irgen_MDTRA(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_MulD64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_dw0(r1, mkexpr(result)); - return "mdtra"; } -static const HChar * +static void s390_irgen_MXTRA(UChar r3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("mxtra", is_valid_fpr_pair(r1)); - s390_insn_assert("mxtra", is_valid_fpr_pair(r2)); - s390_insn_assert("mxtra", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -12520,10 +11064,9 @@ s390_irgen_MXTRA(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_MulD128, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_pair(r1, mkexpr(result)); - return "mxtra"; } -static const HChar * +static void s390_irgen_QADTR(UChar r3, UChar m4, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -12537,15 +11080,14 @@ s390_irgen_QADTR(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_QuantizeD64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_dw0(r1, mkexpr(result)); - return "qadtr"; } -static const HChar * +static void s390_irgen_QAXTR(UChar r3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("qaxtr", is_valid_fpr_pair(r1)); - s390_insn_assert("qaxtr", is_valid_fpr_pair(r2)); - s390_insn_assert("qaxtr", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -12558,10 +11100,9 @@ s390_irgen_QAXTR(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_QuantizeD128, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_pair(r1, mkexpr(result)); - return "qaxtr"; } -static const HChar * +static void s390_irgen_RRDTR(UChar r3, UChar m4, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_I8); @@ -12575,14 +11116,13 @@ s390_irgen_RRDTR(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_SignificanceRoundD64, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_dw0(r1, mkexpr(result)); - return "rrdtr"; } -static const HChar * +static void s390_irgen_RRXTR(UChar r3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("rrxtr", is_valid_fpr_pair(r1)); - s390_insn_assert("rrxtr", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_I8); IRTemp op2 = newTemp(Ity_D128); @@ -12595,10 +11135,9 @@ s390_irgen_RRXTR(UChar r3, UChar m4, UChar r1, UChar r2) assign(result, triop(Iop_SignificanceRoundD128, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_dpr_pair(r1, mkexpr(result)); - return "rrxtr"; } -static const HChar * +static void s390_irgen_SDTRA(UChar r3, UChar m4, UChar r1, UChar r2) { IRTemp op1 = newTemp(Ity_D64); @@ -12613,15 +11152,14 @@ s390_irgen_SDTRA(UChar r3, UChar m4, UChar r1, UChar r2) mkexpr(op2))); s390_cc_thunk_putF(S390_CC_OP_DFP_RESULT_64, result); put_dpr_dw0(r1, mkexpr(result)); - return "sdtra"; } -static const HChar * +static void s390_irgen_SXTRA(UChar r3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("sxtra", is_valid_fpr_pair(r1)); - s390_insn_assert("sxtra", is_valid_fpr_pair(r2)); - s390_insn_assert("sxtra", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op1 = newTemp(Ity_D128); IRTemp op2 = newTemp(Ity_D128); @@ -12635,10 +11173,9 @@ s390_irgen_SXTRA(UChar r3, UChar m4, UChar r1, UChar r2) mkexpr(op2))); put_dpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1d128(S390_CC_OP_DFP_RESULT_128, result); - return "sxtra"; } -static const HChar * +static void s390_irgen_SLDT(UChar r3, IRTemp op2addr, UChar r1) { IRTemp op = newTemp(Ity_D64); @@ -12647,14 +11184,13 @@ s390_irgen_SLDT(UChar r3, IRTemp op2addr, UChar r1) put_dpr_dw0(r1, binop(Iop_ShlD64, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - return "sldt"; } -static const HChar * +static void s390_irgen_SLXT(UChar r3, IRTemp op2addr, UChar r1) { - s390_insn_assert("slxt", is_valid_fpr_pair(r1)); - s390_insn_assert("slxt", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op = newTemp(Ity_D128); @@ -12662,10 +11198,9 @@ s390_irgen_SLXT(UChar r3, IRTemp op2addr, UChar r1) put_dpr_pair(r1, binop(Iop_ShlD128, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - return "slxt"; } -static const HChar * +static void s390_irgen_SRDT(UChar r3, IRTemp op2addr, UChar r1) { IRTemp op = newTemp(Ity_D64); @@ -12674,14 +11209,13 @@ s390_irgen_SRDT(UChar r3, IRTemp op2addr, UChar r1) put_dpr_dw0(r1, binop(Iop_ShrD64, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - return "srdt"; } -static const HChar * +static void s390_irgen_SRXT(UChar r3, IRTemp op2addr, UChar r1) { - s390_insn_assert("srxt", is_valid_fpr_pair(r1)); - s390_insn_assert("srxt", is_valid_fpr_pair(r3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r3)); IRTemp op = newTemp(Ity_D128); @@ -12689,10 +11223,9 @@ s390_irgen_SRXT(UChar r3, IRTemp op2addr, UChar r1) put_dpr_pair(r1, binop(Iop_ShrD128, mkexpr(op), unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(63))))); - return "srxt"; } -static const HChar * +static void s390_irgen_TDCET(UChar r1, IRTemp op2addr) { IRTemp value = newTemp(Ity_D32); @@ -12700,10 +11233,9 @@ s390_irgen_TDCET(UChar r1, IRTemp op2addr) assign(value, get_dpr_w0(r1)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_TDC_32, value, op2addr); - return "tdcet"; } -static const HChar * +static void s390_irgen_TDCDT(UChar r1, IRTemp op2addr) { IRTemp value = newTemp(Ity_D64); @@ -12711,23 +11243,21 @@ s390_irgen_TDCDT(UChar r1, IRTemp op2addr) assign(value, get_dpr_dw0(r1)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_TDC_64, value, op2addr); - return "tdcdt"; } -static const HChar * +static void s390_irgen_TDCXT(UChar r1, IRTemp op2addr) { - s390_insn_assert("tdcxt", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp value = newTemp(Ity_D128); assign(value, get_dpr_pair(r1)); s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_TDC_128, value, op2addr); - return "tdcxt"; } -static const HChar * +static void s390_irgen_TDGET(UChar r1, IRTemp op2addr) { IRTemp value = newTemp(Ity_D32); @@ -12735,10 +11265,9 @@ s390_irgen_TDGET(UChar r1, IRTemp op2addr) assign(value, get_dpr_w0(r1)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_TDG_32, value, op2addr); - return "tdget"; } -static const HChar * +static void s390_irgen_TDGDT(UChar r1, IRTemp op2addr) { IRTemp value = newTemp(Ity_D64); @@ -12746,23 +11275,21 @@ s390_irgen_TDGDT(UChar r1, IRTemp op2addr) assign(value, get_dpr_dw0(r1)); s390_cc_thunk_putFZ(S390_CC_OP_DFP_TDG_64, value, op2addr); - return "tdgdt"; } -static const HChar * +static void s390_irgen_TDGXT(UChar r1, IRTemp op2addr) { - s390_insn_assert("tdgxt", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp value = newTemp(Ity_D128); assign(value, get_dpr_pair(r1)); s390_cc_thunk_put1d128Z(S390_CC_OP_DFP_TDG_128, value, op2addr); - return "tdgxt"; } -static const HChar * +static void s390_irgen_CLC(UChar length, IRTemp start1, IRTemp start2) { IRType ty; @@ -12787,14 +11314,13 @@ s390_irgen_CLC(UChar length, IRTemp start1, IRTemp start2) assign(len, mkU64(length)); s390_irgen_CLC_EX(len, start1, start2); } - return "clc"; } -static const HChar * +static void s390_irgen_CLCL(UChar r1, UChar r2) { - s390_insn_assert("clcl", is_valid_gpr_pair(r1)); - s390_insn_assert("clcl", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr1 = newTemp(Ity_I64); IRTemp addr2 = newTemp(Ity_I64); @@ -12869,15 +11395,13 @@ s390_irgen_CLCL(UChar r1, UChar r2) binop(Iop_Sub32, mkexpr(r2p1), mkU32(1)))); iterate(); - - return "clcl"; } -static const HChar * +static void s390_irgen_CLCLE(UChar r1, UChar r3, IRTemp pad2) { - s390_insn_assert("clcle", is_valid_gpr_pair(r1)); - s390_insn_assert("clcle", is_valid_gpr_pair(r3)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r3)); IRTemp addr1, addr3, addr1_load, addr3_load, len1, len3, single1, single3; @@ -12946,8 +11470,6 @@ s390_irgen_CLCLE(UChar r1, UChar r3, IRTemp pad2) mkU64(0), binop(Iop_Sub64, mkexpr(len3), mkU64(1)))); iterate(); - - return "clcle"; } @@ -13096,7 +11618,7 @@ s390_irgen_EX_SS(UChar r, IRTemp addr2, IRTemp torun, last_execute_target = Invalid_execute_target; } -static const HChar * +static void s390_irgen_EX(UChar r1, IRTemp addr2) { IRTemp insn0, unmodified_insn; @@ -13135,44 +11657,44 @@ s390_irgen_EX(UChar r1, IRTemp addr2) put_IA(mkaddr_expr(guest_IA_next_instr)); dis_res->whatNext = Dis_StopHere; dis_res->jk_StopHere = Ijk_InvalICache; - return "ex"; + return; } switch (last_execute_target & 0xff00000000000000ULL) { case 0xd200000000000000ULL: /* special case MVC */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_MVC_EX, 64); - return "ex@mvc"; + return; case 0xd500000000000000ULL: /* special case CLC */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_CLC_EX, 64); - return "ex@clc"; + return; case 0xd700000000000000ULL: /* special case XC */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_XC_EX, 32); - return "ex@xc"; + return; case 0xd600000000000000ULL: /* special case OC */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_OC_EX, 32); - return "ex@oc"; + return; case 0xd400000000000000ULL: /* special case NC */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_NC_EX, 32); - return "ex@nc"; + return; case 0xdc00000000000000ULL: /* special case TR */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_TR_EX, 64); - return "ex@tr"; + return; case 0xe800000000000000ULL: /* special case MVCIN */ s390_irgen_EX_SS(r1, addr2, unmodified_insn, s390_irgen_MVCIN_EX, 64); - return "ex@mvcin"; + return; default: { @@ -13218,16 +11740,13 @@ s390_irgen_EX(UChar r1, IRTemp addr2) bytes = (UChar *) &last_execute_target; s390_decode_and_irgen(bytes, ((((bytes[0] >> 6) + 1) >> 1) + 1) << 1, dis_res); - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - vex_printf(" which was executed by\n"); /* dont make useless translations in the next execute */ last_execute_target = Invalid_execute_target; } } - return "ex"; } -static const HChar * +static void s390_irgen_EXRL(UChar r1, UInt offset) { IRTemp addr = newTemp(Ity_I64); @@ -13247,21 +11766,18 @@ s390_irgen_EXRL(UChar r1, UInt offset) bytes_addr = guest_IA_rel_base; assign(addr, mkU64(bytes_addr)); s390_irgen_EX(r1, addr); - return "exrl"; } -static const HChar * +static void s390_irgen_IPM(UChar r1) { // As long as we dont support SPM, lets just assume 0 as program mask put_gpr_b4(r1, unop(Iop_32to8, binop(Iop_Or32, mkU32(0 /* program mask */), binop(Iop_Shl32, s390_call_calculate_cc(), mkU8(4))))); - - return "ipm"; } -static const HChar * +static void s390_irgen_SRST(UChar r1, UChar r2) { IRTemp address = newTemp(Ity_I64); @@ -13295,11 +11811,9 @@ s390_irgen_SRST(UChar r1, UChar r2) put_gpr_dw0(r2, binop(Iop_Add64, mkexpr(address), mkU64(1))); iterate(); - - return "srst"; } -static const HChar * +static void s390_irgen_CLST(UChar r1, UChar r2) { IRTemp address1 = newTemp(Ity_I64); @@ -13353,8 +11867,6 @@ s390_irgen_CLST(UChar r1, UChar r2) put_gpr_dw0(r2, binop(Iop_Add64, get_gpr_dw0(r2), mkU64(1))); iterate(); - - return "clst"; } static void @@ -13376,23 +11888,19 @@ s390_irgen_load_multiple_32bit(UChar r1, UChar r3, IRTemp op2addr) } while (reg != (r3 + 1)); } -static const HChar * +static void s390_irgen_LM(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_multiple_32bit(r1, r3, op2addr); - - return "lm"; } -static const HChar * +static void s390_irgen_LMY(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_multiple_32bit(r1, r3, op2addr); - - return "lmy"; } -static const HChar * +static void s390_irgen_LMH(UChar r1, UChar r3, IRTemp op2addr) { UChar reg; @@ -13409,11 +11917,9 @@ s390_irgen_LMH(UChar r1, UChar r3, IRTemp op2addr) assign(addr, binop(Iop_Add64, mkexpr(old), mkU64(4))); reg++; } while (reg != (r3 + 1)); - - return "lmh"; } -static const HChar * +static void s390_irgen_LMG(UChar r1, UChar r3, IRTemp op2addr) { UChar reg; @@ -13430,8 +11936,6 @@ s390_irgen_LMG(UChar r1, UChar r3, IRTemp op2addr) assign(addr, binop(Iop_Add64, mkexpr(old), mkU64(8))); reg++; } while (reg != (r3 + 1)); - - return "lmg"; } static void @@ -13453,23 +11957,19 @@ s390_irgen_store_multiple_32bit(UChar r1, UChar r3, IRTemp op2addr) } while( reg != (r3 + 1)); } -static const HChar * +static void s390_irgen_STM(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_store_multiple_32bit(r1, r3, op2addr); - - return "stm"; } -static const HChar * +static void s390_irgen_STMY(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_store_multiple_32bit(r1, r3, op2addr); - - return "stmy"; } -static const HChar * +static void s390_irgen_STMH(UChar r1, UChar r3, IRTemp op2addr) { UChar reg; @@ -13486,11 +11986,9 @@ s390_irgen_STMH(UChar r1, UChar r3, IRTemp op2addr) assign(addr, binop(Iop_Add64, mkexpr(old), mkU64(4))); reg++; } while( reg != (r3 + 1)); - - return "stmh"; } -static const HChar * +static void s390_irgen_STMG(UChar r1, UChar r3, IRTemp op2addr) { UChar reg; @@ -13507,8 +12005,6 @@ s390_irgen_STMG(UChar r1, UChar r3, IRTemp op2addr) assign(addr, binop(Iop_Add64, mkexpr(old), mkU64(8))); reg++; } while( reg != (r3 + 1)); - - return "stmg"; } static void @@ -13548,15 +12044,13 @@ s390_irgen_xonc(IROp op, IRTemp length, IRTemp start1, IRTemp start2) put_counter_dw0(mkU64(0)); } -static const HChar * +static void s390_irgen_XC(UChar length, IRTemp start1, IRTemp start2) { IRTemp len = newTemp(Ity_I32); assign(len, mkU32(length)); s390_irgen_xonc(Iop_Xor8, len, start1, start2); - - return "xc"; } static void @@ -13592,57 +12086,46 @@ s390_irgen_XC_sameloc(UChar length, UChar b, UShort d) } s390_cc_set_val(0); - - if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) - S390_DISASM(MNM("xc"), UDLB(d, length, b), UDXB(d, 0, b)); } -static const HChar * +static void s390_irgen_NC(UChar length, IRTemp start1, IRTemp start2) { IRTemp len = newTemp(Ity_I32); assign(len, mkU32(length)); s390_irgen_xonc(Iop_And8, len, start1, start2); - - return "nc"; } -static const HChar * +static void s390_irgen_OC(UChar length, IRTemp start1, IRTemp start2) { IRTemp len = newTemp(Ity_I32); assign(len, mkU32(length)); s390_irgen_xonc(Iop_Or8, len, start1, start2); - - return "oc"; } -static const HChar * +static void s390_irgen_MVC(UChar length, IRTemp start1, IRTemp start2) { IRTemp len = newTemp(Ity_I64); assign(len, mkU64(length)); s390_irgen_MVC_EX(len, start1, start2); - - return "mvc"; } -static const HChar * +static void s390_irgen_MVCIN(UChar length, IRTemp start1, IRTemp start2) { IRTemp len = newTemp(Ity_I64); assign(len, mkU64(length)); s390_irgen_MVCIN_EX(len, start1, start2); - - return "mvcin"; } -static const HChar * +static void s390_irgen_MVCRL(IRTemp op1addr, IRTemp op2addr) { IRTemp counter = newTemp(Ity_I64); @@ -13663,15 +12146,13 @@ s390_irgen_MVCRL(IRTemp op1addr, IRTemp op2addr) put_counter_dw0(binop(Iop_Add64, mkexpr(counter), mkU64(1))); iterate_if(binop(Iop_CmpNE64, mkexpr(offset), mkU64(0))); put_counter_dw0(mkU64(0)); - - return "mvcrl"; } -static const HChar * +static void s390_irgen_MVCL(UChar r1, UChar r2) { - s390_insn_assert("mvcl", is_valid_gpr_pair(r1)); - s390_insn_assert("mvcl", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr1 = newTemp(Ity_I64); IRTemp addr2 = newTemp(Ity_I64); @@ -13748,16 +12229,14 @@ s390_irgen_MVCL(UChar r1, UChar r2) s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, len1, len2, False); iterate_if(binop(Iop_CmpNE32, mkexpr(len1), mkU32(1))); - - return "mvcl"; } -static const HChar * +static void s390_irgen_MVCLE(UChar r1, UChar r3, IRTemp pad2) { - s390_insn_assert("mvcle", is_valid_gpr_pair(r1)); - s390_insn_assert("mvcle", is_valid_gpr_pair(r3)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r3)); IRTemp addr1, addr3, addr3_load, len1, len3, single; @@ -13805,11 +12284,9 @@ s390_irgen_MVCLE(UChar r1, UChar r3, IRTemp pad2) s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, len1, len3, False); iterate_if(binop(Iop_CmpNE64, mkexpr(len1), mkU64(1))); - - return "mvcle"; } -static const HChar * +static void s390_irgen_MVST(UChar r1, UChar r2) { IRTemp addr1 = newTemp(Ity_I64); @@ -13833,8 +12310,6 @@ s390_irgen_MVST(UChar r1, UChar r2) s390_cc_set_val(1); put_gpr_dw0(r1, binop(Iop_Add64, mkexpr(addr1), mkexpr(counter))); put_counter_dw0(mkU64(0)); - - return "mvst"; } static void @@ -13877,144 +12352,124 @@ s390_irgen_divide_64to64(IROp op, UChar r1, IRTemp op2) put_gpr_dw0(r1 + 1, unop(Iop_128to64, mkexpr(result))); // quotient } -static const HChar * +static void s390_irgen_DR(UChar r1, UChar r2) { - s390_insn_assert("dr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I32); assign(op2, get_gpr_w1(r2)); s390_irgen_divide_64to32(Iop_DivModS64to32, r1, op2); - - return "dr"; } -static const HChar * +static void s390_irgen_D(UChar r1, IRTemp op2addr) { - s390_insn_assert("d", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I32); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_irgen_divide_64to32(Iop_DivModS64to32, r1, op2); - - return "d"; } -static const HChar * +static void s390_irgen_DLR(UChar r1, UChar r2) { - s390_insn_assert("dlr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I32); assign(op2, get_gpr_w1(r2)); s390_irgen_divide_64to32(Iop_DivModU64to32, r1, op2); - - return "dlr"; } -static const HChar * +static void s390_irgen_DL(UChar r1, IRTemp op2addr) { - s390_insn_assert("dl", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I32); assign(op2, load(Ity_I32, mkexpr(op2addr))); s390_irgen_divide_64to32(Iop_DivModU64to32, r1, op2); - - return "dl"; } -static const HChar * +static void s390_irgen_DLG(UChar r1, IRTemp op2addr) { - s390_insn_assert("dlg", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); assign(op2, load(Ity_I64, mkexpr(op2addr))); s390_irgen_divide_128to64(Iop_DivModU128to64, r1, op2); - - return "dlg"; } -static const HChar * +static void s390_irgen_DLGR(UChar r1, UChar r2) { - s390_insn_assert("dlgr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); assign(op2, get_gpr_dw0(r2)); s390_irgen_divide_128to64(Iop_DivModU128to64, r1, op2); - - return "dlgr"; } -static const HChar * +static void s390_irgen_DSGR(UChar r1, UChar r2) { - s390_insn_assert("dsgr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); assign(op2, get_gpr_dw0(r2)); s390_irgen_divide_64to64(Iop_DivModS64to64, r1, op2); - - return "dsgr"; } -static const HChar * +static void s390_irgen_DSG(UChar r1, IRTemp op2addr) { - s390_insn_assert("dsg", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); assign(op2, load(Ity_I64, mkexpr(op2addr))); s390_irgen_divide_64to64(Iop_DivModS64to64, r1, op2); - - return "dsg"; } -static const HChar * +static void s390_irgen_DSGFR(UChar r1, UChar r2) { - s390_insn_assert("dsgfr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); assign(op2, unop(Iop_32Sto64, get_gpr_w1(r2))); s390_irgen_divide_64to64(Iop_DivModS64to64, r1, op2); - - return "dsgfr"; } -static const HChar * +static void s390_irgen_DSGF(UChar r1, IRTemp op2addr) { - s390_insn_assert("dsgf", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp op2 = newTemp(Ity_I64); assign(op2, unop(Iop_32Sto64, load(Ity_I32, mkexpr(op2addr)))); s390_irgen_divide_64to64(Iop_DivModS64to64, r1, op2); - - return "dsgf"; } static void @@ -14036,20 +12491,16 @@ s390_irgen_load_ar_multiple(UChar r1, UChar r3, IRTemp op2addr) } while (reg != (r3 + 1)); } -static const HChar * +static void s390_irgen_LAM(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_ar_multiple(r1, r3, op2addr); - - return "lam"; } -static const HChar * +static void s390_irgen_LAMY(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_load_ar_multiple(r1, r3, op2addr); - - return "lamy"; } static void @@ -14071,20 +12522,16 @@ s390_irgen_store_ar_multiple(UChar r1, UChar r3, IRTemp op2addr) } while (reg != (r3 + 1)); } -static const HChar * +static void s390_irgen_STAM(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_store_ar_multiple(r1, r3, op2addr); - - return "stam"; } -static const HChar * +static void s390_irgen_STAMY(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_store_ar_multiple(r1, r3, op2addr); - - return "stamy"; } @@ -14119,23 +12566,19 @@ s390_irgen_cas_32(UChar r1, UChar r3, IRTemp op2addr) yield_if(mkexpr(nequal)); } -static const HChar * +static void s390_irgen_CS(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_cas_32(r1, r3, op2addr); - - return "cs"; } -static const HChar * +static void s390_irgen_CSY(UChar r1, UChar r3, IRTemp op2addr) { s390_irgen_cas_32(r1, r3, op2addr); - - return "csy"; } -static const HChar * +static void s390_irgen_CSG(UChar r1, UChar r3, IRTemp op2addr) { IRCAS *cas; @@ -14163,8 +12606,6 @@ s390_irgen_CSG(UChar r1, UChar r3, IRTemp op2addr) Otherwise, store the old_value from memory in r1 and yield. */ put_gpr_dw0(r1, mkite(mkexpr(nequal), mkexpr(old_mem), mkexpr(op1))); yield_if(mkexpr(nequal)); - - return "csg"; } /* Implementation for 32-bit compare-double-and-swap */ @@ -14210,31 +12651,27 @@ s390_irgen_cdas_32(UChar r1, UChar r3, IRTemp op2addr) yield_if(mkexpr(nequal)); } -static const HChar * +static void s390_irgen_CDS(UChar r1, UChar r3, IRTemp op2addr) { - s390_insn_assert("cds", is_valid_gpr_pair(r1)); - s390_insn_assert("cds", is_valid_gpr_pair(r3)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r3)); s390_irgen_cdas_32(r1, r3, op2addr); - - return "cds"; } -static const HChar * +static void s390_irgen_CDSY(UChar r1, UChar r3, IRTemp op2addr) { - s390_insn_assert("cdsy", is_valid_gpr_pair(r1)); - s390_insn_assert("cdsy", is_valid_gpr_pair(r3)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r3)); s390_irgen_cdas_32(r1, r3, op2addr); - - return "cdsy"; } -static const HChar * +static void s390_irgen_CDSG(UChar r1, UChar r3, IRTemp op2addr) { - s390_insn_assert("cdsg", is_valid_gpr_pair(r1)); - s390_insn_assert("cdsg", is_valid_gpr_pair(r3)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r3)); IRCAS *cas; IRTemp op1_high = newTemp(Ity_I64); @@ -14275,18 +12712,16 @@ s390_irgen_CDSG(UChar r1, UChar r3, IRTemp op2addr) put_gpr_dw0(r1, mkite(mkexpr(nequal), mkexpr(old_mem_high), mkexpr(op1_high))); put_gpr_dw0(r1+1, mkite(mkexpr(nequal), mkexpr(old_mem_low), mkexpr(op1_low))); yield_if(mkexpr(nequal)); - - return "cdsg"; } /* Binary floating point */ -static const HChar * +static void s390_irgen_AXBR(UChar r1, UChar r2) { - s390_insn_assert("axbr", is_valid_fpr_pair(r1)); - s390_insn_assert("axbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp op1 = newTemp(Ity_F128); IRTemp op2 = newTemp(Ity_F128); @@ -14300,14 +12735,12 @@ s390_irgen_AXBR(UChar r1, UChar r2) put_fpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1f128(S390_CC_OP_BFP_RESULT_128, result); - - return "axbr"; } /* Helper for "compare" insns CEBR, CDBR, CXBR, and their signalling counterparts. */ -static const HChar * -s390_irgen_CxBR(const HChar *mnem, UChar r1, UChar r2, IRType type, IROp cmp_op) +static void +s390_irgen_CxBR(UChar r1, UChar r2, IRType type, IROp cmp_op) { IRTemp op1 = newTemp(type); IRTemp op2 = newTemp(type); @@ -14320,54 +12753,53 @@ s390_irgen_CxBR(const HChar *mnem, UChar r1, UChar r2, IRType type, IROp cmp_op) assign(cc_s390, convert_vex_bfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - return mnem; } -static const HChar * +static void s390_irgen_CEBR(UChar r1, UChar r2) { - return s390_irgen_CxBR("cebr", r1, r2, Ity_F32, Iop_CmpF32); + s390_irgen_CxBR(r1, r2, Ity_F32, Iop_CmpF32); } -static const HChar * +static void s390_irgen_KEBR(UChar r1, UChar r2) { - return s390_irgen_CxBR("kebr", r1, r2, Ity_F32, Iop_CmpF32); + s390_irgen_CxBR(r1, r2, Ity_F32, Iop_CmpF32); } -static const HChar * +static void s390_irgen_CDBR(UChar r1, UChar r2) { - return s390_irgen_CxBR("cdbr", r1, r2, Ity_F64, Iop_CmpF64); + s390_irgen_CxBR(r1, r2, Ity_F64, Iop_CmpF64); } -static const HChar * +static void s390_irgen_KDBR(UChar r1, UChar r2) { - return s390_irgen_CxBR("kdbr", r1, r2, Ity_F64, Iop_CmpF64); + s390_irgen_CxBR(r1, r2, Ity_F64, Iop_CmpF64); } -static const HChar * +static void s390_irgen_CXBR(UChar r1, UChar r2) { - s390_insn_assert("cxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("cxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); - return s390_irgen_CxBR("cxbr", r1, r2, Ity_F128, Iop_CmpF128); + s390_irgen_CxBR(r1, r2, Ity_F128, Iop_CmpF128); } -static const HChar * +static void s390_irgen_KXBR(UChar r1, UChar r2) { - s390_insn_assert("kxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("kxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); - return s390_irgen_CxBR("kxbr", r1, r2, Ity_F128, Iop_CmpF128); + s390_irgen_CxBR(r1, r2, Ity_F128, Iop_CmpF128); } /* Helper for "compare" insns CEB, CDB, and their signalling counterparts. */ -static const HChar * -s390_irgen_CxB(const HChar *mnem, UChar r1, IRTemp op2addr, IRType type, +static void +s390_irgen_CxB(UChar r1, IRTemp op2addr, IRType type, IROp cmp_op) { IRTemp op1 = newTemp(type); @@ -14381,38 +12813,37 @@ s390_irgen_CxB(const HChar *mnem, UChar r1, IRTemp op2addr, IRType type, assign(cc_s390, convert_vex_bfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - return mnem; } -static const HChar * +static void s390_irgen_CEB(UChar r1, IRTemp op2addr) { - return s390_irgen_CxB("ceb", r1, op2addr, Ity_F32, Iop_CmpF32); + s390_irgen_CxB(r1, op2addr, Ity_F32, Iop_CmpF32); } -static const HChar * +static void s390_irgen_KEB(UChar r1, IRTemp op2addr) { - return s390_irgen_CxB("keb", r1, op2addr, Ity_F32, Iop_CmpF32); + s390_irgen_CxB(r1, op2addr, Ity_F32, Iop_CmpF32); } -static const HChar * +static void s390_irgen_CDB(UChar r1, IRTemp op2addr) { - return s390_irgen_CxB("cdb", r1, op2addr, Ity_F64, Iop_CmpF64); + s390_irgen_CxB(r1, op2addr, Ity_F64, Iop_CmpF64); } -static const HChar * +static void s390_irgen_KDB(UChar r1, IRTemp op2addr) { - return s390_irgen_CxB("kdb", r1, op2addr, Ity_F64, Iop_CmpF64); + s390_irgen_CxB(r1, op2addr, Ity_F64, Iop_CmpF64); } -static const HChar * +static void s390_irgen_CXFBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxfbra", is_valid_fpr_pair(r1)); - s390_insn_assert("cxfbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14420,15 +12851,13 @@ s390_irgen_CXFBRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_w1(r2)); put_fpr_pair(r1, unop(Iop_I32StoF128, mkexpr(op2))); - - return "cxfbra"; } -static const HChar * +static void s390_irgen_CXLFBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxlfbr", is_valid_fpr_pair(r1)); - s390_insn_assert("cxlfbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14436,15 +12865,14 @@ s390_irgen_CXLFBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_w1(r2)); put_fpr_pair(r1, unop(Iop_I32UtoF128, mkexpr(op2))); - return "cxlfbr"; } -static const HChar * +static void s390_irgen_CXGBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxgbra", is_valid_fpr_pair(r1)); - s390_insn_assert("cxgbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14452,15 +12880,13 @@ s390_irgen_CXGBRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_dw0(r2)); put_fpr_pair(r1, unop(Iop_I64StoF128, mkexpr(op2))); - - return "cxgbra"; } -static const HChar * +static void s390_irgen_CXLGBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cxlgbr", is_valid_fpr_pair(r1)); - s390_insn_assert("cxlgbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14468,14 +12894,13 @@ s390_irgen_CXLGBR(UChar m3, UChar m4, UChar r1, UChar r2) assign(op2, get_gpr_dw0(r2)); put_fpr_pair(r1, unop(Iop_I64UtoF128, mkexpr(op2))); - return "cxlgbr"; } -static const HChar * +static void s390_irgen_CFXBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cfxbra", is_valid_fpr_pair(r2)); - s390_insn_assert("cfxbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14488,15 +12913,13 @@ s390_irgen_CFXBRA(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_128_TO_INT_32, op, rounding_mode); - - return "cfxbra"; } -static const HChar * +static void s390_irgen_CLFXBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clfxbr", is_valid_fpr_pair(r2)); - s390_insn_assert("clfxbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14509,15 +12932,14 @@ s390_irgen_CLFXBR(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_w1(r1, mkexpr(result)); s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_128_TO_UINT_32, op, rounding_mode); - return "clfxbr"; } -static const HChar * +static void s390_irgen_CGXBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("cgxbra", is_valid_fpr_pair(r2)); - s390_insn_assert("cgxbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14530,15 +12952,13 @@ s390_irgen_CGXBRA(UChar m3, UChar m4, UChar r1, UChar r2) mkexpr(op))); put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_128_TO_INT_64, op, rounding_mode); - - return "cgxbra"; } -static const HChar * +static void s390_irgen_CLGXBR(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("clgxbr", is_valid_fpr_pair(r2)); - s390_insn_assert("clgxbr", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14552,14 +12972,13 @@ s390_irgen_CLGXBR(UChar m3, UChar m4, UChar r1, UChar r2) put_gpr_dw0(r1, mkexpr(result)); s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_128_TO_UINT_64, op, rounding_mode); - return "clgxbr"; } -static const HChar * +static void s390_irgen_DXBR(UChar r1, UChar r2) { - s390_insn_assert("dxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("dxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp op1 = newTemp(Ity_F128); IRTemp op2 = newTemp(Ity_F128); @@ -14571,96 +12990,82 @@ s390_irgen_DXBR(UChar r1, UChar r2) assign(result, triop(Iop_DivF128, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_pair(r1, mkexpr(result)); - - return "dxbr"; } -static const HChar * +static void s390_irgen_LTXBR(UChar r1, UChar r2) { - s390_insn_assert("ltxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("ltxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp result = newTemp(Ity_F128); assign(result, get_fpr_pair(r2)); put_fpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1f128(S390_CC_OP_BFP_RESULT_128, result); - - return "ltxbr"; } -static const HChar * +static void s390_irgen_LCXBR(UChar r1, UChar r2) { - s390_insn_assert("lcxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("lcxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp result = newTemp(Ity_F128); assign(result, unop(Iop_NegF128, get_fpr_pair(r2))); put_fpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1f128(S390_CC_OP_BFP_RESULT_128, result); - - return "lcxbr"; } -static const HChar * +static void s390_irgen_LXDBR(UChar r1, UChar r2) { - s390_insn_assert("lxdbr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp op = newTemp(Ity_F64); assign(op, get_fpr_dw0(r2)); put_fpr_pair(r1, unop(Iop_F64toF128, mkexpr(op))); - - return "lxdbr"; } -static const HChar * +static void s390_irgen_LXEBR(UChar r1, UChar r2) { - s390_insn_assert("lxebr", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp op = newTemp(Ity_F32); assign(op, get_fpr_w0(r2)); put_fpr_pair(r1, unop(Iop_F32toF128, mkexpr(op))); - - return "lxebr"; } -static const HChar * +static void s390_irgen_LXDB(UChar r1, IRTemp op2addr) { - s390_insn_assert("lxdb", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp op = newTemp(Ity_F64); assign(op, load(Ity_F64, mkexpr(op2addr))); put_fpr_pair(r1, unop(Iop_F64toF128, mkexpr(op))); - - return "lxdb"; } -static const HChar * +static void s390_irgen_LXEB(UChar r1, IRTemp op2addr) { - s390_insn_assert("lxeb", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp op = newTemp(Ity_F32); assign(op, load(Ity_F32, mkexpr(op2addr))); put_fpr_pair(r1, unop(Iop_F32toF128, mkexpr(op))); - - return "lxeb"; } -static const HChar * +static void s390_irgen_FIEBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("fiebra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14669,14 +13074,12 @@ s390_irgen_FIEBRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_RoundF32toInt, mkexpr(encode_bfp_rounding_mode(m3)), get_fpr_w0(r2))); put_fpr_w0(r1, mkexpr(result)); - - return "fiebra"; } -static const HChar * +static void s390_irgen_FIDBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("fidbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14685,16 +13088,14 @@ s390_irgen_FIDBRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_RoundF64toInt, mkexpr(encode_bfp_rounding_mode(m3)), get_fpr_dw0(r2))); put_fpr_dw0(r1, mkexpr(result)); - - return "fidbra"; } -static const HChar * +static void s390_irgen_FIXBRA(UChar m3, UChar m4, UChar r1, UChar r2) { - s390_insn_assert("fixbra", is_valid_fpr_pair(r1)); - s390_insn_assert("fixbra", is_valid_fpr_pair(r2)); - s390_insn_assert("fixbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); @@ -14703,11 +13104,9 @@ s390_irgen_FIXBRA(UChar m3, UChar m4, UChar r1, UChar r2) assign(result, binop(Iop_RoundF128toInt, mkexpr(encode_bfp_rounding_mode(m3)), get_fpr_pair(r2))); put_fpr_pair(r1, mkexpr(result)); - - return "fixbra"; } -static const HChar * +static void s390_irgen_LNEBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F32); @@ -14715,11 +13114,9 @@ s390_irgen_LNEBR(UChar r1, UChar r2) assign(result, unop(Iop_NegF32, unop(Iop_AbsF32, get_fpr_w0(r2)))); put_fpr_w0(r1, mkexpr(result)); s390_cc_thunk_put1f(S390_CC_OP_BFP_RESULT_32, result); - - return "lnebr"; } -static const HChar * +static void s390_irgen_LNDBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); @@ -14727,26 +13124,22 @@ s390_irgen_LNDBR(UChar r1, UChar r2) assign(result, unop(Iop_NegF64, unop(Iop_AbsF64, get_fpr_dw0(r2)))); put_fpr_dw0(r1, mkexpr(result)); s390_cc_thunk_put1f(S390_CC_OP_BFP_RESULT_64, result); - - return "lndbr"; } -static const HChar * +static void s390_irgen_LNXBR(UChar r1, UChar r2) { - s390_insn_assert("lnxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("lnxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp result = newTemp(Ity_F128); assign(result, unop(Iop_NegF128, unop(Iop_AbsF128, get_fpr_pair(r2)))); put_fpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1f128(S390_CC_OP_BFP_RESULT_128, result); - - return "lnxbr"; } -static const HChar * +static void s390_irgen_LPEBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F32); @@ -14754,11 +13147,9 @@ s390_irgen_LPEBR(UChar r1, UChar r2) assign(result, unop(Iop_AbsF32, get_fpr_w0(r2))); put_fpr_w0(r1, mkexpr(result)); s390_cc_thunk_put1f(S390_CC_OP_BFP_RESULT_32, result); - - return "lpebr"; } -static const HChar * +static void s390_irgen_LPDBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); @@ -14766,66 +13157,58 @@ s390_irgen_LPDBR(UChar r1, UChar r2) assign(result, unop(Iop_AbsF64, get_fpr_dw0(r2))); put_fpr_dw0(r1, mkexpr(result)); s390_cc_thunk_put1f(S390_CC_OP_BFP_RESULT_64, result); - - return "lpdbr"; } -static const HChar * +static void s390_irgen_LPXBR(UChar r1, UChar r2) { - s390_insn_assert("lpxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("lpxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp result = newTemp(Ity_F128); assign(result, unop(Iop_AbsF128, get_fpr_pair(r2))); put_fpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1f128(S390_CC_OP_BFP_RESULT_128, result); - - return "lpxbr"; } -static const HChar * +static void s390_irgen_LDXBRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); - s390_insn_assert("ldxbra", is_valid_fpr_pair(r1)); - s390_insn_assert("ldxbra", is_valid_fpr_pair(r2)); - s390_insn_assert("ldxbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); IRTemp result = newTemp(Ity_F64); assign(result, binop(Iop_F128toF64, mkexpr(encode_bfp_rounding_mode(m3)), get_fpr_pair(r2))); put_fpr_dw0(r1, mkexpr(result)); - - return "ldxbra"; } -static const HChar * +static void s390_irgen_LEXBRA(UChar m3, UChar m4, UChar r1, UChar r2) { if ((m4 & 0x4) != 0) emulation_warning(EmWarn_S390X_XxC_not_zero); - s390_insn_assert("lexbra", is_valid_fpr_pair(r1)); - s390_insn_assert("lexbra", is_valid_fpr_pair(r2)); - s390_insn_assert("lexbra", is_valid_rounding_mode(m3)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_rounding_mode(m3)); IRTemp result = newTemp(Ity_F32); assign(result, binop(Iop_F128toF32, mkexpr(encode_bfp_rounding_mode(m3)), get_fpr_pair(r2))); put_fpr_w0(r1, mkexpr(result)); - - return "lexbra"; } -static const HChar * +static void s390_irgen_MXBR(UChar r1, UChar r2) { - s390_insn_assert("mxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("mxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp op1 = newTemp(Ity_F128); IRTemp op2 = newTemp(Ity_F128); @@ -14837,33 +13220,27 @@ s390_irgen_MXBR(UChar r1, UChar r2) assign(result, triop(Iop_MulF128, mkexpr(rounding_mode), mkexpr(op1), mkexpr(op2))); put_fpr_pair(r1, mkexpr(result)); - - return "mxbr"; } -static const HChar * +static void s390_irgen_MAEBR(UChar r1, UChar r3, UChar r2) { IRTemp rounding_mode = encode_bfp_rounding_mode(S390_BFP_ROUND_PER_FPC); put_fpr_w0(r1, qop(Iop_MAddF32, mkexpr(rounding_mode), get_fpr_w0(r3), get_fpr_w0(r2), get_fpr_w0(r1))); - - return "maebr"; } -static const HChar * +static void s390_irgen_MADBR(UChar r1, UChar r3, UChar r2) { IRTemp rounding_mode = encode_bfp_rounding_mode(S390_BFP_ROUND_PER_FPC); put_fpr_dw0(r1, qop(Iop_MAddF64, mkexpr(rounding_mode), get_fpr_dw0(r3), get_fpr_dw0(r2), get_fpr_dw0(r1))); - - return "madbr"; } -static const HChar * +static void s390_irgen_MAEB(UChar r3, IRTemp op2addr, UChar r1) { IRExpr *op2 = load(Ity_F32, mkexpr(op2addr)); @@ -14871,11 +13248,9 @@ s390_irgen_MAEB(UChar r3, IRTemp op2addr, UChar r1) put_fpr_w0(r1, qop(Iop_MAddF32, mkexpr(rounding_mode), get_fpr_w0(r3), op2, get_fpr_w0(r1))); - - return "maeb"; } -static const HChar * +static void s390_irgen_MADB(UChar r3, IRTemp op2addr, UChar r1) { IRExpr *op2 = load(Ity_F64, mkexpr(op2addr)); @@ -14883,33 +13258,27 @@ s390_irgen_MADB(UChar r3, IRTemp op2addr, UChar r1) put_fpr_dw0(r1, qop(Iop_MAddF64, mkexpr(rounding_mode), get_fpr_dw0(r3), op2, get_fpr_dw0(r1))); - - return "madb"; } -static const HChar * +static void s390_irgen_MSEBR(UChar r1, UChar r3, UChar r2) { IRTemp rounding_mode = encode_bfp_rounding_mode(S390_BFP_ROUND_PER_FPC); put_fpr_w0(r1, qop(Iop_MSubF32, mkexpr(rounding_mode), get_fpr_w0(r3), get_fpr_w0(r2), get_fpr_w0(r1))); - - return "msebr"; } -static const HChar * +static void s390_irgen_MSDBR(UChar r1, UChar r3, UChar r2) { IRTemp rounding_mode = encode_bfp_rounding_mode(S390_BFP_ROUND_PER_FPC); put_fpr_dw0(r1, qop(Iop_MSubF64, mkexpr(rounding_mode), get_fpr_dw0(r3), get_fpr_dw0(r2), get_fpr_dw0(r1))); - - return "msdbr"; } -static const HChar * +static void s390_irgen_MSEB(UChar r3, IRTemp op2addr, UChar r1) { IRExpr *op2 = load(Ity_F32, mkexpr(op2addr)); @@ -14917,11 +13286,9 @@ s390_irgen_MSEB(UChar r3, IRTemp op2addr, UChar r1) put_fpr_w0(r1, qop(Iop_MSubF32, mkexpr(rounding_mode), get_fpr_w0(r3), op2, get_fpr_w0(r1))); - - return "mseb"; } -static const HChar * +static void s390_irgen_MSDB(UChar r3, IRTemp op2addr, UChar r1) { IRExpr *op2 = load(Ity_F64, mkexpr(op2addr)); @@ -14929,11 +13296,9 @@ s390_irgen_MSDB(UChar r3, IRTemp op2addr, UChar r1) put_fpr_dw0(r1, qop(Iop_MSubF64, mkexpr(rounding_mode), get_fpr_dw0(r3), op2, get_fpr_dw0(r1))); - - return "msdb"; } -static const HChar * +static void s390_irgen_SQEBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F32); @@ -14941,11 +13306,9 @@ s390_irgen_SQEBR(UChar r1, UChar r2) assign(result, binop(Iop_SqrtF32, mkexpr(rounding_mode), get_fpr_w0(r2))); put_fpr_w0(r1, mkexpr(result)); - - return "sqebr"; } -static const HChar * +static void s390_irgen_SQDBR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); @@ -14953,15 +13316,13 @@ s390_irgen_SQDBR(UChar r1, UChar r2) assign(result, binop(Iop_SqrtF64, mkexpr(rounding_mode), get_fpr_dw0(r2))); put_fpr_dw0(r1, mkexpr(result)); - - return "sqdbr"; } -static const HChar * +static void s390_irgen_SQXBR(UChar r1, UChar r2) { - s390_insn_assert("sqxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("sqxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp result = newTemp(Ity_F128); IRTemp rounding_mode = encode_bfp_rounding_mode(S390_BFP_ROUND_PER_FPC); @@ -14969,11 +13330,9 @@ s390_irgen_SQXBR(UChar r1, UChar r2) assign(result, binop(Iop_SqrtF128, mkexpr(rounding_mode), get_fpr_pair(r2))); put_fpr_pair(r1, mkexpr(result)); - - return "sqxbr"; } -static const HChar * +static void s390_irgen_SQEB(UChar r1, IRTemp op2addr) { IRTemp op = newTemp(Ity_F32); @@ -14981,11 +13340,9 @@ s390_irgen_SQEB(UChar r1, IRTemp op2addr) assign(op, load(Ity_F32, mkexpr(op2addr))); put_fpr_w0(r1, binop(Iop_SqrtF32, mkexpr(rounding_mode), mkexpr(op))); - - return "sqeb"; } -static const HChar * +static void s390_irgen_SQDB(UChar r1, IRTemp op2addr) { IRTemp op = newTemp(Ity_F64); @@ -14993,15 +13350,13 @@ s390_irgen_SQDB(UChar r1, IRTemp op2addr) assign(op, load(Ity_F64, mkexpr(op2addr))); put_fpr_dw0(r1, binop(Iop_SqrtF64, mkexpr(rounding_mode), mkexpr(op))); - - return "sqdb"; } -static const HChar * +static void s390_irgen_SXBR(UChar r1, UChar r2) { - s390_insn_assert("sxbr", is_valid_fpr_pair(r1)); - s390_insn_assert("sxbr", is_valid_fpr_pair(r2)); + s390_insn_assert(is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r2)); IRTemp op1 = newTemp(Ity_F128); IRTemp op2 = newTemp(Ity_F128); @@ -15014,11 +13369,9 @@ s390_irgen_SXBR(UChar r1, UChar r2) mkexpr(op2))); put_fpr_pair(r1, mkexpr(result)); s390_cc_thunk_put1f128(S390_CC_OP_BFP_RESULT_128, result); - - return "sxbr"; } -static const HChar * +static void s390_irgen_TCEB(UChar r1, IRTemp op2addr) { IRTemp value = newTemp(Ity_F32); @@ -15026,11 +13379,9 @@ s390_irgen_TCEB(UChar r1, IRTemp op2addr) assign(value, get_fpr_w0(r1)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_TDC_32, value, op2addr); - - return "tceb"; } -static const HChar * +static void s390_irgen_TCDB(UChar r1, IRTemp op2addr) { IRTemp value = newTemp(Ity_F64); @@ -15038,75 +13389,61 @@ s390_irgen_TCDB(UChar r1, IRTemp op2addr) assign(value, get_fpr_dw0(r1)); s390_cc_thunk_putFZ(S390_CC_OP_BFP_TDC_64, value, op2addr); - - return "tcdb"; } -static const HChar * +static void s390_irgen_TCXB(UChar r1, IRTemp op2addr) { - s390_insn_assert("tcxb", is_valid_fpr_pair(r1)); + s390_insn_assert(is_valid_fpr_pair(r1)); IRTemp value = newTemp(Ity_F128); assign(value, get_fpr_pair(r1)); s390_cc_thunk_put1f128Z(S390_CC_OP_BFP_TDC_128, value, op2addr); - - return "tcxb"; } -static const HChar * +static void s390_irgen_LCDFR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); assign(result, unop(Iop_NegF64, get_fpr_dw0(r2))); put_fpr_dw0(r1, mkexpr(result)); - - return "lcdfr"; } -static const HChar * +static void s390_irgen_LNDFR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); assign(result, unop(Iop_NegF64, unop(Iop_AbsF64, get_fpr_dw0(r2)))); put_fpr_dw0(r1, mkexpr(result)); - - return "lndfr"; } -static const HChar * +static void s390_irgen_LPDFR(UChar r1, UChar r2) { IRTemp result = newTemp(Ity_F64); assign(result, unop(Iop_AbsF64, get_fpr_dw0(r2))); put_fpr_dw0(r1, mkexpr(result)); - - return "lpdfr"; } -static const HChar * +static void s390_irgen_LDGR(UChar r1, UChar r2) { put_fpr_dw0(r1, unop(Iop_ReinterpI64asF64, get_gpr_dw0(r2))); - - return "ldgr"; } -static const HChar * +static void s390_irgen_LGDR(UChar r1, UChar r2) { put_gpr_dw0(r1, unop(Iop_ReinterpF64asI64, get_fpr_dw0(r2))); - - return "lgdr"; } -static const HChar * +static void s390_irgen_CPSDR(UChar r3, UChar r1, UChar r2) { IRTemp sign = newTemp(Ity_I64); @@ -15118,8 +13455,6 @@ s390_irgen_CPSDR(UChar r3, UChar r1, UChar r2) mkU64((1ULL << 63) - 1))); put_fpr_dw0(r1, unop(Iop_ReinterpI64asF64, binop(Iop_Or64, mkexpr(value), mkexpr(sign)))); - - return "cpsdr"; } @@ -15138,20 +13473,16 @@ s390_call_cvb(IRExpr *in) return call; } -static const HChar * +static void s390_irgen_CVB(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, s390_call_cvb(load(Ity_I64, mkexpr(op2addr)))); - - return "cvb"; } -static const HChar * +static void s390_irgen_CVBY(UChar r1, IRTemp op2addr) { put_gpr_w1(r1, s390_call_cvb(load(Ity_I64, mkexpr(op2addr)))); - - return "cvby"; } @@ -15170,26 +13501,22 @@ s390_call_cvd(IRExpr *in) return call; } -static const HChar * +static void s390_irgen_CVD(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), s390_call_cvd(unop(Iop_32Uto64, get_gpr_w1(r1)))); - - return "cvd"; } -static const HChar * +static void s390_irgen_CVDY(UChar r1, IRTemp op2addr) { store(mkexpr(op2addr), s390_call_cvd(get_gpr_w1(r1))); - - return "cvdy"; } -static const HChar * +static void s390_irgen_FLOGR(UChar r1, UChar r2) { - s390_insn_assert("flogr", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp input = newTemp(Ity_I64); IRTemp num = newTemp(Ity_I64); @@ -15227,14 +13554,12 @@ s390_irgen_FLOGR(UChar r1, UChar r2) /* Compare the original value as an unsigned integer with 0. */ s390_cc_thunk_put2(S390_CC_OP_UNSIGNED_COMPARE, input, mktemp(Ity_I64, mkU64(0)), False); - - return "flogr"; } -static const HChar * +static void s390_irgen_POPCNT(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("popcnt", (m3 & 7) == 0); + s390_insn_assert((m3 & 7) == 0); static const ULong masks[] = { 0x5555555555555555, 0x3333333333333333, 0x0F0F0F0F0F0F0F0F, @@ -15262,10 +13587,9 @@ s390_irgen_POPCNT(UChar m3, UChar r1, UChar r2) } s390_cc_thunk_putZ(S390_CC_OP_BITWISE, val); put_gpr_dw0(r1, mkexpr(val)); - return "popcnt"; } -static const HChar * +static void s390_irgen_STCK(IRTemp op2addr) { IRDirty *d; @@ -15279,10 +13603,9 @@ s390_irgen_STCK(IRTemp op2addr) d->mSize = 8; stmt(IRStmt_Dirty(d)); s390_cc_set(cc); - return "stck"; } -static const HChar * +static void s390_irgen_STCKF(IRTemp op2addr) { IRTemp cc = newTemp(Ity_I64); @@ -15295,10 +13618,9 @@ s390_irgen_STCKF(IRTemp op2addr) d->mSize = 8; stmt(IRStmt_Dirty(d)); s390_cc_set(cc); - return "stckf"; } -static const HChar * +static void s390_irgen_STCKE(IRTemp op2addr) { IRDirty *d; @@ -15312,20 +13634,18 @@ s390_irgen_STCKE(IRTemp op2addr) d->mSize = 16; stmt(IRStmt_Dirty(d)); s390_cc_set(cc); - return "stcke"; } -static const HChar * +static void s390_irgen_STFLE(UChar b2, UShort d2) { extension(S390_EXT_STFLE, b2 | (d2 << 8)); - return "stfle"; } -static const HChar * +static void s390_irgen_CKSM(UChar r1,UChar r2) { - s390_insn_assert("cksm", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr = newTemp(Ity_I64); IRTemp op = newTemp(Ity_I32); @@ -15384,14 +13704,12 @@ s390_irgen_CKSM(UChar r1,UChar r2) put_gpr_dw0(r2+1, binop(Iop_Sub64, mkexpr(len), mkexpr(inc))); iterate_if(binop(Iop_CmpNE64, mkexpr(len), mkU64(0))); - - return "cksm"; } -static const HChar * +static void s390_irgen_TROO(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("troo", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp src_addr, des_addr, tab_addr, src_len, test_byte; src_addr = newTemp(Ity_I64); @@ -15433,14 +13751,12 @@ s390_irgen_TROO(UChar m3, UChar r1, UChar r2) put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(1))); iterate(); - - return "troo"; } -static const HChar * +static void s390_irgen_TRTO(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("trto", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp src_addr, des_addr, tab_addr, src_len, test_byte; src_addr = newTemp(Ity_I64); @@ -15483,14 +13799,12 @@ s390_irgen_TRTO(UChar m3, UChar r1, UChar r2) put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(2))); iterate(); - - return "trto"; } -static const HChar * +static void s390_irgen_TROT(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("trot", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp src_addr, des_addr, tab_addr, src_len, test_byte; src_addr = newTemp(Ity_I64); @@ -15532,14 +13846,12 @@ s390_irgen_TROT(UChar m3, UChar r1, UChar r2) put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(1))); iterate(); - - return "trot"; } -static const HChar * +static void s390_irgen_TRTT(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("trtt", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp src_addr, des_addr, tab_addr, src_len, test_byte; src_addr = newTemp(Ity_I64); @@ -15582,25 +13894,21 @@ s390_irgen_TRTT(UChar m3, UChar r1, UChar r2) put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(2))); iterate(); - - return "trtt"; } -static const HChar * +static void s390_irgen_TR(UChar length, IRTemp start1, IRTemp start2) { IRTemp len = newTemp(Ity_I64); assign(len, mkU64(length)); s390_irgen_TR_EX(len, start1, start2); - - return "tr"; } -static const HChar * +static void s390_irgen_TRE(UChar r1,UChar r2) { - s390_insn_assert("tre", is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r1)); IRTemp src_addr, tab_addr, src_len, test_byte; src_addr = newTemp(Ity_I64); @@ -15637,8 +13945,6 @@ s390_irgen_TRE(UChar r1,UChar r2) put_gpr_dw0(r1+1, binop(Iop_Sub64, mkexpr(src_len), mkU64(1))); iterate(); - - return "tre"; } static IRExpr * @@ -15655,11 +13961,11 @@ s390_call_cu21(IRExpr *srcval, IRExpr *low_surrogate) return call; } -static const HChar * +static void s390_irgen_CU21(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("cu21", is_valid_gpr_pair(r1)); - s390_insn_assert("cu21", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr1 = newTemp(Ity_I64); IRTemp addr2 = newTemp(Ity_I64); @@ -15767,8 +14073,6 @@ s390_irgen_CU21(UChar m3, UChar r1, UChar r2) put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes))); iterate(); - - return "cu21"; } static IRExpr * @@ -15785,11 +14089,11 @@ s390_call_cu24(IRExpr *srcval, IRExpr *low_surrogate) return call; } -static const HChar * +static void s390_irgen_CU24(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("cu24", is_valid_gpr_pair(r1)); - s390_insn_assert("cu24", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr1 = newTemp(Ity_I64); IRTemp addr2 = newTemp(Ity_I64); @@ -15877,8 +14181,6 @@ s390_irgen_CU24(UChar m3, UChar r1, UChar r2) put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkU64(4))); iterate(); - - return "cu24"; } static IRExpr * @@ -15895,11 +14197,11 @@ s390_call_cu42(IRExpr *srcval) return call; } -static const HChar * +static void s390_irgen_CU42(UChar r1, UChar r2) { - s390_insn_assert("cu42", is_valid_gpr_pair(r1)); - s390_insn_assert("cu42", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr1 = newTemp(Ity_I64); IRTemp addr2 = newTemp(Ity_I64); @@ -15974,8 +14276,6 @@ s390_irgen_CU42(UChar r1, UChar r2) put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes))); iterate(); - - return "cu42"; } static IRExpr * @@ -15992,11 +14292,11 @@ s390_call_cu41(IRExpr *srcval) return call; } -static const HChar * +static void s390_irgen_CU41(UChar r1, UChar r2) { - s390_insn_assert("cu41", is_valid_gpr_pair(r1)); - s390_insn_assert("cu41", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); IRTemp addr1 = newTemp(Ity_I64); IRTemp addr2 = newTemp(Ity_I64); @@ -16068,8 +14368,6 @@ s390_irgen_CU41(UChar r1, UChar r2) put_gpr_dw0(r1 + 1, binop(Iop_Sub64, mkexpr(len1), mkexpr(num_bytes))); iterate(); - - return "cu41"; } static IRExpr * @@ -16242,26 +14540,22 @@ s390_irgen_cu12_cu14(UChar m3, UChar r1, UChar r2, Bool is_cu12) iterate(); } -static const HChar * +static void s390_irgen_CU12(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("cu12", is_valid_gpr_pair(r1)); - s390_insn_assert("cu12", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); s390_irgen_cu12_cu14(m3, r1, r2, /* is_cu12 = */ 1); - - return "cu12"; } -static const HChar * +static void s390_irgen_CU14(UChar m3, UChar r1, UChar r2) { - s390_insn_assert("cu14", is_valid_gpr_pair(r1)); - s390_insn_assert("cu14", is_valid_gpr_pair(r2)); + s390_insn_assert(is_valid_gpr_pair(r1)); + s390_insn_assert(is_valid_gpr_pair(r2)); s390_irgen_cu12_cu14(m3, r1, r2, /* is_cu12 = */ 0); - - return "cu14"; } static IRExpr * @@ -16279,139 +14573,114 @@ s390_call_ecag(IRExpr *op2addr) return call; } -static const HChar * +static void s390_irgen_ECAG(UChar r1, UChar r3 __attribute__((unused)), IRTemp op2addr) { put_gpr_dw0(r1, s390_call_ecag(mkexpr(op2addr))); - - return "ecag"; } -static const HChar * +static void s390_irgen_VL(UChar v1, IRTemp op2addr) { put_vr_qw(v1, load(Ity_V128, mkexpr(op2addr))); - - return "vl"; } -static const HChar * +static void s390_irgen_VLR(UChar v1, UChar v2) { put_vr_qw(v1, get_vr_qw(v2)); - - return "vlr"; } -static const HChar * +static void s390_irgen_VST(UChar v1, IRTemp op2addr) { store(mkexpr(op2addr), get_vr_qw(v1)); - - return "vst"; } -static const HChar * +static void s390_irgen_VLREP(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vlrep", m3 <= 3); + s390_insn_assert(m3 <= 3); IRType o2type = s390_vr_get_type(m3); IRExpr* o2 = load(o2type, mkexpr(op2addr)); s390_vr_fill(v1, o2); - return "vlrep"; } -static const HChar * +static void s390_irgen_VLEB(UChar v1, IRTemp op2addr, UChar m3) { /* Specification exception cannot occur. */ IRExpr* o2 = load(Ity_I8, mkexpr(op2addr)); put_vr(v1, Ity_I8, m3, o2); - - return "vleb"; } -static const HChar * +static void s390_irgen_VLEH(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vleh", m3 < 8); + s390_insn_assert(m3 < 8); IRExpr* o2 = load(Ity_I16, mkexpr(op2addr)); put_vr(v1, Ity_I16, m3, o2); - - return "vleh"; } -static const HChar * +static void s390_irgen_VLEF(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vlef", m3 < 4); + s390_insn_assert(m3 < 4); IRExpr* o2 = load(Ity_I32, mkexpr(op2addr)); put_vr(v1, Ity_I32, m3, o2); - - return "vlef"; } -static const HChar * +static void s390_irgen_VLEG(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vleg", m3 < 2); + s390_insn_assert(m3 < 2); IRExpr* o2 = load(Ity_I64, mkexpr(op2addr)); put_vr(v1, Ity_I64, m3, o2); - - return "vleg"; } -static const HChar * +static void s390_irgen_VLEIB(UChar v1, UShort i2, UChar m3) { /* Specification exception cannot occur. */ IRExpr* o2 = unop(Iop_16to8, mkU16(i2)); put_vr(v1, Ity_I8, m3, o2); - - return "vleib"; } -static const HChar * +static void s390_irgen_VLEIH(UChar v1, UShort i2, UChar m3) { - s390_insn_assert("vleih", m3 < 8); + s390_insn_assert(m3 < 8); IRExpr* o2 = mkU16(i2); put_vr(v1, Ity_I16, m3, o2); - - return "vleih"; } -static const HChar * +static void s390_irgen_VLEIF(UChar v1, UShort i2, UChar m3) { - s390_insn_assert("vleif", m3 < 4); + s390_insn_assert(m3 < 4); IRExpr* o2 = unop(Iop_16Sto32, mkU16(i2)); put_vr(v1, Ity_I32, m3, o2); - - return "vleif"; } -static const HChar * +static void s390_irgen_VLEIG(UChar v1, UShort i2, UChar m3) { - s390_insn_assert("vleig", m3 < 2); + s390_insn_assert(m3 < 2); IRExpr* o2 = unop(Iop_16Sto64, mkU16(i2)); put_vr(v1, Ity_I64, m3, o2); - - return "vleig"; } -static const HChar * +static void s390_irgen_VLGV(UChar r1, IRTemp op2addr, UChar v3, UChar m4) { - s390_insn_assert("vlgv", m4 <= 3); + s390_insn_assert(m4 <= 3); IRType o2type = s390_vr_get_type(m4); IRExpr* index = unop(Iop_64to8, binop(Iop_And64, mkexpr(op2addr), mkU64(0xf))); @@ -16439,21 +14708,18 @@ s390_irgen_VLGV(UChar r1, IRTemp op2addr, UChar v3, UChar m4) } put_gpr_dw0(r1, result); - return "vlgv"; } -static const HChar * +static void s390_irgen_VGBM(UChar v1, UShort i2) { put_vr_qw(v1, mkV128(i2)); - - return "vgbm"; } -static const HChar * +static void s390_irgen_VGM(UChar v1, UChar i2, UChar i3, UChar m4) { - s390_insn_assert("vgm", m4 <= 3); + s390_insn_assert(m4 <= 3); UChar max_idx = (8 << m4) - 1; UChar from = max_idx & i2; @@ -16487,13 +14753,12 @@ s390_irgen_VGM(UChar v1, UChar i2, UChar i3, UChar m4) } s390_vr_fill(v1, fillValue); - return "vgm"; } -static const HChar * +static void s390_irgen_VLLEZ(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vllez", m3 <= 3 || m3 == 6); + s390_insn_assert(m3 <= 3 || m3 == 6); IRType type = s390_vr_get_type(m3 & 3); IRExpr* op2 = load(type, mkexpr(op2addr)); @@ -16523,32 +14788,29 @@ s390_irgen_VLLEZ(UChar v1, IRTemp op2addr, UChar m3) put_vr_dw0(v1, op2as64bit); } put_vr_dw1(v1, mkU64(0)); - return "vllez"; } -static const HChar * +static void s390_irgen_VGEF(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vgef", m3 < 4); + s390_insn_assert(m3 < 4); put_vr(v1, Ity_I32, m3, load(Ity_I32, mkexpr(op2addr))); - return "vgef"; } -static const HChar * +static void s390_irgen_VGEG(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vgeg", m3 < 2); + s390_insn_assert(m3 < 2); put_vr(v1, Ity_I64, m3, load(Ity_I64, mkexpr(op2addr))); - return "vgeg"; } -static const HChar * +static void s390_irgen_VLM(UChar v1, IRTemp op2addr, UChar v3) { - s390_insn_assert("vlm", v3 >= v1); - s390_insn_assert("vlm", v3 - v1 <= 16); + s390_insn_assert(v3 >= v1); + s390_insn_assert(v3 - v1 <= 16); IRExpr* current = mkexpr(op2addr); @@ -16557,22 +14819,18 @@ s390_irgen_VLM(UChar v1, IRTemp op2addr, UChar v3) put_vr_qw(vr, load(Ity_V128, current)); current = next; } - - return "vlm"; } -static const HChar * +static void s390_irgen_VLVGP(UChar v1, UChar r2, UChar r3) { put_vr_qw(v1, binop(Iop_64HLtoV128, get_gpr_dw0(r2), get_gpr_dw0(r3))); - - return "vlvgp"; } -static const HChar * +static void s390_irgen_VLVG(UChar v1, IRTemp op2addr, UChar r3, UChar m4) { - s390_insn_assert("vlvg", m4 <= 3); + s390_insn_assert(m4 <= 3); IRType type = s390_vr_get_type(m4); IRExpr* index = unop(Iop_64to8, mkexpr(op2addr)); @@ -16598,85 +14856,73 @@ s390_irgen_VLVG(UChar v1, IRTemp op2addr, UChar r3, UChar m4) default: vpanic("s390_irgen_VLVG: unknown type"); } - - return "vlvg"; } -static const HChar * +static void s390_irgen_VMRH(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmrh", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_InterleaveHI8x16, Iop_InterleaveHI16x8, Iop_InterleaveHI32x4, Iop_InterleaveHI64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmrh"; } -static const HChar * +static void s390_irgen_VMRL(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmrl", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_InterleaveLO8x16, Iop_InterleaveLO16x8, Iop_InterleaveLO32x4, Iop_InterleaveLO64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmrl"; } -static const HChar * +static void s390_irgen_VPK(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vpk", m4 >= 1 && m4 <= 3); + s390_insn_assert(m4 >= 1 && m4 <= 3); const IROp ops[] = { Iop_NarrowBin16to8x16, Iop_NarrowBin32to16x8, Iop_NarrowBin64to32x4 }; Char index = m4 - 1; put_vr_qw(v1, binop(ops[index], get_vr_qw(v2), get_vr_qw(v3))); - return "vpk"; } -static const HChar * +static void s390_irgen_VPERM(UChar v1, UChar v2, UChar v3, UChar v4) { put_vr_qw(v1, triop(Iop_Perm8x16x2, get_vr_qw(v2), get_vr_qw(v3), get_vr_qw(v4))); - - return "vperm"; } -static const HChar * +static void s390_irgen_VSCEF(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vscef", m3 < 4); + s390_insn_assert(m3 < 4); store(mkexpr(op2addr), get_vr(v1, Ity_I32, m3)); - return "vscef"; } -static const HChar * +static void s390_irgen_VSCEG(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vsceg", m3 < 2); + s390_insn_assert(m3 < 2); store(mkexpr(op2addr), get_vr(v1, Ity_I64, m3)); - return "vsceg"; } -static const HChar * +static void s390_irgen_VPDI(UChar v1, UChar v2, UChar v3, UChar m4) { put_vr_qw(v1, binop(Iop_64HLtoV128, m4 & 4 ? get_vr_dw1(v2) : get_vr_dw0(v2), m4 & 1 ? get_vr_dw1(v3) : get_vr_dw0(v3))); - return "vpdi"; } -static const HChar * +static void s390_irgen_VSEG(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vseg", m3 <= 2); + s390_insn_assert(m3 <= 2); IRType type = s390_vr_get_type(m3); switch(type) { @@ -16696,54 +14942,44 @@ s390_irgen_VSEG(UChar v1, UChar v2, UChar m3) ppIRType(type); vpanic("s390_irgen_VSEG: unknown type"); } - - return "vseg"; } -static const HChar * +static void s390_irgen_VSTEB(UChar v1, IRTemp op2addr, UChar m3) { /* Specification exception cannot occur. */ store(mkexpr(op2addr), get_vr(v1, Ity_I8, m3)); - - return "vsteb"; } -static const HChar * +static void s390_irgen_VSTEH(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vsteh", m3 < 8); + s390_insn_assert(m3 < 8); store(mkexpr(op2addr), get_vr(v1, Ity_I16, m3)); - - return "vsteh"; } -static const HChar * +static void s390_irgen_VSTEF(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vstef", m3 < 8); + s390_insn_assert(m3 < 8); store(mkexpr(op2addr), get_vr(v1, Ity_I32, m3)); - - return "vstef"; } -static const HChar * +static void s390_irgen_VSTEG(UChar v1, IRTemp op2addr, UChar m3) { - s390_insn_assert("vsteg", m3 < 2); + s390_insn_assert(m3 < 2); store(mkexpr(op2addr), get_vr(v1, Ity_I64, m3)); - - return "vsteg"; } -static const HChar * +static void s390_irgen_VSTM(UChar v1, IRTemp op2addr, UChar v3) { - s390_insn_assert("vstm", v3 >= v1); - s390_insn_assert("vstm", v3 - v1 <= 16); + s390_insn_assert(v3 >= v1); + s390_insn_assert(v3 - v1 <= 16); IRExpr* current = mkexpr(op2addr); @@ -16752,71 +14988,60 @@ s390_irgen_VSTM(UChar v1, IRTemp op2addr, UChar v3) store(current, get_vr_qw(vr)); current = next; } - - return "vstm"; } -static const HChar * +static void s390_irgen_VUPH(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vuph", m3 <= 2); + s390_insn_assert(m3 <= 2); const IROp ops[] = { Iop_Widen8Sto16x8, Iop_Widen16Sto32x4, Iop_Widen32Sto64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_dw0(v2))); - - return "vuph"; } -static const HChar * +static void s390_irgen_VUPLH(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vuplh", m3 <= 2); + s390_insn_assert(m3 <= 2); const IROp ops[] = { Iop_Widen8Uto16x8, Iop_Widen16Uto32x4, Iop_Widen32Uto64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_dw0(v2))); - return "vuplh"; } -static const HChar * +static void s390_irgen_VUPL(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vupl", m3 <= 2); + s390_insn_assert(m3 <= 2); const IROp ops[] = { Iop_Widen8Sto16x8, Iop_Widen16Sto32x4, Iop_Widen32Sto64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_dw1(v2))); - - return "vupl"; } -static const HChar * +static void s390_irgen_VUPLL(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vupll", m3 <= 2); + s390_insn_assert(m3 <= 2); const IROp ops[] = { Iop_Widen8Uto16x8, Iop_Widen16Uto32x4, Iop_Widen32Uto64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_dw1(v2))); - - return "vupll"; } -static const HChar * +static void s390_irgen_VREP(UChar v1, UChar v3, UShort i2, UChar m4) { - s390_insn_assert("vrep", m4 <= 3); - s390_insn_assert("vrep", (m4 == 0 && i2 < 16) || (m4 == 1 && i2 < 8) || + s390_insn_assert(m4 <= 3); + s390_insn_assert((m4 == 0 && i2 < 16) || (m4 == 1 && i2 < 8) || (m4 == 2 && i2 < 4) || (m4 == 3 && i2 < 2)); IRType type = s390_vr_get_type(m4); IRExpr* arg = get_vr(v3, type, i2); s390_vr_fill(v1, arg); - - return "vrep"; } -static const HChar * +static void s390_irgen_VREPI(UChar v1, UShort i2, UChar m3) { - s390_insn_assert("vrepi", m3 <= 3); + s390_insn_assert(m3 <= 3); IRType type = s390_vr_get_type(m3); IRExpr *value; @@ -16838,14 +15063,12 @@ s390_irgen_VREPI(UChar v1, UShort i2, UChar m3) vpanic("s390_irgen_VREPI: unknown type"); } s390_vr_fill(v1, value); - - return "vrepi"; } -static const HChar * +static void s390_irgen_VPKS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vpks", m4 >= 1 && m4 <= 3); + s390_insn_assert(m4 >= 1 && m4 <= 3); if (!s390_vr_is_cs_set(m5)) { const IROp ops[] = { Iop_QNarrowBin16Sto8Sx16, Iop_QNarrowBin32Sto16Sx8, @@ -16885,14 +15108,12 @@ s390_irgen_VPKS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); } - - return "vpks"; } -static const HChar * +static void s390_irgen_VPKLS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vpkls", m4 >= 1 && m4 <= 3); + s390_insn_assert(m4 >= 1 && m4 <= 3); if (!s390_vr_is_cs_set(m5)) { const IROp ops[] = { Iop_QNarrowBin16Uto8Ux16, Iop_QNarrowBin32Uto16Ux8, @@ -16932,11 +15153,9 @@ s390_irgen_VPKLS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); } - - return "vpkls"; } -static const HChar * +static void s390_irgen_VSEL(UChar v1, UChar v2, UChar v3, UChar v4) { IRExpr* vIfTrue = get_vr_qw(v2); @@ -16944,190 +15163,160 @@ s390_irgen_VSEL(UChar v1, UChar v2, UChar v3, UChar v4) IRExpr* vCond = get_vr_qw(v4); put_vr_qw(v1, s390_V128_bitwiseITE(vCond, vIfTrue, vIfFalse)); - return "vsel"; } -static const HChar * +static void s390_irgen_VLBB(UChar v1, IRTemp addr, UChar m3) { - s390_insn_assert("vlbb", m3 <= 6); + s390_insn_assert(m3 <= 6); IRExpr* maxIndex = binop(Iop_Sub32, s390_getCountToBlockBoundary(addr, m3), mkU32(1)); s390_vr_loadWithLength(v1, addr, maxIndex, False); - - return "vlbb"; } -static const HChar * +static void s390_irgen_VLL(UChar v1, IRTemp addr, UChar r3) { s390_vr_loadWithLength(v1, addr, get_gpr_w1(r3), False); - - return "vll"; } -static const HChar * +static void s390_irgen_VLRL(UChar v1, IRTemp addr, UChar i3) { if (! s390_host_has_vxd) { emulation_failure(EmFail_S390X_vxd); - return "vlrl"; + return; } - s390_insn_assert("vlrl", (i3 & 0xf0) == 0); + s390_insn_assert((i3 & 0xf0) == 0); s390_vr_loadWithLength(v1, addr, mkU32((UInt) i3), True); - - return "vlrl"; } -static const HChar * +static void s390_irgen_VLRLR(UChar v1, UChar r3, IRTemp addr) { if (! s390_host_has_vxd) { emulation_failure(EmFail_S390X_vxd); - return "vlrlr"; + return; } s390_vr_loadWithLength(v1, addr, get_gpr_w1(r3), True); - - return "vlrlr"; } -static const HChar * +static void s390_irgen_VSTL(UChar v1, IRTemp addr, UChar r3) { s390_vr_storeWithLength(v1, addr, get_gpr_w1(r3), False); - return "vstl"; } -static const HChar * +static void s390_irgen_VSTRL(UChar v1, IRTemp addr, UChar i3) { if (! s390_host_has_vxd) { emulation_failure(EmFail_S390X_vxd); - return "vstrl"; + return; } - s390_insn_assert("vstrl", (i3 & 0xf0) == 0); + s390_insn_assert((i3 & 0xf0) == 0); s390_vr_storeWithLength(v1, addr, mkU32((UInt) i3), True); - return "vstrl"; } -static const HChar * +static void s390_irgen_VSTRLR(UChar v1, UChar r3, IRTemp addr) { if (! s390_host_has_vxd) { emulation_failure(EmFail_S390X_vxd); - return "vstrlr"; + return; } s390_vr_storeWithLength(v1, addr, get_gpr_w1(r3), True); - return "vstrlr"; } -static const HChar * +static void s390_irgen_VX(UChar v1, UChar v2, UChar v3) { put_vr_qw(v1, binop(Iop_XorV128, get_vr_qw(v2), get_vr_qw(v3))); - - return "vx"; } -static const HChar * +static void s390_irgen_VN(UChar v1, UChar v2, UChar v3) { put_vr_qw(v1, binop(Iop_AndV128, get_vr_qw(v2), get_vr_qw(v3))); - - return "vn"; } -static const HChar * +static void s390_irgen_VO(UChar v1, UChar v2, UChar v3) { put_vr_qw(v1, binop(Iop_OrV128, get_vr_qw(v2), get_vr_qw(v3))); - - return "vo"; } -static const HChar * +static void s390_irgen_VOC(UChar v1, UChar v2, UChar v3) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "voc"; + return; } put_vr_qw(v1, binop(Iop_OrV128, get_vr_qw(v2), unop(Iop_NotV128, get_vr_qw(v3)))); - - return "voc"; } -static const HChar * +static void s390_irgen_VNN(UChar v1, UChar v2, UChar v3) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vnn"; + return; } put_vr_qw(v1, unop(Iop_NotV128, binop(Iop_AndV128, get_vr_qw(v2), get_vr_qw(v3)))); - - return "vnn"; } -static const HChar * +static void s390_irgen_VNO(UChar v1, UChar v2, UChar v3) { put_vr_qw(v1, unop(Iop_NotV128, binop(Iop_OrV128, get_vr_qw(v2), get_vr_qw(v3)))); - - return "vno"; } -static const HChar * +static void s390_irgen_VNX(UChar v1, UChar v2, UChar v3) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vnx"; + return; } put_vr_qw(v1, unop(Iop_NotV128, binop(Iop_XorV128, get_vr_qw(v2), get_vr_qw(v3)))); - - return "vnx"; } -static const HChar * +static void s390_irgen_LZRF(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I32); assign(op2, binop(Iop_And32, load(Ity_I32, mkexpr(op2addr)), mkU32(0xffffff00))); put_gpr_w1(r1, mkexpr(op2)); - - return "lzrf"; } -static const HChar * +static void s390_irgen_LZRG(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I64); assign(op2, binop(Iop_And64, load(Ity_I64, mkexpr(op2addr)), mkU64(0xffffffffffffff00UL))); put_gpr_dw0(r1, mkexpr(op2)); - - return "lzrg"; } -static const HChar * +static void s390_irgen_LLZRGF(UChar r1, IRTemp op2addr) { IRTemp op2 = newTemp(Ity_I32); @@ -17135,68 +15324,54 @@ s390_irgen_LLZRGF(UChar r1, IRTemp op2addr) assign(op2, binop(Iop_And32, load(Ity_I32, mkexpr(op2addr)), mkU32(0xffffff00))); put_gpr_w1(r1, mkexpr(op2)); put_gpr_w0(r1, mkU32(0)); - - return "llzrgf"; } -static const HChar * +static void s390_irgen_LOCFH(UChar r1, IRTemp op2addr) { /* condition is checked in format handler */ put_gpr_w0(r1, load(Ity_I32, mkexpr(op2addr))); - - return "locfh"; } -static const HChar * +static void s390_irgen_LOCFHR(UChar m3, UChar r1, UChar r2) { next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0))); put_gpr_w0(r1, get_gpr_w0(r2)); - - return "locfhr"; } -static const HChar * +static void s390_irgen_LOCHHI(UChar r1, UChar m3, UShort i2) { next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0))); put_gpr_w0(r1, mkU32((UInt)(Int)(Short)i2)); - - return "lochhi"; } -static const HChar * +static void s390_irgen_LOCHI(UChar r1, UChar m3, UShort i2) { next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0))); put_gpr_w1(r1, mkU32((UInt)(Int)(Short)i2)); - - return "lochi"; } -static const HChar * +static void s390_irgen_LOCGHI(UChar r1, UChar m3, UShort i2) { next_insn_if(binop(Iop_CmpEQ32, s390_call_calculate_cond(m3), mkU32(0))); put_gpr_dw0(r1, mkU64((ULong)(Long)(Short)i2)); - - return "locghi"; } -static const HChar * +static void s390_irgen_STOCFH(UChar r1, IRTemp op2addr) { /* condition is checked in format handler */ store(mkexpr(op2addr), get_gpr_w1(r1)); - - return "stocfh"; } -static const HChar * +static void s390_irgen_LCBB(UChar r1, IRTemp op2addr, UChar m3) { - s390_insn_assert("lcbb", m3 <= 6); + s390_insn_assert(m3 <= 6); IRTemp op2 = newTemp(Ity_I32); assign(op2, s390_getCountToBlockBoundary(op2addr, m3)); @@ -17204,39 +15379,35 @@ s390_irgen_LCBB(UChar r1, IRTemp op2addr, UChar m3) IRExpr* cc = mkite(binop(Iop_CmpEQ32, mkexpr(op2), mkU32(16)), mkU64(0), mkU64(3)); s390_cc_thunk_fill(mkU64(S390_CC_OP_SET), cc, mkU64(0), mkU64(0)); - - return "lcbb"; } -static const HChar * +static void s390_irgen_PRNO(UChar r1, UChar r2) { if (!s390_host_has_msa5) { emulation_failure(EmFail_S390X_prno); - return "prno"; + return; } /* Check for obvious specification exceptions */ - s390_insn_assert("prno", r1 % 2 == 0 && r2 % 2 == 0 && r1 != 0 && r2 != 0); + s390_insn_assert(r1 % 2 == 0 && r2 % 2 == 0 && r1 != 0 && r2 != 0); extension(S390_EXT_PRNO, r1 | (r2 << 4)); - return "prno"; } -static const HChar * +static void s390_irgen_DFLTCC(UChar r3, UChar r1, UChar r2) { if (!s390_host_has_dflt) { emulation_failure(EmFail_S390X_dflt); - return "dfltcc"; + return; } /* Check for obvious specification exceptions */ - s390_insn_assert("dfltcc", r1 % 2 == 0 && r1 != 0 && + s390_insn_assert(r1 % 2 == 0 && r1 != 0 && r2 % 2 == 0 && r2 != 0 && r3 >= 2); extension(S390_EXT_DFLT, r1 | (r2 << 4) | (r3 << 8)); - return "dfltcc"; } enum s390_VStrX { @@ -17425,26 +15596,24 @@ s390_irgen_VStrX(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, dis_res->hint = Dis_HintVerbose; } -static const HChar * +static void s390_irgen_VFAE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vfae", m4 <= 2); + s390_insn_assert(m4 <= 2); s390_irgen_VStrX(v1, v2, v3, 255, m4, m5, s390_VStrX_VFAE); - return "vfae"; } -static const HChar * +static void s390_irgen_VFEE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vfee", m4 < 3 && m5 == (m5 & 3)); + s390_insn_assert(m4 < 3 && m5 == (m5 & 3)); s390_irgen_VStrX(v1, v2, v3, 255, m4, m5, s390_VStrX_VFEE); - return "vfee"; } -static const HChar * +static void s390_irgen_VFENE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vfene", m4 < 3 && m5 == (m5 & 3)); + s390_insn_assert(m4 < 3 && m5 == (m5 & 3)); static const IROp compare_op[3] = { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4 @@ -17524,13 +15693,12 @@ s390_irgen_VFENE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) s390_cc_set(cc); } dis_res->hint = Dis_HintVerbose; - return "vfene"; } -static const HChar * +static void s390_irgen_VISTR(UChar v1, UChar v2, UChar m3, UChar m5) { - s390_insn_assert("vistr", m3 < 3 && m5 == (m5 & 1)); + s390_insn_assert(m3 < 3 && m5 == (m5 & 1)); static const IROp compare_op[3] = { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4 @@ -17558,26 +15726,24 @@ s390_irgen_VISTR(UChar v1, UChar v2, UChar m3, UChar m5) s390_cc_set(cc); } dis_res->hint = Dis_HintVerbose; - return "vistr"; } -static const HChar * +static void s390_irgen_VSTRC(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { - s390_insn_assert("vstrc", m5 <= 2); + s390_insn_assert(m5 <= 2); s390_irgen_VStrX(v1, v2, v3, v4, m5, m6, s390_VStrX_VSTRC); - return "vstrc"; } -static const HChar * +static void s390_irgen_VSTRS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vstrs"; + return; } - s390_insn_assert("vstrs", m5 <= 2 && m6 == (m6 & 2)); + s390_insn_assert(m5 <= 2 && m6 == (m6 & 2)); IRTemp op2 = newTemp(Ity_V128); IRTemp op3 = newTemp(Ity_V128); @@ -17670,134 +15836,112 @@ s390_irgen_VSTRS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) s390_cc_set(cc); dis_res->hint = Dis_HintVerbose; - return "vstrs"; } -static const HChar * +static void s390_irgen_VNC(UChar v1, UChar v2, UChar v3) { put_vr_qw(v1, binop(Iop_AndV128, get_vr_qw(v2), unop(Iop_NotV128, get_vr_qw(v3))) ); - - return "vnc"; } -static const HChar * +static void s390_irgen_VA(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("va", m4 <= 4); + s390_insn_assert(m4 <= 4); const IROp ops[] = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4, Iop_Add64x2, Iop_Add128x1 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "va"; } -static const HChar * +static void s390_irgen_VS(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vs", m4 <= 4); + s390_insn_assert(m4 <= 4); const IROp ops[] = { Iop_Sub8x16, Iop_Sub16x8, Iop_Sub32x4, Iop_Sub64x2, Iop_Sub128x1 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vs"; } -static const HChar * +static void s390_irgen_VMX(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmx", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Max8Sx16, Iop_Max16Sx8, Iop_Max32Sx4, Iop_Max64Sx2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmx"; } -static const HChar * +static void s390_irgen_VMXL(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmxl", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Max8Ux16, Iop_Max16Ux8, Iop_Max32Ux4, Iop_Max64Ux2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmxl"; } -static const HChar * +static void s390_irgen_VMN(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmn", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Min8Sx16, Iop_Min16Sx8, Iop_Min32Sx4, Iop_Min64Sx2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmn"; } -static const HChar * +static void s390_irgen_VMNL(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmnl", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Min8Ux16, Iop_Min16Ux8, Iop_Min32Ux4, Iop_Min64Ux2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmnl"; } -static const HChar * +static void s390_irgen_VAVG(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vavg", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Avg8Sx16, Iop_Avg16Sx8, Iop_Avg32Sx4, Iop_Avg64Sx2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vavg"; } -static const HChar * +static void s390_irgen_VAVGL(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vavgl", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Avg8Ux16, Iop_Avg16Ux8, Iop_Avg32Ux4, Iop_Avg64Ux2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vavgl"; } -static const HChar * +static void s390_irgen_VLC(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vlc", m3 < 4); + s390_insn_assert(m3 < 4); IRType type = s390_vr_get_type(m3); put_vr_qw(v1, s390_V128_get_complement(get_vr_qw(v2), type)); - return "vlc"; } -static const HChar * +static void s390_irgen_VLP(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vlp", m3 <= 3); + s390_insn_assert(m3 <= 3); const IROp ops[] = { Iop_Abs8x16, Iop_Abs16x8, Iop_Abs32x4, Iop_Abs64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_qw(v2))); - - return "vlp"; } -static const HChar * +static void s390_irgen_VCH(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vch", m4 <= 3); + s390_insn_assert(m4 <= 3); if (!s390_vr_is_cs_set(m5)) { const IROp ops[] = { Iop_CmpGT8Sx16, Iop_CmpGT16Sx8, Iop_CmpGT32Sx4, @@ -17836,14 +15980,12 @@ s390_irgen_VCH(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); } - - return "vch"; } -static const HChar * +static void s390_irgen_VCHL(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vchl", m4 <= 3); + s390_insn_assert(m4 <= 3); if (!s390_vr_is_cs_set(m5)) { const IROp ops[] = { Iop_CmpGT8Ux16, Iop_CmpGT16Ux8, Iop_CmpGT32Ux4, @@ -17882,36 +16024,30 @@ s390_irgen_VCHL(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); } - - return "vchl"; } -static const HChar * +static void s390_irgen_VCLZ(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vclz", m3 <= 3); + s390_insn_assert(m3 <= 3); const IROp ops[] = { Iop_Clz8x16, Iop_Clz16x8, Iop_Clz32x4, Iop_Clz64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_qw(v2))); - - return "vclz"; } -static const HChar * +static void s390_irgen_VCTZ(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vctz", m3 <= 3); + s390_insn_assert(m3 <= 3); const IROp ops[] = { Iop_Ctz8x16, Iop_Ctz16x8, Iop_Ctz32x4, Iop_Ctz64x2 }; put_vr_qw(v1, unop(ops[m3], get_vr_qw(v2))); - - return "vctz"; } -static const HChar * +static void s390_irgen_VPOPCT(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vpopct", m3 <= 3); + s390_insn_assert(m3 <= 3); IRExpr* cnt = unop(Iop_Cnt8x16, get_vr_qw(v2)); @@ -17924,149 +16060,123 @@ s390_irgen_VPOPCT(UChar v1, UChar v2, UChar m3) } } put_vr_qw(v1, cnt); - - return "vpopct"; } -static const HChar * +static void s390_irgen_VML(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vml", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vml"; } -static const HChar * +static void s390_irgen_VMLH(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmlh", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_MulHi8Ux16, Iop_MulHi16Ux8, Iop_MulHi32Ux4 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmlh"; } -static const HChar * +static void s390_irgen_VMH(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmh", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_MulHi8Sx16, Iop_MulHi16Sx8, Iop_MulHi32Sx4 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmh"; } -static const HChar * +static void s390_irgen_VMO(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmo", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_MullEven8Sx16, Iop_MullEven16Sx8, Iop_MullEven32Sx4 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmo"; } -static const HChar * +static void s390_irgen_VMLO(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmlo", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_MullEven8Ux16, Iop_MullEven16Ux8, Iop_MullEven32Ux4 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vmlo"; } -static const HChar * +static void s390_irgen_VESLV(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vselv", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Shl8x16, Iop_Shl16x8, Iop_Shl32x4, Iop_Shl64x2}; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "veslv"; } -static const HChar * +static void s390_irgen_VESL(UChar v1, IRTemp op2addr, UChar v3, UChar m4) { - s390_insn_assert("vesl", m4 <= 3); + s390_insn_assert(m4 <= 3); IRExpr* shift_amount = unop(Iop_64to8, mkexpr(op2addr)); const IROp ops[] = { Iop_ShlN8x16, Iop_ShlN16x8, Iop_ShlN32x4, Iop_ShlN64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v3), shift_amount)); - - return "vesl"; } -static const HChar * +static void s390_irgen_VESRAV(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vesrav", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Sar8x16, Iop_Sar16x8, Iop_Sar32x4, Iop_Sar64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vesrav"; } -static const HChar * +static void s390_irgen_VESRA(UChar v1, IRTemp op2addr, UChar v3, UChar m4) { - s390_insn_assert("vesra", m4 <= 3); + s390_insn_assert(m4 <= 3); IRExpr* shift_amount = unop(Iop_64to8, mkexpr(op2addr)); const IROp ops[] = { Iop_SarN8x16, Iop_SarN16x8, Iop_SarN32x4, Iop_SarN64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v3), shift_amount)); - - return "vesra"; } -static const HChar * +static void s390_irgen_VESRLV(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vesrlv", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Shr8x16, Iop_Shr16x8, Iop_Shr32x4, Iop_Shr64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "vesrlv"; } -static const HChar * +static void s390_irgen_VESRL(UChar v1, IRTemp op2addr, UChar v3, UChar m4) { - s390_insn_assert("vesrl", m4 <= 3); + s390_insn_assert(m4 <= 3); IRExpr* shift_amount = unop(Iop_64to8, mkexpr(op2addr)); const IROp ops[] = { Iop_ShrN8x16, Iop_ShrN16x8, Iop_ShrN32x4, Iop_ShrN64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v3), shift_amount)); - - return "vesrl"; } -static const HChar * +static void s390_irgen_VERLLV(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("verllv", m4 <= 3); + s390_insn_assert(m4 <= 3); const IROp ops[] = { Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4, Iop_Rol64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v2), get_vr_qw(v3))); - - return "verllv"; } -static const HChar * +static void s390_irgen_VERLL(UChar v1, IRTemp op2addr, UChar v3, UChar m4) { - s390_insn_assert("verll", m4 <= 3); + s390_insn_assert(m4 <= 3); /* There is no Iop_RolN?x?? operations so we have to use VECTOR x VECTOR variant. @@ -18074,11 +16184,9 @@ s390_irgen_VERLL(UChar v1, IRTemp op2addr, UChar v3, UChar m4) IRExpr* shift_vector = unop(Iop_Dup8x16, unop(Iop_64to8, mkexpr(op2addr))); const IROp ops[] = { Iop_Rol8x16, Iop_Rol16x8, Iop_Rol32x4, Iop_Rol64x2 }; put_vr_qw(v1, binop(ops[m4], get_vr_qw(v3), shift_vector)); - - return "verll"; } -static const HChar * +static void s390_irgen_VSL(UChar v1, UChar v2, UChar v3) { IRTemp a = newTemp(Ity_V128); @@ -18095,10 +16203,9 @@ s390_irgen_VSL(UChar v1, UChar v2, UChar v3) binop(Iop_ShlV128, mkexpr(a), mkU8(8)), unop(Iop_NotV128, mkexpr(b))), unop(Iop_Dup8x16, mkU8(1))))); - return "vsl"; } -static const HChar * +static void s390_irgen_VSRL(UChar v1, UChar v2, UChar v3) { IRTemp a = newTemp(Ity_V128); @@ -18115,10 +16222,9 @@ s390_irgen_VSRL(UChar v1, UChar v2, UChar v3) binop(Iop_ShrV128, mkexpr(a), mkU8(8)), unop(Iop_NotV128, mkexpr(b))), unop(Iop_Dup8x16, mkU8(1))))); - return "vsrl"; } -static const HChar * +static void s390_irgen_VSRA(UChar v1, UChar v2, UChar v3) { IRTemp a = newTemp(Ity_V128); @@ -18141,13 +16247,12 @@ s390_irgen_VSRA(UChar v1, UChar v2, UChar v3) binop(Iop_ShrV128, mkexpr(a), mkU8(8)), unop(Iop_NotV128, mkexpr(b))), unop(Iop_Dup8x16, mkU8(1))))); - return "vsra"; } -static const HChar * +static void s390_irgen_VERIM(UChar v1, UChar v2, UChar v3, UChar i4, UChar m5) { - s390_insn_assert("verim", m5 <= 3); + s390_insn_assert(m5 <= 3); /* There is no Iop_RolN?x?? operations so we have to use VECTOR x VECTOR variant. @@ -18160,14 +16265,12 @@ s390_irgen_VERIM(UChar v1, UChar v2, UChar v3, UChar i4, UChar m5) IRExpr* mask = get_vr_qw(v3); IRExpr* result = get_vr_qw(v1); put_vr_qw(v1, s390_V128_bitwiseITE(mask, rotated_vector, result)); - - return "verim"; } -static const HChar * +static void s390_irgen_VEC(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vec", m3 <= 3); + s390_insn_assert(m3 <= 3); IRType type = s390_vr_get_type(m3); IRTemp op1 = newTemp(type); @@ -18195,14 +16298,12 @@ s390_irgen_VEC(UChar v1, UChar v2, UChar m3) } s390_cc_thunk_putSS(S390_CC_OP_SIGNED_COMPARE, op1, op2); - - return "vec"; } -static const HChar * +static void s390_irgen_VECL(UChar v1, UChar v2, UChar m3) { - s390_insn_assert("vecl", m3 <= 3); + s390_insn_assert(m3 <= 3); IRType type = s390_vr_get_type(m3); IRTemp op1 = newTemp(type); @@ -18230,14 +16331,12 @@ s390_irgen_VECL(UChar v1, UChar v2, UChar m3) } s390_cc_thunk_putZZ(S390_CC_OP_UNSIGNED_COMPARE, op1, op2); - - return "vecl"; } -static const HChar * +static void s390_irgen_VCEQ(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert("vceq", m4 <= 3); + s390_insn_assert(m4 <= 3); if (!s390_vr_is_cs_set(m5)) { const IROp ops[] = { Iop_CmpEQ8x16, Iop_CmpEQ16x8, Iop_CmpEQ32x4, @@ -18276,41 +16375,36 @@ s390_irgen_VCEQ(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); } - - return "vceq"; } -static const HChar * +static void s390_irgen_VSLB(UChar v1, UChar v2, UChar v3) { IRTemp shift_amount = newTemp(Ity_I8); assign(shift_amount, binop(Iop_And8, get_vr_b7(v3), mkU8(0b01111000))); put_vr_qw(v1, binop(Iop_ShlV128, get_vr_qw(v2), mkexpr(shift_amount))); - return "vslb"; } -static const HChar * +static void s390_irgen_VSRLB(UChar v1, UChar v2, UChar v3) { IRTemp shift_amount = newTemp(Ity_I8); assign(shift_amount, binop(Iop_And8, get_vr_b7(v3), mkU8(0b01111000))); put_vr_qw(v1, binop(Iop_ShrV128, get_vr_qw(v2), mkexpr(shift_amount))); - return "vsrlb"; } -static const HChar * +static void s390_irgen_VSRAB(UChar v1, UChar v2, UChar v3) { IRTemp shift_amount = newTemp(Ity_I8); assign(shift_amount, binop(Iop_And8, get_vr_b7(v3), mkU8(0b01111000))); put_vr_qw(v1, binop(Iop_SarV128, get_vr_qw(v2), mkexpr(shift_amount))); - return "vsrab"; } -static const HChar * +static void s390_irgen_VSLDB(UChar v1, UChar v2, UChar v3, UChar i4) { UChar imm = i4 & 0b00001111; @@ -18327,19 +16421,17 @@ s390_irgen_VSLDB(UChar v1, UChar v2, UChar v3, UChar i4) ) ); } - - return "vsldb"; } -static const HChar * +static void s390_irgen_VSLD(UChar v1, UChar v2, UChar v3, UChar i4) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vsld"; + return; } - s390_insn_assert("vsld", i4 <= 7); + s390_insn_assert(i4 <= 7); if (i4 == 0) { /* Just copy v2. */ @@ -18353,19 +16445,17 @@ s390_irgen_VSLD(UChar v1, UChar v2, UChar v3, UChar i4) ) ); } - - return "vsld"; } -static const HChar * +static void s390_irgen_VSRD(UChar v1, UChar v2, UChar v3, UChar i4) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vsrd"; + return; } - s390_insn_assert("vsrd", i4 <= 7); + s390_insn_assert(i4 <= 7); if (i4 == 0) { /* Just copy v3. */ @@ -18379,14 +16469,12 @@ s390_irgen_VSRD(UChar v1, UChar v2, UChar v3, UChar i4) ) ); } - - return "vsrd"; } -static const HChar * +static void s390_irgen_VME(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vme", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_MullEven8Sx16, Iop_MullEven16Sx8, Iop_MullEven32Sx4 }; @@ -18396,14 +16484,12 @@ s390_irgen_VME(UChar v1, UChar v2, UChar v3, UChar m4) binop(Iop_ShrV128, get_vr_qw(v3), mkU8(shifts[m4])) ); put_vr_qw(v1, result); - - return "vme"; } -static const HChar * +static void s390_irgen_VMLE(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vmle", m4 <= 2); + s390_insn_assert(m4 <= 2); const IROp ops[] = { Iop_MullEven8Ux16, Iop_MullEven16Ux8, Iop_MullEven32Ux4 }; @@ -18413,14 +16499,12 @@ s390_irgen_VMLE(UChar v1, UChar v2, UChar v3, UChar m4) binop(Iop_ShrV128, get_vr_qw(v3), mkU8(shifts[m4])) ); put_vr_qw(v1, result); - - return "vmle"; } -static const HChar * +static void s390_irgen_VMAO(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmao", m5 <= 2); + s390_insn_assert(m5 <= 2); const IROp mul_ops[] = { Iop_MullEven8Sx16, Iop_MullEven16Sx8, Iop_MullEven32Sx4 }; @@ -18429,14 +16513,12 @@ s390_irgen_VMAO(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) IRExpr* mul_result = binop(mul_ops[m5], get_vr_qw(v2), get_vr_qw(v3)); IRExpr* result = binop(add_ops[m5], mul_result, get_vr_qw(v4)); put_vr_qw(v1, result); - - return "vmao"; } -static const HChar * +static void s390_irgen_VMALO(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmalo", m5 <= 2); + s390_insn_assert(m5 <= 2); const IROp mul_ops[] = { Iop_MullEven8Ux16, Iop_MullEven16Ux8, Iop_MullEven32Ux4 }; @@ -18445,14 +16527,12 @@ s390_irgen_VMALO(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) IRExpr* mul_result = binop(mul_ops[m5], get_vr_qw(v2), get_vr_qw(v3)); IRExpr* result = binop(add_ops[m5], mul_result, get_vr_qw(v4)); put_vr_qw(v1, result); - - return "vmalo"; } -static const HChar * +static void s390_irgen_VMAE(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmae", m5 <= 2); + s390_insn_assert(m5 <= 2); const IROp mul_ops[] = { Iop_MullEven8Sx16, Iop_MullEven16Sx8, Iop_MullEven32Sx4 }; @@ -18465,14 +16545,12 @@ s390_irgen_VMAE(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) binop(Iop_ShrV128, get_vr_qw(v3), mkU8(shifts[m5]))); IRExpr* result = binop(add_ops[m5], mul_result, get_vr_qw(v4)); put_vr_qw(v1, result); - - return "vmae"; } -static const HChar * +static void s390_irgen_VMALE(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmale", m5 <= 2); + s390_insn_assert(m5 <= 2); const IROp mul_ops[] = { Iop_MullEven8Ux16, Iop_MullEven16Ux8, Iop_MullEven32Ux4 }; @@ -18488,14 +16566,12 @@ s390_irgen_VMALE(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) IRExpr* result = binop(add_ops[m5], mul_result, get_vr_qw(v4)); put_vr_qw(v1, result); - - return "vmale"; } -static const HChar * +static void s390_irgen_VMAL(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmal", m5 <= 2); + s390_insn_assert(m5 <= 2); const IROp mul_ops[] = { Iop_Mul8x16, Iop_Mul16x8, Iop_Mul32x4 }; const IROp add_ops[] = { Iop_Add8x16, Iop_Add16x8, Iop_Add32x4 }; @@ -18503,14 +16579,12 @@ s390_irgen_VMAL(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) IRExpr* mul_result = binop(mul_ops[m5], get_vr_qw(v2), get_vr_qw(v3)); IRExpr* result = binop(add_ops[m5], mul_result, get_vr_qw(v4)); put_vr_qw(v1, result); - - return "vmal"; } -static const HChar * +static void s390_irgen_VSUM(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vsum", m4 <= 1); + s390_insn_assert(m4 <= 1); IRType type = s390_vr_get_type(m4); IRExpr* mask; @@ -18530,14 +16604,12 @@ s390_irgen_VSUM(UChar v1, UChar v2, UChar v3, UChar m4) IRExpr* addition = binop(Iop_AndV128, get_vr_qw(v3), mask); put_vr_qw(v1, binop(Iop_Add32x4, sum, addition)); - - return "vsum"; } -static const HChar * +static void s390_irgen_VSUMG(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vsumg", m4 == 1 || m4 == 2); + s390_insn_assert(m4 == 1 || m4 == 2); IRType type = s390_vr_get_type(m4); IRExpr* mask; @@ -18557,14 +16629,12 @@ s390_irgen_VSUMG(UChar v1, UChar v2, UChar v3, UChar m4) IRExpr* addition = binop(Iop_AndV128, get_vr_qw(v3), mask); put_vr_qw(v1, binop(Iop_Add64x2, sum, addition)); - - return "vsumg"; } -static const HChar * +static void s390_irgen_VSUMQ(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vsumq", m4 == 2 || m4 == 3); + s390_insn_assert(m4 == 2 || m4 == 3); IRType type = s390_vr_get_type(m4); IRExpr* mask; @@ -18584,11 +16654,9 @@ s390_irgen_VSUMQ(UChar v1, UChar v2, UChar v3, UChar m4) IRExpr* addition = binop(Iop_AndV128, get_vr_qw(v3), mask); put_vr_qw(v1, binop(Iop_Add128x1, sum, addition)); - - return "vsumq"; } -static const HChar * +static void s390_irgen_VTM(UChar v1, UChar v2) { IRTemp op1 = newTemp(Ity_V128); @@ -18614,13 +16682,12 @@ s390_irgen_VTM(UChar v1, UChar v2) assign(cc, mkite(masked_is_zero, mkU64(0), mkite(diff_is_zero, mkU64(3), mkU64(1)))); s390_cc_set(cc); - return "vtm"; } -static const HChar * +static void s390_irgen_VAC(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vac", m5 == 4); + s390_insn_assert(m5 == 4); IRTemp sum = newTemp(Ity_V128); assign(sum, binop(Iop_Add128x1, get_vr_qw(v2), get_vr_qw(v3))); @@ -18628,27 +16695,24 @@ s390_irgen_VAC(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) IRExpr* mask = binop(Iop_64HLtoV128, mkU64(0), mkU64(1)); IRExpr* carry_in = binop(Iop_AndV128, get_vr_qw(v4), mask); put_vr_qw(v1, binop(Iop_Add128x1, mkexpr(sum), carry_in)); - - return "vac"; } -static const HChar * +static void s390_irgen_VACC(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vacc", m4 <= 4); + s390_insn_assert(m4 <= 4); IRType type = s390_vr_get_type(m4); IRExpr* arg1 = get_vr_qw(v2); IRExpr* arg2 = get_vr_qw(v3); put_vr_qw(v1, s390_V128_calculate_carry_out(arg1, arg2, type, False)); - return "vacc"; } -static const HChar * +static void s390_irgen_VACCC(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vaccc", m5 == 4); + s390_insn_assert(m5 == 4); IRExpr* result = s390_V128_calculate_carry_out_with_carry(get_vr_qw(v2), @@ -18657,10 +16721,9 @@ s390_irgen_VACCC(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) ); put_vr_qw(v1, result); - return "vaccc"; } -static const HChar* +static void s390_irgen_VCKSM(UChar v1, UChar v2, UChar v3) { @@ -18671,14 +16734,12 @@ s390_irgen_VCKSM(UChar v1, UChar v2, UChar v3) put_vr_qw(v1, binop(Iop_64HLtoV128, unop(Iop_32Uto64, mkexpr(result)), mkU64(0ULL))); - - return "vcksm"; } -static const HChar * +static void s390_irgen_VGFM(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vgfm", m4 <= 3); + s390_insn_assert(m4 <= 3); IRDirty* d; IRTemp cc = newTemp(Ity_I64); @@ -18708,13 +16769,12 @@ s390_irgen_VGFM(UChar v1, UChar v2, UChar v3, UChar m4) d->fxState[2].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - return "vgfm"; } -static const HChar * +static void s390_irgen_VGFMA(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vgfma", m5 <= 3); + s390_insn_assert(m5 <= 3); IRDirty* d; IRTemp cc = newTemp(Ity_I64); @@ -18748,13 +16808,12 @@ s390_irgen_VGFMA(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) d->fxState[3].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - return "vgfma"; } -static const HChar * +static void s390_irgen_VSBI(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vsbi", m5 == 4); + s390_insn_assert(m5 == 4); IRExpr* mask = binop(Iop_64HLtoV128, mkU64(0ULL), mkU64(1ULL)); IRExpr* carry_in = binop(Iop_AndV128, get_vr_qw(v4), mask); @@ -18767,13 +16826,12 @@ s390_irgen_VSBI(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) ); put_vr_qw(v1, binop(Iop_Add128x1, mkexpr(sum), carry_in)); - return "vsbi"; } -static const HChar * +static void s390_irgen_VSCBI(UChar v1, UChar v2, UChar v3, UChar m4) { - s390_insn_assert("vscbi", m4 <= 4); + s390_insn_assert(m4 <= 4); IRType type = s390_vr_get_type(m4); IRExpr* arg1 = get_vr_qw(v2); @@ -18781,13 +16839,12 @@ s390_irgen_VSCBI(UChar v1, UChar v2, UChar v3, UChar m4) IRExpr* result = s390_V128_calculate_carry_out(arg1, arg2, type, True); put_vr_qw(v1, result); - return "vscbi"; } -static const HChar * +static void s390_irgen_VSBCBI(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vsbcbi", m5 == 4); + s390_insn_assert(m5 == 4); IRExpr* result = s390_V128_calculate_carry_out_with_carry(get_vr_qw(v2), @@ -18795,13 +16852,12 @@ s390_irgen_VSBCBI(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) get_vr_qw(v4)); put_vr_qw(v1, result); - return "vsbcbi"; } -static const HChar * +static void s390_irgen_VMAH(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmah", m5 < 3); + s390_insn_assert(m5 < 3); IRDirty* d; IRTemp cc = newTemp(Ity_I64); @@ -18835,14 +16891,12 @@ s390_irgen_VMAH(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) d->fxState[3].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - - return "vmah"; } -static const HChar * +static void s390_irgen_VMALH(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) { - s390_insn_assert("vmalh", m5 < 3); + s390_insn_assert(m5 < 3); IRDirty* d; IRTemp cc = newTemp(Ity_I64); @@ -18876,19 +16930,17 @@ s390_irgen_VMALH(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5) d->fxState[3].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - - return "vmalh"; } -static const HChar * +static void s390_irgen_VMSL(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vmsl"; + return; } - s390_insn_assert("vmsl", m5 == 3 && (m6 & 3) == 0); + s390_insn_assert(m5 == 3 && (m6 & 3) == 0); IRDirty* d; IRTemp cc = newTemp(Ity_I64); @@ -18923,8 +16975,6 @@ s390_irgen_VMSL(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) d->fxState[3].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - - return "vmsl"; } static void @@ -18965,69 +17015,64 @@ s390_vector_fp_convert(IROp op, IRType fromType, IRType toType, Bool rounding, } } -static const HChar * +static void s390_irgen_VCDG(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vcdg", m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); - s390_insn_assert("vcdg", (m4 & 0x3) == 0); - s390_insn_assert("vcdg", m5 != 2 && m5 <= 7); + s390_insn_assert(m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); + s390_insn_assert((m4 & 0x3) == 0); + s390_insn_assert(m5 != 2 && m5 <= 7); s390_vector_fp_convert(m3 == 2 ? Iop_I32StoF32 : Iop_I64StoF64, m3 == 2 ? Ity_I32 : Ity_I64, m3 == 2 ? Ity_F32 : Ity_F64, True, v1, v2, m3, m4, m5); - return "vcdg"; } -static const HChar * +static void s390_irgen_VCDLG(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vcdlg", m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); - s390_insn_assert("vcdlg", (m4 & 0x3) == 0); - s390_insn_assert("vcdlg", m5 != 2 && m5 <= 7); + s390_insn_assert(m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); + s390_insn_assert((m4 & 0x3) == 0); + s390_insn_assert(m5 != 2 && m5 <= 7); s390_vector_fp_convert(m3 == 2 ? Iop_I32UtoF32 : Iop_I64UtoF64, m3 == 2 ? Ity_I32 : Ity_I64, m3 == 2 ? Ity_F32 : Ity_F64, True, v1, v2, m3, m4, m5); - return "vcdlg"; } -static const HChar * +static void s390_irgen_VCGD(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vcgd", m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); - s390_insn_assert("vcgd", (m4 & 0x3) == 0); - s390_insn_assert("vcgd", m5 != 2 && m5 <= 7); + s390_insn_assert(m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); + s390_insn_assert((m4 & 0x3) == 0); + s390_insn_assert(m5 != 2 && m5 <= 7); s390_vector_fp_convert(m3 == 2 ? Iop_F32toI32S : Iop_F64toI64S, m3 == 2 ? Ity_F32 : Ity_F64, m3 == 2 ? Ity_I32 : Ity_I64, True, v1, v2, m3, m4, m5); - return "vcgd"; } -static const HChar * +static void s390_irgen_VCLGD(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vclgd", m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); - s390_insn_assert("vclgd", (m4 & 0x3) == 0); - s390_insn_assert("vclgd", m5 != 2 && m5 <= 7); + s390_insn_assert(m3 == 3 || (m3 == 2 && s390_host_has_vxe2)); + s390_insn_assert((m4 & 0x3) == 0); + s390_insn_assert(m5 != 2 && m5 <= 7); s390_vector_fp_convert(m3 == 2 ? Iop_F32toI32U : Iop_F64toI64U, m3 == 2 ? Ity_F32 : Ity_F64, m3 == 2 ? Ity_I32 : Ity_I64, True, v1, v2, m3, m4, m5); - return "vclgd"; } -static const HChar * +static void s390_irgen_VFI(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vfi", - (m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4))); - s390_insn_assert("vfi", (m4 & 0x3) == 0); - s390_insn_assert("vfi", m5 != 2 && m5 <= 7); + s390_insn_assert((m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4))); + s390_insn_assert((m4 & 0x3) == 0); + s390_insn_assert(m5 != 2 && m5 <= 7); switch (m3) { case 2: s390_vector_fp_convert(Iop_RoundF32toInt, Ity_F32, Ity_F32, True, @@ -19037,15 +17082,13 @@ s390_irgen_VFI(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) case 4: s390_vector_fp_convert(Iop_RoundF128toInt, Ity_F128, Ity_F128, True, v1, v2, m3, m4, m5); break; } - - return "vfi"; } -static const HChar * +static void s390_irgen_VFLL(UChar v1, UChar v2, UChar m3, UChar m4) { - s390_insn_assert("vfll", m3 == 2 || (s390_host_has_vxe && m3 == 3)); - s390_insn_assert("vfll", (m4 & 0x7) == 0); + s390_insn_assert(m3 == 2 || (s390_host_has_vxe && m3 == 3)); + s390_insn_assert((m4 & 0x7) == 0); if (m3 == 2) s390_vector_fp_convert(Iop_F32toF64, Ity_F32, Ity_F64, False, @@ -19053,16 +17096,14 @@ s390_irgen_VFLL(UChar v1, UChar v2, UChar m3, UChar m4) else s390_vector_fp_convert(Iop_F64toF128, Ity_F64, Ity_F128, False, v1, v2, m3, m4, /* don't care */ 0); - - return "vfll"; } -static const HChar * +static void s390_irgen_VFLR(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vflr", m3 == 3 || (s390_host_has_vxe && m3 == 4)); - s390_insn_assert("vflr", (m4 & 0x3) == 0); - s390_insn_assert("vflr", m5 != 2 && m5 <= 7); + s390_insn_assert(m3 == 3 || (s390_host_has_vxe && m3 == 4)); + s390_insn_assert((m4 & 0x3) == 0); + s390_insn_assert(m5 != 2 && m5 <= 7); if (m3 == 3) s390_vector_fp_convert(Iop_F64toF32, Ity_F64, Ity_F32, True, @@ -19070,16 +17111,14 @@ s390_irgen_VFLR(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) else s390_vector_fp_convert(Iop_F128toF64, Ity_F128, Ity_F64, True, v1, v2, m3, m4, m5); - - return "vflr"; } -static const HChar * +static void s390_irgen_VFPSO(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - s390_insn_assert("vfpso", m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4)); - s390_insn_assert("vfpso", (m4 & 0x7) == 0); - s390_insn_assert("vfpso", m5 <= 2); + s390_insn_assert(m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4)); + s390_insn_assert((m4 & 0x7) == 0); + s390_insn_assert(m5 <= 2); Bool single = s390_vr_is_single_element_control_set(m4) || m3 == 4; IRType type = single ? s390_vr_get_ftype(m3) : Ity_V128; @@ -19106,16 +17145,14 @@ s390_irgen_VFPSO(UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) const IROp *ops = m5 == 2 ? abs_ops : negate_ops; put_vr(v1, type, 0, unop(ops[idx], get_vr(v2, type, 0))); } - - return "vfpso"; } -static const HChar * -s390x_vec_fp_binary_op(const HChar* mnm, const IROp ops[], +static void +s390x_vec_fp_binary_op(const IROp ops[], UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - s390_insn_assert(mnm, (m5 & 7) == 0 && + s390_insn_assert((m5 & 7) == 0 && (m4 == 3 || (s390_host_has_vxe && m4 >= 2 && m4 <= 4))); int idx = 2 * (m4 - 2); @@ -19129,15 +17166,13 @@ s390x_vec_fp_binary_op(const HChar* mnm, const IROp ops[], put_vr_qw(v1, triop(ops[idx + 1], get_bfp_rounding_mode_from_fpc(), get_vr_qw(v2), get_vr_qw(v3))); } - - return mnm; } -static const HChar * -s390x_vec_fp_unary_op(const HChar* mnm, const IROp ops[], +static void +s390x_vec_fp_unary_op(const IROp ops[], UChar v1, UChar v2, UChar m3, UChar m4) { - s390_insn_assert(mnm, (m4 & 7) == 0 && + s390_insn_assert((m4 & 7) == 0 && (m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4))); int idx = 2 * (m3 - 2); @@ -19152,19 +17187,17 @@ s390x_vec_fp_unary_op(const HChar* mnm, const IROp ops[], put_vr_qw(v1, binop(ops[idx + 1], get_bfp_rounding_mode_from_fpc(), get_vr_qw(v2))); } - - return mnm; } -static const HChar * +static void s390_vector_fp_mulAddOrSub(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6, - const HChar* mnm, const IROp single_ops[], + const IROp single_ops[], Bool negate) { - s390_insn_assert(mnm, (m5 & 0x7) == 0); - s390_insn_assert(mnm, m6 == 3 || (s390_host_has_vxe && m6 >= 2 && m6 <= 4)); + s390_insn_assert((m5 & 0x7) == 0); + s390_insn_assert(m6 == 3 || (s390_host_has_vxe && m6 >= 2 && m6 <= 4)); static const IROp negate_ops[] = { Iop_NegF32, Iop_NegF64, Iop_NegF128 }; IRType type = s390_vr_get_ftype(m6); @@ -19182,10 +17215,9 @@ s390_vector_fp_mulAddOrSub(UChar v1, UChar v2, UChar v3, UChar v4, get_vr(v4, type, idx)); put_vr(v1, type, idx, negate ? unop(negate_ops[m6 - 2], result) : result); } - return mnm; } -static const HChar * +static void s390_irgen_VFA(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { static const IROp vfa_ops[] = { @@ -19193,10 +17225,10 @@ s390_irgen_VFA(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) Iop_AddF64, Iop_Add64Fx2, Iop_AddF128, }; - return s390x_vec_fp_binary_op("vfa", vfa_ops, v1, v2, v3, m4, m5); + s390x_vec_fp_binary_op(vfa_ops, v1, v2, v3, m4, m5); } -static const HChar * +static void s390_irgen_VFS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { static const IROp vfs_ops[] = { @@ -19204,10 +17236,10 @@ s390_irgen_VFS(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) Iop_SubF64, Iop_Sub64Fx2, Iop_SubF128, }; - return s390x_vec_fp_binary_op("vfs", vfs_ops, v1, v2, v3, m4, m5); + s390x_vec_fp_binary_op(vfs_ops, v1, v2, v3, m4, m5); } -static const HChar * +static void s390_irgen_VFM(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { static const IROp vfm_ops[] = { @@ -19215,10 +17247,10 @@ s390_irgen_VFM(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) Iop_MulF64, Iop_Mul64Fx2, Iop_MulF128, }; - return s390x_vec_fp_binary_op("vfm", vfm_ops, v1, v2, v3, m4, m5); + s390x_vec_fp_binary_op(vfm_ops, v1, v2, v3, m4, m5); } -static const HChar * +static void s390_irgen_VFD(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { static const IROp vfd_ops[] = { @@ -19226,10 +17258,10 @@ s390_irgen_VFD(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) Iop_DivF64, Iop_Div64Fx2, Iop_DivF128, }; - return s390x_vec_fp_binary_op("vfd", vfd_ops, v1, v2, v3, m4, m5); + s390x_vec_fp_binary_op(vfd_ops, v1, v2, v3, m4, m5); } -static const HChar * +static void s390_irgen_VFSQ(UChar v1, UChar v2, UChar m3, UChar m4) { static const IROp vfsq_ops[] = { @@ -19237,59 +17269,59 @@ s390_irgen_VFSQ(UChar v1, UChar v2, UChar m3, UChar m4) Iop_SqrtF64, Iop_Sqrt64Fx2, Iop_SqrtF128 }; - return s390x_vec_fp_unary_op("vfsq", vfsq_ops, v1, v2, m3, m4); + s390x_vec_fp_unary_op(vfsq_ops, v1, v2, m3, m4); } static const IROp FMA_single_ops[] = { Iop_MAddF32, Iop_MAddF64, Iop_MAddF128 }; -static const HChar * +static void s390_irgen_VFMA(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { - return s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, - "vfma", FMA_single_ops, False); + s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, + FMA_single_ops, False); } -static const HChar * +static void s390_irgen_VFNMA(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vfnma"; + return; } - return s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, - "vfnma", FMA_single_ops, True); + s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, + FMA_single_ops, True); } static const IROp FMS_single_ops[] = { Iop_MSubF32, Iop_MSubF64, Iop_MSubF128 }; -static const HChar * +static void s390_irgen_VFMS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { - return s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, - "vfms", FMS_single_ops, False); + s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, + FMS_single_ops, False); } -static const HChar * +static void s390_irgen_VFNMS(UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vfnms"; + return; } - return s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, - "vfnms", FMS_single_ops, True); + s390_vector_fp_mulAddOrSub(v1, v2, v3, v4, m5, m6, + FMS_single_ops, True); } -static const HChar * +static void s390_irgen_WFC(UChar v1, UChar v2, UChar m3, UChar m4) { - s390_insn_assert("wfc", m4 == 0 && + s390_insn_assert(m4 == 0 && (m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4))); static const IROp ops[] = { Iop_CmpF32, Iop_CmpF64, Iop_CmpF128 }; @@ -19301,27 +17333,23 @@ s390_irgen_WFC(UChar v1, UChar v2, UChar m3, UChar m4) IRTemp cc_s390 = newTemp(Ity_I32); assign(cc_s390, convert_vex_bfpcc_to_s390(cc_vex)); s390_cc_thunk_put1(S390_CC_OP_SET, cc_s390, False); - - return "wfc"; } -static const HChar * +static void s390_irgen_WFK(UChar v1, UChar v2, UChar m3, UChar m4) { - s390_insn_assert("wfk", m4 == 0 && + s390_insn_assert(m4 == 0 && (m3 == 3 || (s390_host_has_vxe && m3 >= 2 && m3 <= 4))); s390_irgen_WFC(v1, v2, m3, m4); - - return "wfk"; } -static const HChar * +static void s390_irgen_VFCx(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6, - const HChar *mnem, IRCmpFResult cmp, Bool equal_ok, + IRCmpFResult cmp, Bool equal_ok, IROp cmp32, IROp cmp64) { - s390_insn_assert(mnem, (m5 & 3) == 0 && (m6 & 14) == 0 && + s390_insn_assert((m5 & 3) == 0 && (m6 & 14) == 0 && (m4 == 3 || (s390_host_has_vxe && m4 >= 2 && m4 <= 4))); Bool single = s390_vr_is_single_element_control_set(m5) || m4 == 4; @@ -19375,39 +17403,36 @@ s390_irgen_VFCx(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6, s390_cc_set(cc); } } - - return mnem; } -static const HChar * +static void s390_irgen_VFCE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { - return s390_irgen_VFCx(v1, v2, v3, m4, m5, m6, "vfce", Ircr_EQ, - False, Iop_CmpEQ32Fx4, Iop_CmpEQ64Fx2); + s390_irgen_VFCx(v1, v2, v3, m4, m5, m6, Ircr_EQ, + False, Iop_CmpEQ32Fx4, Iop_CmpEQ64Fx2); } -static const HChar * +static void s390_irgen_VFCH(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { /* Swap arguments and compare "low" instead. */ - return s390_irgen_VFCx(v1, v3, v2, m4, m5, m6, "vfch", Ircr_LT, - False, Iop_CmpLT32Fx4, Iop_CmpLT64Fx2); + s390_irgen_VFCx(v1, v3, v2, m4, m5, m6, Ircr_LT, + False, Iop_CmpLT32Fx4, Iop_CmpLT64Fx2); } -static const HChar * +static void s390_irgen_VFCHE(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { /* Swap arguments and compare "low or equal" instead. */ - return s390_irgen_VFCx(v1, v3, v2, m4, m5, m6, "vfche", Ircr_LT, - True, Iop_CmpLE32Fx4, Iop_CmpLE64Fx2); + s390_irgen_VFCx(v1, v3, v2, m4, m5, m6, Ircr_LT, + True, Iop_CmpLE32Fx4, Iop_CmpLE64Fx2); } -static const HChar * +static void s390_irgen_VFTCI(UChar v1, UChar v2, UShort i3, UChar m4, UChar m5) { - s390_insn_assert("vftci", - (m4 == 3 || (s390_host_has_vxe && m4 >= 2 && m4 <= 4))); - s390_insn_assert("vftci", (m5 & 0x7) == 0); + s390_insn_assert((m4 == 3 || (s390_host_has_vxe && m4 >= 2 && m4 <= 4))); + s390_insn_assert((m5 & 0x7) == 0); Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5); @@ -19440,21 +17465,19 @@ s390_irgen_VFTCI(UChar v1, UChar v2, UShort i3, UChar m4, UChar m5) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); - - return "vftci"; } -static const HChar * +static void s390_irgen_VFMIN(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vfmin"; + return; } - s390_insn_assert("vfmin", m4 >= 2 && m4 <= 4); - s390_insn_assert("vfmin", (m5 & 0x7) == 0); - s390_insn_assert("vfmin", m6 <= 4 || (m6 >= 8 && m6 <= 12)); + s390_insn_assert(m4 >= 2 && m4 <= 4); + s390_insn_assert((m5 & 0x7) == 0); + s390_insn_assert(m6 <= 4 || (m6 >= 8 && m6 <= 12)); Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5); IRDirty* d; @@ -19488,20 +17511,19 @@ s390_irgen_VFMIN(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) d->fxState[2].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - return "vfmin"; } -static const HChar * +static void s390_irgen_VFMAX(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vfmax"; + return; } - s390_insn_assert("vfmax", m4 >= 2 && m4 <= 4); - s390_insn_assert("vfmax", (m5 & 0x7) == 0); - s390_insn_assert("vfmax", m6 <= 4 || (m6 >= 8 && m6 <= 12)); + s390_insn_assert(m4 >= 2 && m4 <= 4); + s390_insn_assert((m5 & 0x7) == 0); + s390_insn_assert(m6 <= 4 || (m6 >= 8 && m6 <= 12)); Bool isSingleElementOp = s390_vr_is_single_element_control_set(m5); IRDirty* d; @@ -19535,15 +17557,14 @@ s390_irgen_VFMAX(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) d->fxState[2].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - return "vfmax"; } -static const HChar * +static void s390_irgen_VBPERM(UChar v1, UChar v2, UChar v3) { if (! s390_host_has_vxe) { emulation_failure(EmFail_S390X_vxe); - return "vbperm"; + return; } IRDirty* d; @@ -19577,31 +17598,27 @@ s390_irgen_VBPERM(UChar v1, UChar v2, UChar v3) stmt(IRStmt_Dirty(d)); s390_cc_set(cc); - return "vbperm"; } -static const HChar * +static void s390_irgen_SELR(UChar r3, UChar m4, UChar r1, UChar r2) { IRExpr* cond = binop(Iop_CmpNE32, s390_call_calculate_cond(m4), mkU32(0)); put_gpr_w1(r1, mkite(cond, get_gpr_w1(r2), get_gpr_w1(r3))); - return "selr"; } -static const HChar * +static void s390_irgen_SELGR(UChar r3, UChar m4, UChar r1, UChar r2) { IRExpr* cond = binop(Iop_CmpNE32, s390_call_calculate_cond(m4), mkU32(0)); put_gpr_dw0(r1, mkite(cond, get_gpr_dw0(r2), get_gpr_dw0(r3))); - return "selgr"; } -static const HChar * +static void s390_irgen_SELFHR(UChar r3, UChar m4, UChar r1, UChar r2) { IRExpr* cond = binop(Iop_CmpNE32, s390_call_calculate_cond(m4), mkU32(0)); put_gpr_w0(r1, mkite(cond, get_gpr_w0(r2), get_gpr_w0(r3))); - return "selfhr"; } /* Helper function that byte-swaps each element of its V128 input operand */ @@ -19633,60 +17650,56 @@ s390_reverse_elements(IRExpr* v, UChar m) mkU64(perm[m - 1][1]))); } -static const HChar * +static void s390_irgen_VLBR(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vlbr"; + return; } - s390_insn_assert("vlbr", m3 >= 1 && m3 <= 4); + s390_insn_assert(m3 >= 1 && m3 <= 4); put_vr_qw(v1, s390_byteswap_elements(load(Ity_V128, mkexpr(op2addr)), m3)); - return "vlbr"; } -static const HChar * +static void s390_irgen_VSTBR(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vstbr"; + return; } - s390_insn_assert("vstbr", m3 >= 1 && m3 <= 4); + s390_insn_assert(m3 >= 1 && m3 <= 4); store(mkexpr(op2addr), s390_byteswap_elements(get_vr_qw(v1), m3)); - return "vstbr"; } -static const HChar * +static void s390_irgen_VLER(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vler"; + return; } - s390_insn_assert("vler", m3 >= 1 && m3 <= 3); + s390_insn_assert(m3 >= 1 && m3 <= 3); put_vr_qw(v1, s390_reverse_elements(load(Ity_V128, mkexpr(op2addr)), m3)); - return "vler"; } -static const HChar * +static void s390_irgen_VSTER(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vster"; + return; } - s390_insn_assert("vster", m3 >= 1 && m3 <= 4); + s390_insn_assert(m3 >= 1 && m3 <= 4); store(mkexpr(op2addr), s390_reverse_elements(get_vr_qw(v1), m3)); - return "vster"; } /* Helper function that combines its two V128 operands by replacing element 'to' @@ -19712,33 +17725,32 @@ s390_insert_byteswapped(IRExpr* a, IRExpr* b, UChar m, UChar to, UChar from) mkU64(permH), mkU64(permL))); } -static const HChar * +static void s390_irgen_VLEBRH(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vlebrh"; + return; } - s390_insn_assert("vlebrh", m3 <= 7); + s390_insn_assert(m3 <= 7); IRTemp op2 = newTemp(Ity_I16); assign(op2, load(Ity_I16, mkexpr(op2addr))); put_vr(v1, Ity_I16, m3, binop(Iop_Or16, binop(Iop_Shl16, mkexpr(op2), mkU8(8)), binop(Iop_Shr16, mkexpr(op2), mkU8(8)))); - return "vlebrh"; } -static const HChar * +static void s390_irgen_VLEBRF(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vlebrf"; + return; } - s390_insn_assert("vlebrf", m3 <= 3); + s390_insn_assert(m3 <= 3); IRTemp op1 = newTemp(Ity_V128); assign(op1, get_vr_qw(v1)); @@ -19746,18 +17758,17 @@ s390_irgen_VLEBRF(UChar v1, IRTemp op2addr, UChar m3) assign(op2, unop(Iop_32Uto64, load(Ity_I32, mkexpr(op2addr)))); IRExpr* b = binop(Iop_64HLtoV128, mkexpr(op2), mkexpr(op2)); put_vr_qw(v1, s390_insert_byteswapped(mkexpr(op1), b, 2, m3, 3)); - return "vlebrf"; } -static const HChar * +static void s390_irgen_VLEBRG(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vlebrg"; + return; } - s390_insn_assert("vlebrg", m3 <= 1); + s390_insn_assert(m3 <= 1); IRTemp op1 = newTemp(Ity_V128); assign(op1, get_vr_qw(v1)); @@ -19765,18 +17776,17 @@ s390_irgen_VLEBRG(UChar v1, IRTemp op2addr, UChar m3) assign(op2, load(Ity_I64, mkexpr(op2addr))); IRExpr* b = binop(Iop_64HLtoV128, mkexpr(op2), mkexpr(op2)); put_vr_qw(v1, s390_insert_byteswapped(mkexpr(op1), b, 3, m3, 1)); - return "vlebrg"; } -static const HChar * +static void s390_irgen_VLBRREP(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vlbrrep"; + return; } - s390_insn_assert("vlbrrep", m3 >= 1 && m3 <= 3); + s390_insn_assert(m3 >= 1 && m3 <= 3); static const ULong perm[3] = { 0x0f0e0f0e0f0e0f0e, /* 2-byte element */ @@ -19793,18 +17803,17 @@ s390_irgen_VLBRREP(UChar v1, IRTemp op2addr, UChar m3) put_vr_qw(v1, binop(Iop_Perm8x16, binop(Iop_64HLtoV128, mkexpr(op2), mkexpr(op2)), binop(Iop_64HLtoV128, permHL, permHL))); - return "vlbrrep"; } -static const HChar * +static void s390_irgen_VLLEBRZ(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vllebrz"; + return; } - s390_insn_assert("vllebrz", (m3 >= 1 && m3 <= 3) || m3 == 6); + s390_insn_assert((m3 >= 1 && m3 <= 3) || m3 == 6); static const ULong perm[6] = { 0x0000000000000f0e, /* 2-byte element */ @@ -19824,68 +17833,64 @@ s390_irgen_VLLEBRZ(UChar v1, IRTemp op2addr, UChar m3) put_vr_qw(v1, binop(Iop_Perm8x16, binop(Iop_64HLtoV128, mkU64(0), mkexpr(op2)), binop(Iop_64HLtoV128, permH, mkU64(0)))); - return "vllebrz"; } -static const HChar * +static void s390_irgen_VSTEBRH(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vstebrh"; + return; } - s390_insn_assert("vstebrh", m3 <= 7); + s390_insn_assert(m3 <= 7); IRTemp op1 = newTemp(Ity_I16); assign(op1, get_vr(v1, Ity_I16, m3)); store(mkexpr(op2addr), binop(Iop_Or16, binop(Iop_Shl16, mkexpr(op1), mkU8(8)), binop(Iop_Shr16, mkexpr(op1), mkU8(8)))); - return "vstebrh"; } -static const HChar * +static void s390_irgen_VSTEBRF(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vstebrf"; + return; } - s390_insn_assert("vstebrf", m3 <= 3); + s390_insn_assert(m3 <= 3); IRTemp op1 = newTemp(Ity_V128); assign(op1, get_vr_qw(v1)); IRExpr* b = s390_insert_byteswapped(mkexpr(op1), mkexpr(op1), 2, 3, m3); store(mkexpr(op2addr), unop(Iop_V128to32, b)); - return "vstebrf"; } -static const HChar * +static void s390_irgen_VSTEBRG(UChar v1, IRTemp op2addr, UChar m3) { if (! s390_host_has_vxe2) { emulation_failure(EmFail_S390X_vxe2); - return "vstebrg"; + return; } - s390_insn_assert("vstebrg", m3 <= 1); + s390_insn_assert(m3 <= 1); IRTemp op1 = newTemp(Ity_V128); assign(op1, get_vr_qw(v1)); IRExpr* b = s390_insert_byteswapped(mkexpr(op1), mkexpr(op1), 3, 1, m3); store(mkexpr(op2addr), unop(Iop_V128to64, b)); - return "vstebrg"; } -static const HChar * -s390_irgen_VCxx(const HChar *mnem, s390x_vec_op_details_t details, +static void +s390_irgen_VCxx(s390x_vec_op_details_t details, UShort v2_offs, UShort v2_size) { if (! s390_host_has_nnpa) { emulation_failure(EmFail_S390X_nnpa); - return mnem; + return; } IRDirty* d = unsafeIRDirty_0_N(0, "s390x_dirtyhelper_vec_op", @@ -19904,10 +17909,9 @@ s390_irgen_VCxx(const HChar *mnem, s390x_vec_op_details_t details, d->fxState[1].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - return mnem; } -static const HChar * +static void s390_irgen_VCNF(UChar v1, UChar v2, UChar m3, UChar m4) { s390x_vec_op_details_t details = { .serialized = 0ULL }; @@ -19916,10 +17920,10 @@ s390_irgen_VCNF(UChar v1, UChar v2, UChar m3, UChar m4) details.v2 = v2; details.m3 = m3; details.m4 = m4; - return s390_irgen_VCxx("vcnf", details, 0, sizeof(V128)); + s390_irgen_VCxx( details, 0, sizeof(V128)); } -static const HChar * +static void s390_irgen_VCLFNH(UChar v1, UChar v2, UChar m3, UChar m4) { s390x_vec_op_details_t details = { .serialized = 0ULL }; @@ -19928,10 +17932,10 @@ s390_irgen_VCLFNH(UChar v1, UChar v2, UChar m3, UChar m4) details.v2 = v2; details.m3 = m3; details.m4 = m4; - return s390_irgen_VCxx("vclfnh", details, 0, sizeof(V128) / 2); + s390_irgen_VCxx(details, 0, sizeof(V128) / 2); } -static const HChar * +static void s390_irgen_VCFN(UChar v1, UChar v2, UChar m3, UChar m4) { s390x_vec_op_details_t details = { .serialized = 0ULL }; @@ -19940,10 +17944,10 @@ s390_irgen_VCFN(UChar v1, UChar v2, UChar m3, UChar m4) details.v2 = v2; details.m3 = m3; details.m4 = m4; - return s390_irgen_VCxx("vcfn", details, 0, sizeof(V128)); + s390_irgen_VCxx(details, 0, sizeof(V128)); } -static const HChar * +static void s390_irgen_VCLFNL(UChar v1, UChar v2, UChar m3, UChar m4) { s390x_vec_op_details_t details = { .serialized = 0ULL }; @@ -19952,16 +17956,15 @@ s390_irgen_VCLFNL(UChar v1, UChar v2, UChar m3, UChar m4) details.v2 = v2; details.m3 = m3; details.m4 = m4; - return s390_irgen_VCxx("vclfnl", details, sizeof(V128) / 2, - sizeof(V128) / 2); + s390_irgen_VCxx(details, sizeof(V128) / 2, sizeof(V128) / 2); } -static const HChar * +static void s390_irgen_VCRNF(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { if (! s390_host_has_nnpa) { emulation_failure(EmFail_S390X_nnpa); - return "vcrnf"; + return; } s390x_vec_op_details_t details = { .serialized = 0ULL }; @@ -19989,149 +17992,132 @@ s390_irgen_VCRNF(UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) d->fxState[2].size = sizeof(V128); stmt(IRStmt_Dirty(d)); - return "vcrnf"; } -static const HChar * +static void s390_irgen_NNPA(void) { if (! s390_host_has_nnpa) { emulation_failure(EmFail_S390X_nnpa); - return "nnpa"; + return; } extension(S390_EXT_NNPA, 0); - return "nnpa"; } -static const HChar * +static void s390_irgen_KM(UChar r1, UChar r2) { - s390_insn_assert("km", r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KM, r1 | (r2 << 4)); - return "km"; } -static const HChar * +static void s390_irgen_KMC(UChar r1, UChar r2) { - s390_insn_assert("kmc", r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KMC, r1 | (r2 << 4)); - return "kmc"; } -static const HChar * +static void s390_irgen_KIMD(UChar r1, UChar r2) { /* r1 is reserved */ - s390_insn_assert("kimd", r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KIMD, r1 | (r2 << 4)); - return "kimd"; } -static const HChar * +static void s390_irgen_KLMD(UChar r1, UChar r2) { /* r1 is only used by some functions */ - s390_insn_assert("klmd", r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KLMD, r1 | (r2 << 4)); - return "klmd"; } -static const HChar * +static void s390_irgen_KMAC(UChar r1, UChar r2) { /* r1 is ignored */ - s390_insn_assert("kmac", r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KMAC, r1 | (r2 << 4)); - return "kmac"; } -static const HChar * +static void s390_irgen_PCC(void) { extension(S390_EXT_PCC, 0); - return "pcc"; } -static const HChar * +static void s390_irgen_KMCTR(UChar r3, UChar r1, UChar r2) { - s390_insn_assert("kmctr", r1 % 2 == 0 && r1 != 0 && r2 % 2 == 0 && r2 != 0 && + s390_insn_assert(r1 % 2 == 0 && r1 != 0 && r2 % 2 == 0 && r2 != 0 && r3 % 2 == 0 && r3 != 0); extension(S390_EXT_KMCTR, r1 | (r2 << 4) | (r3 << 8)); - return "kmctr"; } -static const HChar * +static void s390_irgen_KMO(UChar r1, UChar r2) { - s390_insn_assert("kmo", r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KMO, r1 | (r2 << 4)); - return "kmo"; } -static const HChar * +static void s390_irgen_KMF(UChar r1, UChar r2) { - s390_insn_assert("kmf", r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r1 != 0 && r1 % 2 == 0 && r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KMF, r1 | (r2 << 4)); - return "kmf"; } -static const HChar * +static void s390_irgen_KMA(UChar r3, UChar r1, UChar r2) { if (! s390_host_has_msa8) { emulation_failure(EmFail_S390X_msa8); - return "kma"; + return; } - s390_insn_assert("kma", r1 % 2 == 0 && r1 != 0 && r2 % 2 == 0 && r2 != 0 && + s390_insn_assert(r1 % 2 == 0 && r1 != 0 && r2 % 2 == 0 && r2 != 0 && r3 % 2 == 0 && r3 != 0 && r3 != r1 && r3 != r2); extension(S390_EXT_KMA, r1 | (r2 << 4) | (r3 << 8)); - return "kma"; } -static const HChar * +static void s390_irgen_KDSA(UChar r1, UChar r2) { if (! s390_host_has_msa9) { emulation_failure(EmFail_S390X_msa9); - return "kdsa"; + return; } /* r1 is reserved */ - s390_insn_assert("kdsa", r2 != 0 && r2 % 2 == 0); + s390_insn_assert(r2 != 0 && r2 % 2 == 0); extension(S390_EXT_KDSA, r1 | (r2 << 4)); - return "kdsa"; } -static const HChar * +static void s390_irgen_BPP(UChar m1, UShort i2, IRTemp op3addr) { /* Treat as a no-op */ - return "bpp"; } -static const HChar * +static void s390_irgen_BPRP(UChar m1, UShort i2, UInt i3) { /* Treat as a no-op */ - return "bprp"; } -static const HChar * +static void s390_irgen_NIAI(UChar i1, UChar i2) { /* Treat as a no-op */ - return "niai"; } -static const HChar * +static void s390_irgen_PPA(UChar m3, UChar r1, UChar r2) { /* Treat as a no-op. m3 could indicate one of the following: 1: transaction-abort assist -- fine, we don't support transactions 15: in-order-execution assist -- we don't claim support */ - return "ppa"; } /* New insns are added here. @@ -20994,11 +18980,10 @@ s390_decode_4byte_and_irgen(const UChar *bytes) RRF2_m4(ovl), RRF2_r1(ovl), RRF2_r2(ovl)); goto ok; case 0xb960: s390_format_RRF_U0RR(s390_irgen_CGRT, RRF2_m3(ovl), - RRF2_r1(ovl), RRF2_r2(ovl), - cabt_disasm); goto ok; + RRF2_r1(ovl), RRF2_r2(ovl) + ); goto ok; case 0xb961: s390_format_RRF_U0RR(s390_irgen_CLGRT, RRF2_m3(ovl), - RRF2_r1(ovl), RRF2_r2(ovl), - cabt_disasm); goto ok; + RRF2_r1(ovl), RRF2_r2(ovl)); goto ok; case 0xb964: s390_format_RRF_R0RR2(s390_irgen_NNGRK, RRF4_r3(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; case 0xb965: s390_format_RRF_R0RR2(s390_irgen_OCGRK, RRF4_r3(ovl), @@ -21012,11 +18997,9 @@ s390_decode_4byte_and_irgen(const UChar *bytes) case 0xb96c: /* BEXTG */ goto unimplemented; case 0xb96d: /* BDEPG */ goto unimplemented; case 0xb972: s390_format_RRF_U0RR(s390_irgen_CRT, RRF2_m3(ovl), - RRF2_r1(ovl), RRF2_r2(ovl), - cabt_disasm); goto ok; + RRF2_r1(ovl), RRF2_r2(ovl)); goto ok; case 0xb973: s390_format_RRF_U0RR(s390_irgen_CLRT, RRF2_m3(ovl), - RRF2_r1(ovl), RRF2_r2(ovl), - cabt_disasm); goto ok; + RRF2_r1(ovl), RRF2_r2(ovl)); goto ok; case 0xb974: s390_format_RRF_R0RR2(s390_irgen_NNRK, RRF4_r3(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; case 0xb975: s390_format_RRF_R0RR2(s390_irgen_OCRK, RRF4_r3(ovl), @@ -21130,13 +19113,11 @@ s390_decode_4byte_and_irgen(const UChar *bytes) case 0xb9df: s390_format_RRE_RR(s390_irgen_CLHLR, RRE_r1(ovl), RRE_r2(ovl)); goto ok; case 0xb9e0: s390_format_RRF_U0RR(s390_irgen_LOCFHR, RRF3_r3(ovl), - RRF3_r1(ovl), RRF3_r2(ovl), - cls_disasm); goto ok; + RRF3_r1(ovl), RRF3_r2(ovl)); goto ok; case 0xb9e1: s390_format_RRFa_U0RR(s390_irgen_POPCNT, RRF3_r3(ovl), RRF3_r1(ovl), RRF3_r2(ovl)); goto ok; case 0xb9e2: s390_format_RRF_U0RR(s390_irgen_LOCGR, RRF3_r3(ovl), - RRF3_r1(ovl), RRF3_r2(ovl), - cls_disasm); goto ok; + RRF3_r1(ovl), RRF3_r2(ovl)); goto ok; case 0xb9e3: s390_format_RRF_RURR(s390_irgen_SELGR, RRF4_r3(ovl), RRF4_m4(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; @@ -21174,8 +19155,7 @@ s390_decode_4byte_and_irgen(const UChar *bytes) RRF4_m4(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; case 0xb9f2: s390_format_RRF_U0RR(s390_irgen_LOCR, RRF3_r3(ovl), - RRF3_r1(ovl), RRF3_r2(ovl), - cls_disasm); goto ok; + RRF3_r1(ovl), RRF3_r2(ovl)); goto ok; case 0xb9f4: s390_format_RRF_R0RR2(s390_irgen_NRK, RRF4_r3(ovl), RRF4_r1(ovl), RRF4_r2(ovl)); goto ok; @@ -21813,56 +19793,56 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe60000000001ULL: s390_format_VRX_VRRDM(s390_irgen_VLEBRH, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000002ULL: s390_format_VRX_VRRDM(s390_irgen_VLEBRG, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000003ULL: s390_format_VRX_VRRDM(s390_irgen_VLEBRF, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000004ULL: s390_format_VRX_VRRDM(s390_irgen_VLLEBRZ, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), vllebrz_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000005ULL: s390_format_VRX_VRRDM(s390_irgen_VLBRREP, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), va_like_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000006ULL: s390_format_VRX_VRRDM(s390_irgen_VLBR, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), va_like_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000007ULL: s390_format_VRX_VRRDM(s390_irgen_VLER, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), va_like_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000009ULL: s390_format_VRX_VRRDM(s390_irgen_VSTEBRH, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe6000000000aULL: s390_format_VRX_VRRDM(s390_irgen_VSTEBRG, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), vstebrg_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe6000000000bULL: s390_format_VRX_VRRDM(s390_irgen_VSTEBRF, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), vstebrf_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe6000000000eULL: s390_format_VRX_VRRDM(s390_irgen_VSTBR, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), va_like_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe6000000000fULL: s390_format_VRX_VRRDM(s390_irgen_VSTER, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), va_like_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe60000000034ULL: /* VPKZ */ goto unimplemented; case 0xe60000000035ULL: s390_format_VSI_URDV(s390_irgen_VLRL, VSI_v1(ovl), VSI_b2(ovl), VSI_d2(ovl), @@ -21891,19 +19871,19 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe60000000055ULL: s390_format_VRRa_VVMM(s390_irgen_VCNF, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), NULL); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe60000000056ULL: s390_format_VRRa_VVMM(s390_irgen_VCLFNH, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), NULL); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe6000000005dULL: s390_format_VRRa_VVMM(s390_irgen_VCFN, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), NULL); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe6000000005eULL: s390_format_VRRa_VVMM(s390_irgen_VCLFNL, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), NULL); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe60000000058ULL: /* VCVD */ goto unimplemented; case 0xe60000000059ULL: /* VSRP */ goto unimplemented; case 0xe6000000005aULL: /* VCVDG */ goto unimplemented; @@ -21918,7 +19898,7 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRRa_v1(ovl), VRRa_v2(ovl), VRRa_v3(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), NULL); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe60000000077ULL: /* VCP */ goto unimplemented; case 0xe60000000078ULL: /* VMP */ goto unimplemented; case 0xe60000000079ULL: /* VMSP */ goto unimplemented; @@ -21932,27 +19912,27 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe70000000000ULL: s390_format_VRX_VRRDM(s390_irgen_VLEB, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000001ULL: s390_format_VRX_VRRDM(s390_irgen_VLEH, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000002ULL: s390_format_VRX_VRRDM(s390_irgen_VLEG, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000003ULL: s390_format_VRX_VRRDM(s390_irgen_VLEF, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000004ULL: s390_format_VRX_VRRDM(s390_irgen_VLLEZ, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), vllez_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000005ULL: s390_format_VRX_VRRDM(s390_irgen_VLREP, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), va_like_disasm); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000006ULL: s390_format_VRX_VRRD(s390_irgen_VL, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), @@ -21960,23 +19940,23 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe70000000007ULL: s390_format_VRX_VRRDM(s390_irgen_VLBB, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000008ULL: s390_format_VRX_VRRDM(s390_irgen_VSTEB, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe70000000009ULL: s390_format_VRX_VRRDM(s390_irgen_VSTEH, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe7000000000aULL: s390_format_VRX_VRRDM(s390_irgen_VSTEG, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe7000000000bULL: s390_format_VRX_VRRDM(s390_irgen_VSTEF, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), - VRX_rxb(ovl), NULL); goto ok; + VRX_rxb(ovl)); goto ok; case 0xe7000000000eULL: s390_format_VRX_VRRD(s390_irgen_VST, VRX_v1(ovl), VRX_x2(ovl), VRX_b2(ovl), VRX_d2(ovl), VRX_m3(ovl), @@ -22045,10 +20025,9 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRI_rxb(ovl)); goto ok; case 0xe70000000043ULL: s390_format_VRI_VIM(s390_irgen_VLEIF, VRI_v1(ovl), VRI_i2(ovl), VRI_m3(ovl), - VRI_rxb(ovl)); goto ok;break; + VRI_rxb(ovl)); goto ok; case 0xe70000000044ULL: s390_format_VRI_V0U(s390_irgen_VGBM, VRI_v1(ovl), - VRI_i2(ovl), VRI_rxb(ovl), - vgbm_disasm); goto ok; + VRI_i2(ovl), VRI_rxb(ovl)); goto ok; case 0xe70000000045ULL: s390_format_VRI_V0IU(s390_irgen_VREPI, VRI_v1(ovl), VRI_i2(ovl), VRI_m3(ovl), VRI_rxb(ovl)); goto ok; @@ -22164,16 +20143,16 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRR_rxb(ovl)); goto ok; case 0xe70000000080ULL: s390_format_VRR_VVVMM(s390_irgen_VFEE, VRR_v1(ovl), VRR_v2(ovl), VRR_r3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vfae_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe70000000081ULL: s390_format_VRR_VVVMM(s390_irgen_VFENE, VRR_v1(ovl), VRR_v2(ovl), VRR_r3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vfae_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe70000000082ULL: s390_format_VRR_VVVMM(s390_irgen_VFAE, VRR_v1(ovl), VRR_v2(ovl), VRR_r3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vfae_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe70000000084ULL: s390_format_VRR_VVVM(s390_irgen_VPDI, VRR_v1(ovl), VRR_v2(ovl), VRR_r3(ovl), VRR_m4(ovl), VRR_rxb(ovl)); goto ok; @@ -22193,13 +20172,13 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe7000000008aULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRC, VRRd_v1(ovl), VRRd_v2(ovl), VRRd_v3(ovl), VRRd_v4(ovl), VRRd_m5(ovl), - VRRd_m6(ovl), VRRd_rxb(ovl), - vstrc_disasm); goto ok; + VRRd_m6(ovl), VRRd_rxb(ovl) + ); goto ok; case 0xe7000000008bULL: s390_format_VRR_VVVVMM(s390_irgen_VSTRS, VRRd_v1(ovl), VRRd_v2(ovl), VRRd_v3(ovl), VRRd_v4(ovl), VRRd_m5(ovl), - VRRd_m6(ovl), VRRd_rxb(ovl), - vfae_like_disasm); goto ok; + VRRd_m6(ovl), VRRd_rxb(ovl) + ); goto ok; case 0xe7000000008cULL: s390_format_VRR_VVVV(s390_irgen_VPERM, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), VRR_v4(ovl), VRR_rxb(ovl)); goto ok; @@ -22209,34 +20188,34 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe7000000008eULL: s390_format_VRR_VVVVMM(s390_irgen_VFMS, VRRe_v1(ovl), VRRe_v2(ovl), VRRe_v3(ovl), VRRe_v4(ovl), VRRe_m5(ovl), - VRRe_m6(ovl), VRRe_rxb(ovl), - vfms_like_disasm); goto ok; + VRRe_m6(ovl), VRRe_rxb(ovl) + ); goto ok; case 0xe7000000008fULL: s390_format_VRR_VVVVMM(s390_irgen_VFMA, VRRe_v1(ovl), VRRe_v2(ovl), VRRe_v3(ovl), VRRe_v4(ovl), VRRe_m5(ovl), - VRRe_m6(ovl), VRRe_rxb(ovl), - vfms_like_disasm); goto ok; + VRRe_m6(ovl), VRRe_rxb(ovl) + ); goto ok; case 0xe70000000094ULL: s390_format_VRR_VVVM(s390_irgen_VPK, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), VRR_m4(ovl), VRR_rxb(ovl)); goto ok; case 0xe70000000095ULL: s390_format_VRR_VVVMM(s390_irgen_VPKLS, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vch_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe70000000097ULL: s390_format_VRR_VVVMM(s390_irgen_VPKS, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vch_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe7000000009eULL: s390_format_VRR_VVVVMM(s390_irgen_VFNMS, VRRe_v1(ovl), VRRe_v2(ovl), VRRe_v3(ovl), VRRe_v4(ovl), VRRe_m5(ovl), - VRRe_m6(ovl), VRRe_rxb(ovl), - vfms_like_disasm); goto ok; + VRRe_m6(ovl), VRRe_rxb(ovl) + ); goto ok; case 0xe7000000009fULL: s390_format_VRR_VVVVMM(s390_irgen_VFNMA, VRRe_v1(ovl), VRRe_v2(ovl), VRRe_v3(ovl), VRRe_v4(ovl), VRRe_m5(ovl), - VRRe_m6(ovl), VRRe_rxb(ovl), - vfms_like_disasm); goto ok; + VRRe_m6(ovl), VRRe_rxb(ovl) + ); goto ok; case 0xe700000000a1ULL: s390_format_VRR_VVVM(s390_irgen_VMLH, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), VRR_m4(ovl), VRR_rxb(ovl)); goto ok; @@ -22296,8 +20275,8 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe700000000b8ULL: s390_format_VRR_VVVVMM(s390_irgen_VMSL, VRRd_v1(ovl), VRRd_v2(ovl), VRRd_v3(ovl), VRRd_v4(ovl), VRRd_m5(ovl), - VRRd_m6(ovl), VRRd_rxb(ovl), - vmsl_disasm); goto ok; + VRRd_m6(ovl), VRRd_rxb(ovl) + ); goto ok; case 0xe700000000b9ULL: s390_format_VRRd_VVVVM(s390_irgen_VACCC, VRRd_v1(ovl), VRRd_v2(ovl), VRRd_v3(ovl), VRRd_v4(ovl), VRRd_m5(ovl), @@ -22336,8 +20315,8 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRRa_rxb(ovl)); goto ok; case 0xe700000000c4ULL: s390_format_VRRa_VVMM(s390_irgen_VFLL, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), - VRRa_m4(ovl), VRRa_rxb(ovl), - vfll_disasm); goto ok; + VRRa_m4(ovl), VRRa_rxb(ovl) + ); goto ok; case 0xe700000000c5ULL: s390_format_VRRa_VVMMM(s390_irgen_VFLR, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), VRRa_m5(ovl), @@ -22348,12 +20327,12 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRRa_rxb(ovl)); goto ok; case 0xe700000000caULL: s390_format_VRRa_VVMM(s390_irgen_WFK, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), - VRRa_m4(ovl), VRRa_rxb(ovl), - wfc_like_disasm); goto ok; + VRRa_m4(ovl), VRRa_rxb(ovl) + ); goto ok; case 0xe700000000cbULL: s390_format_VRRa_VVMM(s390_irgen_WFC, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), - VRRa_m4(ovl), VRRa_rxb(ovl), - wfc_like_disasm); goto ok; + VRRa_m4(ovl), VRRa_rxb(ovl) + ); goto ok; case 0xe700000000ccULL: s390_format_VRRa_VVMMM(s390_irgen_VFPSO, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), VRRa_m5(ovl), @@ -22361,7 +20340,7 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe700000000ceULL: s390_format_VRRa_VVMM(s390_irgen_VFSQ, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), vfmix_like_disasm); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe700000000d4ULL: s390_format_VRR_VVM(s390_irgen_VUPLL, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_m3(ovl), VRRa_rxb(ovl)); goto ok; @@ -22391,19 +20370,19 @@ s390_decode_6byte_and_irgen(const UChar *bytes) case 0xe700000000e2ULL: s390_format_VRRa_VVVMM(s390_irgen_VFS, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_v3(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), vfa_like_disasm); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe700000000e3ULL: s390_format_VRRa_VVVMM(s390_irgen_VFA, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_v3(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), vfa_like_disasm); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe700000000e5ULL: s390_format_VRRa_VVVMM(s390_irgen_VFD, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_v3(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), vfa_like_disasm); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe700000000e7ULL: s390_format_VRRa_VVVMM(s390_irgen_VFM, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_v3(ovl), VRRa_m3(ovl), VRRa_m4(ovl), - VRRa_rxb(ovl), vfa_like_disasm); goto ok; + VRRa_rxb(ovl)); goto ok; case 0xe700000000e8ULL: s390_format_VRRa_VVVMMM(s390_irgen_VFCE, VRRa_v1(ovl), VRRa_v2(ovl), VRRa_v3(ovl), VRRa_m3(ovl), VRRa_m4(ovl), @@ -22449,16 +20428,16 @@ s390_decode_6byte_and_irgen(const UChar *bytes) VRR_m4(ovl), VRR_rxb(ovl)); goto ok; case 0xe700000000f8ULL: s390_format_VRR_VVVMM(s390_irgen_VCEQ, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vch_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe700000000f9ULL: s390_format_VRR_VVVMM(s390_irgen_VCHL, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vch_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe700000000fbULL: s390_format_VRR_VVVMM(s390_irgen_VCH, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), - VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl), - vch_like_disasm); goto ok; + VRR_m4(ovl), VRR_m5(ovl), VRR_rxb(ovl) + ); goto ok; case 0xe700000000fcULL: s390_format_VRR_VVVM(s390_irgen_VMNL, VRR_v1(ovl), VRR_v2(ovl), VRR_v3(ovl), VRR_m4(ovl), VRR_rxb(ovl)); goto ok; @@ -23309,6 +21288,9 @@ s390_decode_and_irgen(const UChar *bytes, UInt insn_length, DisResult *dres) s390_decode_special_and_irgen(bytes + S390_SPECIAL_OP_PREAMBLE_SIZE); } else { /* Handle normal instructions. */ + if (UNLIKELY(vex_traceflags & VEX_TRACE_FE)) + s390_disasm(bytes); + switch (insn_length) { case 2: status = s390_decode_2byte_and_irgen(bytes); diff --git a/VEX/priv/host_s390_defs.c b/VEX/priv/host_s390_defs.c index 3205060b5..d0b7de838 100644 --- a/VEX/priv/host_s390_defs.c +++ b/VEX/priv/host_s390_defs.c @@ -40,7 +40,6 @@ #include "host_s390_defs.h" #include "s390_disasm.h" #include "guest_s390_defs.h" /* S390X_GUEST_OFFSET */ -#include /*------------------------------------------------------------*/ /*--- Forward declarations ---*/ @@ -1471,24 +1470,40 @@ s390_insn_map_regs(HRegRemap *m, s390_insn *insn) /*--- Functions to emit a sequence of bytes ---*/ /*------------------------------------------------------------*/ +static __inline__ UChar * +emit(UChar *p, const UChar *insn, UInt len) +{ + if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) + s390_disasm(insn); + + return (UChar *)__builtin_memcpy(p, insn, len) + len; +} + + static __inline__ UChar * emit_2bytes(UChar *p, ULong val) { - return (UChar *)__builtin_memcpy(p, ((UChar *)&val) + 6, 2) + 2; + const UChar *insn = (UChar *)&val + 6; + + return emit(p, insn, 2); } static __inline__ UChar * emit_4bytes(UChar *p, ULong val) { - return (UChar *)__builtin_memcpy(p, ((UChar *)&val) + 4, 4) + 4; + const UChar *insn = (UChar *)&val + 4; + + return emit(p, insn, 4); } static __inline__ UChar * emit_6bytes(UChar *p, ULong val) { - return (UChar *)__builtin_memcpy(p, ((UChar *)&val) + 2, 6) + 6; + const UChar *insn = (UChar *)&val + 2; + + return emit(p, insn, 6); } @@ -2001,9 +2016,6 @@ emit_VRR_VVVMM(UChar *p, ULong op, UChar v1, UChar v2, UChar v3, UChar m4, static UChar * s390_emit_AR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ar"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1a00, r1, r2); } @@ -2011,9 +2023,6 @@ s390_emit_AR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_AGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("agr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9080000, r1, r2); } @@ -2021,9 +2030,6 @@ s390_emit_AGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_A(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("a"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x5a000000, r1, x2, b2, d2); } @@ -2031,9 +2037,6 @@ s390_emit_A(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_AY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ay"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000005aULL, r1, x2, b2, dl2, dh2); } @@ -2041,9 +2044,6 @@ s390_emit_AY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_AG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ag"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000008ULL, r1, x2, b2, dl2, dh2); } @@ -2051,9 +2051,6 @@ s390_emit_AG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_AFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("afi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc20900000000ULL, r1, i2); } @@ -2061,9 +2058,6 @@ s390_emit_AFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_AGFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("agfi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc20800000000ULL, r1, i2); } @@ -2071,9 +2065,6 @@ s390_emit_AGFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_AH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ah"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x4a000000, r1, x2, b2, d2); } @@ -2081,9 +2072,6 @@ s390_emit_AH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_AHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ahy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000007aULL, r1, x2, b2, dl2, dh2); } @@ -2091,9 +2079,6 @@ s390_emit_AHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_AHI(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ahi"), GPR(r1), INT((Int)(Short)i2)); - return emit_RI(p, 0xa70a0000, r1, i2); } @@ -2101,9 +2086,6 @@ s390_emit_AHI(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_AGHI(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("aghi"), GPR(r1), INT((Int)(Short)i2)); - return emit_RI(p, 0xa70b0000, r1, i2); } @@ -2111,9 +2093,6 @@ s390_emit_AGHI(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_AGSI(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("agsi"), SDXB(dh1, dl1, 0, b1), INT((Int)(Char)i2)); - return emit_SIY(p, 0xeb000000007aULL, i2, b1, dl1, dh1); } @@ -2121,9 +2100,6 @@ s390_emit_AGSI(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) static UChar * s390_emit_ASI(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("asi"), SDXB(dh1, dl1, 0, b1), INT((Int)(Char)i2)); - return emit_SIY(p, 0xeb000000006aULL, i2, b1, dl1, dh1); } @@ -2131,9 +2107,6 @@ s390_emit_ASI(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) static UChar * s390_emit_NR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("nr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1400, r1, r2); } @@ -2141,9 +2114,6 @@ s390_emit_NR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_NGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ngr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9800000, r1, r2); } @@ -2151,9 +2121,6 @@ s390_emit_NGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_N(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("n"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x54000000, r1, x2, b2, d2); } @@ -2161,9 +2128,6 @@ s390_emit_N(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_NY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ny"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000054ULL, r1, x2, b2, dl2, dh2); } @@ -2171,9 +2135,6 @@ s390_emit_NY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_NG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ng"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000080ULL, r1, x2, b2, dl2, dh2); } @@ -2181,9 +2142,6 @@ s390_emit_NG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_NIHF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("nihf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00a00000000ULL, r1, i2); } @@ -2191,9 +2149,6 @@ s390_emit_NIHF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_NILF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("nilf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00b00000000ULL, r1, i2); } @@ -2201,9 +2156,6 @@ s390_emit_NILF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_NILL(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("nill"), GPR(r1), UINT(i2)); - return emit_RI(p, 0xa5070000, r1, i2); } @@ -2211,9 +2163,6 @@ s390_emit_NILL(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_TM(UChar *p, UChar i2, UChar b1, UShort d1) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("tm"), UDXB(d1, 0, b1), UINT(i2)); - return emit_SI(p, 0x91000000, i2, b1, d1); } @@ -2221,9 +2170,6 @@ s390_emit_TM(UChar *p, UChar i2, UChar b1, UShort d1) static UChar * s390_emit_TMY(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("tmy"), SDXB(dh1, dl1, 0, b1), UINT(i2)); - return emit_SIY(p, 0xeb0000000051ULL, i2, b1, dl1, dh1); } @@ -2231,9 +2177,6 @@ s390_emit_TMY(UChar *p, UChar i2, UChar b1, UShort dl1, UChar dh1) static UChar * s390_emit_TMLL(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("tmll"), GPR(r1), UINT(i2)); - return emit_RI(p, 0xa7010000, r1, i2); } @@ -2241,9 +2184,6 @@ s390_emit_TMLL(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_BASR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("basr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x0d00, r1, r2); } @@ -2251,9 +2191,6 @@ s390_emit_BASR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_BCR(UChar *p, UChar m1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("bcr", bcr_disasm), MASK(m1), GPR(r2)); - return emit_RR(p, 0x0700, m1, r2); } @@ -2261,9 +2198,6 @@ s390_emit_BCR(UChar *p, UChar m1, UChar r2) static UChar * s390_emit_BRC(UChar *p, UChar m1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("brc", brc_disasm), MASK(m1), PCREL((Int)(Short)i2)); - return emit_RI(p, 0xa7040000, m1, i2); } @@ -2271,9 +2205,6 @@ s390_emit_BRC(UChar *p, UChar m1, UShort i2) static UChar * s390_emit_BRCL(UChar *p, UChar m1, ULong i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("brcl", brcl_disasm), MASK(m1), PCREL(i2)); - return emit_RIL(p, 0xc00400000000ULL, m1, i2); } @@ -2281,9 +2212,6 @@ s390_emit_BRCL(UChar *p, UChar m1, ULong i2) static UChar * s390_emit_CR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1900, r1, r2); } @@ -2291,9 +2219,6 @@ s390_emit_CR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9200000, r1, r2); } @@ -2301,9 +2226,6 @@ s390_emit_CGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_C(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("c"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x59000000, r1, x2, b2, d2); } @@ -2311,9 +2233,6 @@ s390_emit_C(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_CY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000059ULL, r1, x2, b2, dl2, dh2); } @@ -2321,9 +2240,6 @@ s390_emit_CY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000020ULL, r1, x2, b2, dl2, dh2); } @@ -2331,9 +2247,6 @@ s390_emit_CG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cfi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc20d00000000ULL, r1, i2); } @@ -2341,9 +2254,6 @@ s390_emit_CFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_CGFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cgfi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc20c00000000ULL, r1, i2); } @@ -2351,9 +2261,6 @@ s390_emit_CGFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_CS(UChar *p, UChar r1, UChar r3, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cs"), GPR(r1), GPR(r3), UDXB(d2, 0, b2)); - return emit_RS(p, 0xba000000, r1, r3, b2, d2); } @@ -2361,9 +2268,6 @@ s390_emit_CS(UChar *p, UChar r1, UChar r3, UChar b2, UShort d2) static UChar * s390_emit_CSY(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("csy"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb0000000014ULL, r1, r3, b2, dl2, dh2); } @@ -2371,9 +2275,6 @@ s390_emit_CSY(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CSG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("csg"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb0000000030ULL, r1, r3, b2, dl2, dh2); } @@ -2381,9 +2282,6 @@ s390_emit_CSG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CDS(UChar *p, UChar r1, UChar r3, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cds"), GPR(r1), GPR(r3), UDXB(d2, 0, b2)); - return emit_RS(p, 0xbb000000, r1, r3, b2, d2); } @@ -2391,9 +2289,6 @@ s390_emit_CDS(UChar *p, UChar r1, UChar r3, UChar b2, UShort d2) static UChar * s390_emit_CDSY(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cdsy"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb0000000031ULL, r1, r3, b2, dl2, dh2); } @@ -2401,9 +2296,6 @@ s390_emit_CDSY(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CDSG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cdsg"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb000000003eULL, r1, r3, b2, dl2, dh2); } @@ -2411,9 +2303,6 @@ s390_emit_CDSG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CLR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("clr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1500, r1, r2); } @@ -2421,9 +2310,6 @@ s390_emit_CLR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CLGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("clgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9210000, r1, r2); } @@ -2431,9 +2317,6 @@ s390_emit_CLGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CL(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cl"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x55000000, r1, x2, b2, d2); } @@ -2441,9 +2324,6 @@ s390_emit_CL(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_CLY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cly"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000055ULL, r1, x2, b2, dl2, dh2); } @@ -2451,9 +2331,6 @@ s390_emit_CLY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CLG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("clg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000021ULL, r1, x2, b2, dl2, dh2); } @@ -2461,9 +2338,6 @@ s390_emit_CLG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_CLFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("clfi"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc20f00000000ULL, r1, i2); } @@ -2471,9 +2345,6 @@ s390_emit_CLFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_CLGFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("clgfi"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc20e00000000ULL, r1, i2); } @@ -2481,9 +2352,6 @@ s390_emit_CLGFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_DR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1d00, r1, r2); } @@ -2491,9 +2359,6 @@ s390_emit_DR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_D(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("d"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x5d000000, r1, x2, b2, d2); } @@ -2501,9 +2366,6 @@ s390_emit_D(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_DLR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dlr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9970000, r1, r2); } @@ -2511,9 +2373,6 @@ s390_emit_DLR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_DLGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dlgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9870000, r1, r2); } @@ -2521,9 +2380,6 @@ s390_emit_DLGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_DL(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dl"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000097ULL, r1, x2, b2, dl2, dh2); } @@ -2531,9 +2387,6 @@ s390_emit_DL(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_DLG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dlg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000087ULL, r1, x2, b2, dl2, dh2); } @@ -2541,9 +2394,6 @@ s390_emit_DLG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_DSGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dsgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb90d0000, r1, r2); } @@ -2551,9 +2401,6 @@ s390_emit_DSGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_DSG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dsg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000000dULL, r1, x2, b2, dl2, dh2); } @@ -2561,9 +2408,6 @@ s390_emit_DSG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_XR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1700, r1, r2); } @@ -2571,9 +2415,6 @@ s390_emit_XR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_XGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9820000, r1, r2); } @@ -2581,9 +2422,6 @@ s390_emit_XGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_X(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("x"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x57000000, r1, x2, b2, d2); } @@ -2591,9 +2429,6 @@ s390_emit_X(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_XY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000057ULL, r1, x2, b2, dl2, dh2); } @@ -2601,9 +2436,6 @@ s390_emit_XY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_XG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000082ULL, r1, x2, b2, dl2, dh2); } @@ -2611,9 +2443,6 @@ s390_emit_XG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_XIHF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xihf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00600000000ULL, r1, i2); } @@ -2621,9 +2450,6 @@ s390_emit_XIHF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_XILF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xilf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00700000000ULL, r1, i2); } @@ -2631,9 +2457,6 @@ s390_emit_XILF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_XC(UChar *p, UInt l, UChar b1, UShort d1, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("xc"), UDLB(d1, l, b1), UDXB(d2, 0, b2)); - return emit_SSa(p, 0xd70000000000ULL, l, b1, d1, b2, d2); } @@ -2641,9 +2464,6 @@ s390_emit_XC(UChar *p, UInt l, UChar b1, UShort d1, UChar b2, UShort d2) static UChar * s390_emit_FLOGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("flogr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9830000, r1, r2); } @@ -2651,9 +2471,6 @@ s390_emit_FLOGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_IC(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ic"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x43000000, r1, x2, b2, d2); } @@ -2661,9 +2478,6 @@ s390_emit_IC(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_ICY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("icy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000073ULL, r1, x2, b2, dl2, dh2); } @@ -2671,9 +2485,6 @@ s390_emit_ICY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_IIHF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("iihf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00800000000ULL, r1, i2); } @@ -2681,9 +2492,6 @@ s390_emit_IIHF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_IILF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("iilf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00900000000ULL, r1, i2); } @@ -2691,9 +2499,6 @@ s390_emit_IILF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_IPM(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ipm"), GPR(r1)); - return emit_RRE(p, 0xb2220000, r1, r2); } @@ -2701,9 +2506,6 @@ s390_emit_IPM(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1800, r1, r2); } @@ -2711,9 +2513,6 @@ s390_emit_LR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9040000, r1, r2); } @@ -2721,9 +2520,6 @@ s390_emit_LGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LGFR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgfr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9140000, r1, r2); } @@ -2731,9 +2527,6 @@ s390_emit_LGFR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_L(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("l"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x58000000, r1, x2, b2, d2); } @@ -2741,9 +2534,6 @@ s390_emit_L(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_LY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ly"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000058ULL, r1, x2, b2, dl2, dh2); } @@ -2751,9 +2541,6 @@ s390_emit_LY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000004ULL, r1, x2, b2, dl2, dh2); } @@ -2761,9 +2548,6 @@ s390_emit_LG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LGF(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgf"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000014ULL, r1, x2, b2, dl2, dh2); } @@ -2771,9 +2555,6 @@ s390_emit_LGF(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LGFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgfi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc00100000000ULL, r1, i2); } @@ -2781,9 +2562,6 @@ s390_emit_LGFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_LTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ltr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1200, r1, r2); } @@ -2791,9 +2569,6 @@ s390_emit_LTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LTGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ltgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9020000, r1, r2); } @@ -2801,9 +2576,6 @@ s390_emit_LTGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LT(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lt"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000012ULL, r1, x2, b2, dl2, dh2); } @@ -2811,9 +2583,6 @@ s390_emit_LT(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LTG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ltg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000002ULL, r1, x2, b2, dl2, dh2); } @@ -2821,9 +2590,6 @@ s390_emit_LTG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lbr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9260000, r1, r2); } @@ -2831,9 +2597,6 @@ s390_emit_LBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LGBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgbr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9060000, r1, r2); } @@ -2841,9 +2604,6 @@ s390_emit_LGBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LB(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lb"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000076ULL, r1, x2, b2, dl2, dh2); } @@ -2851,9 +2611,6 @@ s390_emit_LB(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LGB(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgb"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000077ULL, r1, x2, b2, dl2, dh2); } @@ -2861,9 +2618,6 @@ s390_emit_LGB(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LCR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lcr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1300, r1, r2); } @@ -2871,9 +2625,6 @@ s390_emit_LCR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LCGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lcgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9030000, r1, r2); } @@ -2881,9 +2632,6 @@ s390_emit_LCGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LHR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lhr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9270000, r1, r2); } @@ -2891,9 +2639,6 @@ s390_emit_LHR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LGHR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lghr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9070000, r1, r2); } @@ -2901,9 +2646,6 @@ s390_emit_LGHR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lh"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x48000000, r1, x2, b2, d2); } @@ -2911,9 +2653,6 @@ s390_emit_LH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_LHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lhy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000078ULL, r1, x2, b2, dl2, dh2); } @@ -2921,9 +2660,6 @@ s390_emit_LHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LGH(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgh"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000015ULL, r1, x2, b2, dl2, dh2); } @@ -2931,9 +2667,6 @@ s390_emit_LGH(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LHI(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lhi"), GPR(r1), INT((Int)(Short)i2)); - return emit_RI(p, 0xa7080000, r1, i2); } @@ -2941,9 +2674,6 @@ s390_emit_LHI(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_LGHI(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lghi"), GPR(r1), INT((Int)(Short)i2)); - return emit_RI(p, 0xa7090000, r1, i2); } @@ -2951,9 +2681,6 @@ s390_emit_LGHI(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_LLGFR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llgfr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9160000, r1, r2); } @@ -2961,9 +2688,6 @@ s390_emit_LLGFR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LLGF(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llgf"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000016ULL, r1, x2, b2, dl2, dh2); } @@ -2971,9 +2695,6 @@ s390_emit_LLGF(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LLCR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llcr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9940000, r1, r2); } @@ -2981,9 +2702,6 @@ s390_emit_LLCR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LLGCR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llgcr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9840000, r1, r2); } @@ -2991,9 +2709,6 @@ s390_emit_LLGCR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LLC(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llc"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000094ULL, r1, x2, b2, dl2, dh2); } @@ -3001,9 +2716,6 @@ s390_emit_LLC(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LLGC(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llgc"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000090ULL, r1, x2, b2, dl2, dh2); } @@ -3011,9 +2723,6 @@ s390_emit_LLGC(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LLHR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llhr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9950000, r1, r2); } @@ -3021,9 +2730,6 @@ s390_emit_LLHR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LLGHR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llghr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9850000, r1, r2); } @@ -3031,9 +2737,6 @@ s390_emit_LLGHR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LLH(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llh"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000095ULL, r1, x2, b2, dl2, dh2); } @@ -3041,9 +2744,6 @@ s390_emit_LLH(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LLGH(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llgh"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000091ULL, r1, x2, b2, dl2, dh2); } @@ -3051,9 +2751,6 @@ s390_emit_LLGH(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LLILF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llilf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00f00000000ULL, r1, i2); } @@ -3061,9 +2758,6 @@ s390_emit_LLILF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_LLILL(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("llill"), GPR(r1), UINT(i2)); - return emit_RI(p, 0xa50f0000, r1, i2); } @@ -3071,9 +2765,6 @@ s390_emit_LLILL(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_MR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1c00, r1, r2); } @@ -3081,9 +2772,6 @@ s390_emit_MR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_M(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("m"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x5c000000, r1, x2, b2, d2); } @@ -3091,9 +2779,6 @@ s390_emit_M(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_MFY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mfy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000005cULL, r1, x2, b2, dl2, dh2); } @@ -3101,9 +2786,6 @@ s390_emit_MFY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000084ULL, r1, x2, b2, dl2, dh2); } @@ -3111,9 +2793,6 @@ s390_emit_MG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MGRK(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mgrk"), GPR(r1), GPR(r2), GPR(r3)); - return emit_RRF3(p, 0xb9ec0000, r3, r1, r2); } @@ -3121,9 +2800,6 @@ s390_emit_MGRK(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_MH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mh"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x4c000000, r1, x2, b2, d2); } @@ -3131,9 +2807,6 @@ s390_emit_MH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_MHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mhy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000007cULL, r1, x2, b2, dl2, dh2); } @@ -3141,9 +2814,6 @@ s390_emit_MHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MHI(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mhi"), GPR(r1), INT((Int)(Short)i2)); - return emit_RI(p, 0xa70c0000, r1, i2); } @@ -3151,9 +2821,6 @@ s390_emit_MHI(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_MLR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mlr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9960000, r1, r2); } @@ -3161,9 +2828,6 @@ s390_emit_MLR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_MLGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mlgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9860000, r1, r2); } @@ -3171,9 +2835,6 @@ s390_emit_MLGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_ML(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ml"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000096ULL, r1, x2, b2, dl2, dh2); } @@ -3181,9 +2842,6 @@ s390_emit_ML(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MLG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mlg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000086ULL, r1, x2, b2, dl2, dh2); } @@ -3191,9 +2849,6 @@ s390_emit_MLG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MSR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb2520000, r1, r2); } @@ -3201,9 +2856,6 @@ s390_emit_MSR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_MSGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb90c0000, r1, r2); } @@ -3211,9 +2863,6 @@ s390_emit_MSGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_MS(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ms"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x71000000, r1, x2, b2, d2); } @@ -3221,9 +2870,6 @@ s390_emit_MS(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_MSY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000051ULL, r1, x2, b2, dl2, dh2); } @@ -3231,9 +2877,6 @@ s390_emit_MSY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MSG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000000cULL, r1, x2, b2, dl2, dh2); } @@ -3241,9 +2884,6 @@ s390_emit_MSG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_MSFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msfi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc20100000000ULL, r1, i2); } @@ -3251,9 +2891,6 @@ s390_emit_MSFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_MSGFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msgfi"), GPR(r1), INT(i2)); - return emit_RIL(p, 0xc20000000000ULL, r1, i2); } @@ -3261,9 +2898,6 @@ s390_emit_MSGFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_MVC(UChar *p, UInt l, UChar b1, UShort d1, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mvc"), UDLB(d1, l, b1), UDXB(d2, 0, b2)); - return emit_SSa(p, 0xd20000000000ULL, l, b1, d1, b2, d2); } @@ -3271,9 +2905,6 @@ s390_emit_MVC(UChar *p, UInt l, UChar b1, UShort d1, UChar b2, UShort d2) static UChar * s390_emit_MVI(UChar *p, UChar i2, UChar b1, UShort d1) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mvi"), UDXB(d1, 0, b1), UINT(i2)); - return emit_SI(p, 0x92000000, i2, b1, d1); } @@ -3281,9 +2912,6 @@ s390_emit_MVI(UChar *p, UChar i2, UChar b1, UShort d1) static UChar * s390_emit_MVHHI(UChar *p, UChar b1, UShort d1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mvhhi"), UDXB(d1, 0, b1), INT((Int)(Short)i2)); - return emit_SIL(p, 0xe54400000000ULL, b1, d1, i2); } @@ -3291,9 +2919,6 @@ s390_emit_MVHHI(UChar *p, UChar b1, UShort d1, UShort i2) static UChar * s390_emit_MVHI(UChar *p, UChar b1, UShort d1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mvhi"), UDXB(d1, 0, b1), INT((Int)(Short)i2)); - return emit_SIL(p, 0xe54c00000000ULL, b1, d1, i2); } @@ -3301,9 +2926,6 @@ s390_emit_MVHI(UChar *p, UChar b1, UShort d1, UShort i2) static UChar * s390_emit_MVGHI(UChar *p, UChar b1, UShort d1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mvghi"), UDXB(d1, 0, b1), INT((Int)(Short)i2)); - return emit_SIL(p, 0xe54800000000ULL, b1, d1, i2); } @@ -3311,9 +2933,6 @@ s390_emit_MVGHI(UChar *p, UChar b1, UShort d1, UShort i2) static UChar * s390_emit_OR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("or"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1600, r1, r2); } @@ -3321,9 +2940,6 @@ s390_emit_OR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_OGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ogr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9810000, r1, r2); } @@ -3331,9 +2947,6 @@ s390_emit_OGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_O(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("o"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x56000000, r1, x2, b2, d2); } @@ -3341,9 +2954,6 @@ s390_emit_O(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_OY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("oy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000056ULL, r1, x2, b2, dl2, dh2); } @@ -3351,9 +2961,6 @@ s390_emit_OY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_OG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("og"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000081ULL, r1, x2, b2, dl2, dh2); } @@ -3361,9 +2968,6 @@ s390_emit_OG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_OIHF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("oihf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00c00000000ULL, r1, i2); } @@ -3371,9 +2975,6 @@ s390_emit_OIHF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_OILF(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("oilf"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc00d00000000ULL, r1, i2); } @@ -3381,9 +2982,6 @@ s390_emit_OILF(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_OILL(UChar *p, UChar r1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("oill"), GPR(r1), UINT(i2)); - return emit_RI(p, 0xa50b0000, r1, i2); } @@ -3391,9 +2989,6 @@ s390_emit_OILL(UChar *p, UChar r1, UShort i2) static UChar * s390_emit_SLL(UChar *p, UChar r1, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sll"), GPR(r1), UDXB(d2, 0, b2)); - return emit_RS(p, 0x89000000, r1, 0, b2, d2); } @@ -3401,9 +2996,6 @@ s390_emit_SLL(UChar *p, UChar r1, UChar b2, UShort d2) static UChar * s390_emit_SLLG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sllg"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb000000000dULL, r1, r3, b2, dl2, dh2); } @@ -3411,9 +3003,6 @@ s390_emit_SLLG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_SRA(UChar *p, UChar r1, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sra"), GPR(r1), UDXB(d2, 0, b2)); - return emit_RS(p, 0x8a000000, r1, 0, b2, d2); } @@ -3421,9 +3010,6 @@ s390_emit_SRA(UChar *p, UChar r1, UChar b2, UShort d2) static UChar * s390_emit_SRAG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("srag"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb000000000aULL, r1, r3, b2, dl2, dh2); } @@ -3431,9 +3017,6 @@ s390_emit_SRAG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_SRL(UChar *p, UChar r1, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("srl"), GPR(r1), UDXB(d2, 0, b2)); - return emit_RS(p, 0x88000000, r1, 0, b2, d2); } @@ -3441,9 +3024,6 @@ s390_emit_SRL(UChar *p, UChar r1, UChar b2, UShort d2) static UChar * s390_emit_SRLG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("srlg"), GPR(r1), GPR(r3), SDXB(dh2, dl2, 0, b2)); - return emit_RSY(p, 0xeb000000000cULL, r1, r3, b2, dl2, dh2); } @@ -3451,9 +3031,6 @@ s390_emit_SRLG(UChar *p, UChar r1, UChar r3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_ST(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("st"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x50000000, r1, x2, b2, d2); } @@ -3461,9 +3038,6 @@ s390_emit_ST(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_STY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sty"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000050ULL, r1, x2, b2, dl2, dh2); } @@ -3471,9 +3045,6 @@ s390_emit_STY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_STG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("stg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000024ULL, r1, x2, b2, dl2, dh2); } @@ -3481,9 +3052,6 @@ s390_emit_STG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_STC(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("stc"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x42000000, r1, x2, b2, d2); } @@ -3491,9 +3059,6 @@ s390_emit_STC(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_STCY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("stcy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000072ULL, r1, x2, b2, dl2, dh2); } @@ -3501,9 +3066,6 @@ s390_emit_STCY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_STH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sth"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x40000000, r1, x2, b2, d2); } @@ -3511,9 +3073,6 @@ s390_emit_STH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_STHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sthy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000070ULL, r1, x2, b2, dl2, dh2); } @@ -3521,9 +3080,6 @@ s390_emit_STHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_SR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sr"), GPR(r1), GPR(r2)); - return emit_RR(p, 0x1b00, r1, r2); } @@ -3531,9 +3087,6 @@ s390_emit_SR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sgr"), GPR(r1), GPR(r2)); - return emit_RRE(p, 0xb9090000, r1, r2); } @@ -3541,9 +3094,6 @@ s390_emit_SGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_S(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("s"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x5b000000, r1, x2, b2, d2); } @@ -3551,9 +3101,6 @@ s390_emit_S(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_SY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000005bULL, r1, x2, b2, dl2, dh2); } @@ -3561,9 +3108,6 @@ s390_emit_SY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_SG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sg"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe30000000009ULL, r1, x2, b2, dl2, dh2); } @@ -3571,9 +3115,6 @@ s390_emit_SG(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_SH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sh"), GPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x4b000000, r1, x2, b2, d2); } @@ -3581,9 +3122,6 @@ s390_emit_SH(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_SHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("shy"), GPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xe3000000007bULL, r1, x2, b2, dl2, dh2); } @@ -3591,9 +3129,6 @@ s390_emit_SHY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_SLFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("slfi"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc20500000000ULL, r1, i2); } @@ -3601,9 +3136,6 @@ s390_emit_SLFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_SLGFI(UChar *p, UChar r1, UInt i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("slgfi"), GPR(r1), UINT(i2)); - return emit_RIL(p, 0xc20400000000ULL, r1, i2); } @@ -3611,9 +3143,6 @@ s390_emit_SLGFI(UChar *p, UChar r1, UInt i2) static UChar * s390_emit_LDR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ldr"), FPR(r1), FPR(r2)); - return emit_RR(p, 0x2800, r1, r2); } @@ -3621,9 +3150,6 @@ s390_emit_LDR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LE(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("le"), FPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x78000000, r1, x2, b2, d2); } @@ -3631,9 +3157,6 @@ s390_emit_LE(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_LD(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ld"), FPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x68000000, r1, x2, b2, d2); } @@ -3641,9 +3164,6 @@ s390_emit_LD(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_LEY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ley"), FPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xed0000000064ULL, r1, x2, b2, dl2, dh2); } @@ -3651,9 +3171,6 @@ s390_emit_LEY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LDY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ldy"), FPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xed0000000065ULL, r1, x2, b2, dl2, dh2); } @@ -3661,9 +3178,6 @@ s390_emit_LDY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LDGR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ldgr"), FPR(r1), GPR(r2)); - return emit_RRE(p, 0xb3c10000, r1, r2); } @@ -3671,9 +3185,6 @@ s390_emit_LDGR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LGDR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lgdr"), GPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3cd0000, r1, r2); } @@ -3681,9 +3192,6 @@ s390_emit_LGDR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LZER(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lzer"), FPR(r1)); - return emit_RRE(p, 0xb3740000, r1, r2); } @@ -3691,9 +3199,6 @@ s390_emit_LZER(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LZDR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lzdr"), FPR(r1)); - return emit_RRE(p, 0xb3750000, r1, r2); } @@ -3701,9 +3206,6 @@ s390_emit_LZDR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SFPC(UChar *p, UChar r1) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sfpc"), GPR(r1)); - return emit_RRE(p, 0xb3840000, r1, 0); } @@ -3711,9 +3213,6 @@ s390_emit_SFPC(UChar *p, UChar r1) static UChar * s390_emit_STE(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ste"), FPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x70000000, r1, x2, b2, d2); } @@ -3721,9 +3220,6 @@ s390_emit_STE(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_STD(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("std"), FPR(r1), UDXB(d2, x2, b2)); - return emit_RX(p, 0x60000000, r1, x2, b2, d2); } @@ -3731,9 +3227,6 @@ s390_emit_STD(UChar *p, UChar r1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_STEY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("stey"), FPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xed0000000066ULL, r1, x2, b2, dl2, dh2); } @@ -3741,9 +3234,6 @@ s390_emit_STEY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_STDY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("stdy"), FPR(r1), SDXB(dh2, dl2, x2, b2)); - return emit_RXY(p, 0xed0000000067ULL, r1, x2, b2, dl2, dh2); } @@ -3751,9 +3241,6 @@ s390_emit_STDY(UChar *p, UChar r1, UChar x2, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_AEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("aebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb30a0000, r1, r2); } @@ -3761,9 +3248,6 @@ s390_emit_AEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_ADBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("adbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb31a0000, r1, r2); } @@ -3771,9 +3255,6 @@ s390_emit_ADBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_AXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("axbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb34a0000, r1, r2); } @@ -3781,9 +3262,6 @@ s390_emit_AXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3090000, r1, r2); } @@ -3791,9 +3269,6 @@ s390_emit_CEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3190000, r1, r2); } @@ -3801,9 +3276,6 @@ s390_emit_CDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3490000, r1, r2); } @@ -3813,9 +3285,6 @@ s390_emit_CEFBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cefbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3940000, m3, m4, r1, r2); } @@ -3825,9 +3294,6 @@ s390_emit_CDFBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdfbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3950000, m3, m4, r1, r2); } @@ -3837,9 +3303,6 @@ s390_emit_CXFBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxfbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3960000, m3, m4, r1, r2); } @@ -3849,9 +3312,6 @@ s390_emit_CEGBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cegbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3a40000, m3, m4, r1, r2); } @@ -3861,9 +3321,6 @@ s390_emit_CDGBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdgbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3a50000, m3, m4, r1, r2); } @@ -3873,9 +3330,6 @@ s390_emit_CXGBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxgbra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3a60000, m3, m4, r1, r2); } @@ -3885,9 +3339,6 @@ s390_emit_CELFBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("celfbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3900000, m3, m4, r1, r2); } @@ -3897,9 +3348,6 @@ s390_emit_CDLFBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdlfbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3910000, m3, m4, r1, r2); } @@ -3909,9 +3357,6 @@ s390_emit_CXLFBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxlfbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3920000, m3, m4, r1, r2); } @@ -3921,9 +3366,6 @@ s390_emit_CELGBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("celgbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3a00000, m3, m4, r1, r2); } @@ -3933,9 +3375,6 @@ s390_emit_CDLGBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdlgbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3a10000, m3, m4, r1, r2); } @@ -3945,9 +3384,6 @@ s390_emit_CXLGBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxlgbr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3a20000, m3, m4, r1, r2); } @@ -3957,9 +3393,6 @@ s390_emit_CLFEBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clfebr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb39c0000, m3, m4, r1, r2); } @@ -3969,9 +3402,6 @@ s390_emit_CLFDBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clfdbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb39d0000, m3, m4, r1, r2); } @@ -3981,9 +3411,6 @@ s390_emit_CLFXBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clfxbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb39e0000, m3, m4, r1, r2); } @@ -3993,9 +3420,6 @@ s390_emit_CLGEBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clgebr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3ac0000, m3, m4, r1, r2); } @@ -4005,9 +3429,6 @@ s390_emit_CLGDBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clgdbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3ad0000, m3, m4, r1, r2); } @@ -4017,9 +3438,6 @@ s390_emit_CLGXBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clgxbr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3ae0000, m3, m4, r1, r2); } @@ -4027,9 +3445,6 @@ s390_emit_CLGXBR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CFEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cfebra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF3(p, 0xb3980000, m3, r1, r2); } @@ -4037,9 +3452,6 @@ s390_emit_CFEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CFDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cfdbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF3(p, 0xb3990000, m3, r1, r2); } @@ -4047,9 +3459,6 @@ s390_emit_CFDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CFXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cfxbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF3(p, 0xb39a0000, m3, r1, r2); } @@ -4057,9 +3466,6 @@ s390_emit_CFXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CGEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cgebra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF3(p, 0xb3a80000, m3, r1, r2); } @@ -4067,9 +3473,6 @@ s390_emit_CGEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CGDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cgdbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF3(p, 0xb3a90000, m3, r1, r2); } @@ -4077,9 +3480,6 @@ s390_emit_CGDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CGXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cgxbra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF3(p, 0xb3aa0000, m3, r1, r2); } @@ -4087,9 +3487,6 @@ s390_emit_CGXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_DEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("debr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb30d0000, r1, r2); } @@ -4097,9 +3494,6 @@ s390_emit_DEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_DDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ddbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb31d0000, r1, r2); } @@ -4107,9 +3501,6 @@ s390_emit_DDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_DXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("dxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb34d0000, r1, r2); } @@ -4117,9 +3508,6 @@ s390_emit_DXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LCEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lcebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3030000, r1, r2); } @@ -4127,9 +3515,6 @@ s390_emit_LCEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LCDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lcdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3130000, r1, r2); } @@ -4137,9 +3522,6 @@ s390_emit_LCDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LCXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lcxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3430000, r1, r2); } @@ -4147,9 +3529,6 @@ s390_emit_LCXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LDEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ldebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3040000, r1, r2); } @@ -4157,9 +3536,6 @@ s390_emit_LDEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LXDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lxdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3050000, r1, r2); } @@ -4167,9 +3543,6 @@ s390_emit_LXDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LXEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lxebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3060000, r1, r2); } @@ -4177,9 +3550,6 @@ s390_emit_LXEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LNEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lnebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3010000, r1, r2); } @@ -4187,9 +3557,6 @@ s390_emit_LNEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LNDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lndbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3110000, r1, r2); } @@ -4197,9 +3564,6 @@ s390_emit_LNDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LNXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lnxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3410000, r1, r2); } @@ -4207,9 +3571,6 @@ s390_emit_LNXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LPEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lpebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3000000, r1, r2); } @@ -4217,9 +3578,6 @@ s390_emit_LPEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LPDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lpdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3100000, r1, r2); } @@ -4227,9 +3585,6 @@ s390_emit_LPDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_LPXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lpxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3400000, r1, r2); } @@ -4239,9 +3594,6 @@ s390_emit_LEDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("ledbra", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3440000, m3, m4, r1, r2); } @@ -4251,9 +3603,6 @@ s390_emit_LDXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("ldxbra", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3450000, m3, m4, r1, r2); } @@ -4263,9 +3612,6 @@ s390_emit_LEXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("lexbra", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3460000, m3, m4, r1, r2); } @@ -4273,9 +3619,6 @@ s390_emit_LEXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_FIEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("fiebra", fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3570000, m3, m4, r1, r2); } @@ -4283,9 +3626,6 @@ s390_emit_FIEBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_FIDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("fidbra", fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb35f0000, m3, m4, r1, r2); } @@ -4293,9 +3633,6 @@ s390_emit_FIDBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_FIXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("fixbra", fp_convt_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3470000, m3, m4, r1, r2); } @@ -4303,9 +3640,6 @@ s390_emit_FIXBRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_MEEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("meebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3170000, r1, r2); } @@ -4313,9 +3647,6 @@ s390_emit_MEEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_MDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb31c0000, r1, r2); } @@ -4323,9 +3654,6 @@ s390_emit_MDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_MXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("mxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb34c0000, r1, r2); } @@ -4333,9 +3661,6 @@ s390_emit_MXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_MAEBR(UChar *p, UChar r1, UChar r3, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("maebr"), FPR(r1), FPR(r3), FPR(r2)); - return emit_RRF(p, 0xb30e0000, r1, r3, r2); } @@ -4343,9 +3668,6 @@ s390_emit_MAEBR(UChar *p, UChar r1, UChar r3, UChar r2) static UChar * s390_emit_MADBR(UChar *p, UChar r1, UChar r3, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("madbr"), FPR(r1), FPR(r3), FPR(r2)); - return emit_RRF(p, 0xb31e0000, r1, r3, r2); } @@ -4353,9 +3675,6 @@ s390_emit_MADBR(UChar *p, UChar r1, UChar r3, UChar r2) static UChar * s390_emit_MSEBR(UChar *p, UChar r1, UChar r3, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msebr"), FPR(r1), FPR(r3), FPR(r2)); - return emit_RRF(p, 0xb30f0000, r1, r3, r2); } @@ -4363,9 +3682,6 @@ s390_emit_MSEBR(UChar *p, UChar r1, UChar r3, UChar r2) static UChar * s390_emit_MSDBR(UChar *p, UChar r1, UChar r3, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("msdbr"), FPR(r1), FPR(r3), FPR(r2)); - return emit_RRF(p, 0xb31f0000, r1, r3, r2); } @@ -4373,9 +3689,6 @@ s390_emit_MSDBR(UChar *p, UChar r1, UChar r3, UChar r2) static UChar * s390_emit_SQEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sqebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3140000, r1, r2); } @@ -4383,9 +3696,6 @@ s390_emit_SQEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SQDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sqdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3150000, r1, r2); } @@ -4393,9 +3703,6 @@ s390_emit_SQDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SQXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sqxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3160000, r1, r2); } @@ -4403,9 +3710,6 @@ s390_emit_SQXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SEBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sebr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb30b0000, r1, r2); } @@ -4413,9 +3717,6 @@ s390_emit_SEBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SDBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sdbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb31b0000, r1, r2); } @@ -4423,9 +3724,6 @@ s390_emit_SDBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_SXBR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sxbr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb34b0000, r1, r2); } @@ -4433,9 +3731,6 @@ s390_emit_SXBR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_ADTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("adtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3d20000, r3, m4, r1, r2); } @@ -4443,9 +3738,6 @@ s390_emit_ADTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_AXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("axtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3da0000, r3, m4, r1, r2); } @@ -4453,9 +3745,6 @@ s390_emit_AXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CDTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cdtr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3e40000, r1, r2); } @@ -4463,9 +3752,6 @@ s390_emit_CDTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CXTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cxtr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3ec0000, r1, r2); } @@ -4475,9 +3761,6 @@ s390_emit_CDGTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdgtra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3f10000, m3, m4, r1, r2); } @@ -4490,9 +3773,6 @@ s390_emit_CXGTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) IRop (Iop_I64StoD128) does not take rounding mode. */ vassert(m3 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxgtra", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3f90000, m3, m4, r1, r2); } @@ -4502,9 +3782,6 @@ s390_emit_CDFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9510000, m3, m4, r1, r2); } @@ -4514,9 +3791,6 @@ s390_emit_CXFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9590000, m3, m4, r1, r2); } @@ -4526,9 +3800,6 @@ s390_emit_CDLFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdlftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9530000, m3, m4, r1, r2); } @@ -4538,9 +3809,6 @@ s390_emit_CXLFTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxlftr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb95b0000, m3, m4, r1, r2); } @@ -4550,9 +3818,6 @@ s390_emit_CDLGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cdlgtr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9520000, m3, m4, r1, r2); } @@ -4562,9 +3827,6 @@ s390_emit_CXLGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cxlgtr", fp_convf_disasm), FPR(r1), MASK(m3), GPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb95a0000, m3, m4, r1, r2); } @@ -4572,9 +3834,6 @@ s390_emit_CXLGTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_CEDTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cedtr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3f40000, r1, r2); } @@ -4582,9 +3841,6 @@ s390_emit_CEDTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_CEXTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("cextr"), FPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3fc0000, r1, r2); } @@ -4594,9 +3850,6 @@ s390_emit_CFDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cfdtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9410000, m3, m4, r1, r2); } @@ -4606,9 +3859,6 @@ s390_emit_CFXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cfxtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9490000, m3, m4, r1, r2); } @@ -4618,9 +3868,6 @@ s390_emit_CGDTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cgdtra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3e10000, m3, m4, r1, r2); } @@ -4630,9 +3877,6 @@ s390_emit_CGXTRA(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("cgxtra", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3e90000, m3, m4, r1, r2); } @@ -4642,9 +3886,6 @@ s390_emit_CLFDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clfdtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9430000, m3, m4, r1, r2); } @@ -4654,9 +3895,6 @@ s390_emit_CLFXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clfxtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb94b0000, m3, m4, r1, r2); } @@ -4666,9 +3904,6 @@ s390_emit_CLGDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clgdtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb9420000, m3, m4, r1, r2); } @@ -4678,9 +3913,6 @@ s390_emit_CLGXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("clgxtr", fp_convt_disasm), GPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb94a0000, m3, m4, r1, r2); } @@ -4688,9 +3920,6 @@ s390_emit_CLGXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_DDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("ddtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3d10000, r3, m4, r1, r2); } @@ -4698,9 +3927,6 @@ s390_emit_DDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_DXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("dxtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3d90000, r3, m4, r1, r2); } @@ -4708,9 +3934,6 @@ s390_emit_DXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_EEDTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("eedtr"), GPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3e50000, r1, r2); } @@ -4718,9 +3941,6 @@ s390_emit_EEDTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_EEXTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("eextr"), GPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3ed0000, r1, r2); } @@ -4728,9 +3948,6 @@ s390_emit_EEXTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_ESDTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("esdtr"), GPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3e70000, r1, r2); } @@ -4738,9 +3955,6 @@ s390_emit_ESDTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_ESXTR(UChar *p, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("esxtr"), GPR(r1), FPR(r2)); - return emit_RRE(p, 0xb3ef0000, r1, r2); } @@ -4748,9 +3962,6 @@ s390_emit_ESXTR(UChar *p, UChar r1, UChar r2) static UChar * s390_emit_IEDTR(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("iedtr"), FPR(r1), FPR(r3), GPR(r2)); - return emit_RRF(p, 0xb3f60000, r3, r1, r2); } @@ -4758,9 +3969,6 @@ s390_emit_IEDTR(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_IEXTR(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("iextr"), FPR(r1), FPR(r3), GPR(r2)); - return emit_RRF(p, 0xb3fe0000, r3, r1, r2); } @@ -4768,9 +3976,6 @@ s390_emit_IEXTR(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_LDETR(UChar *p, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("ldetr"), FPR(r1), FPR(r2), UINT(m4)); - return emit_RRF5(p, 0xb3d40000, m4, r1, r2); } @@ -4778,9 +3983,6 @@ s390_emit_LDETR(UChar *p, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_LXDTR(UChar *p, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("lxdtr"), FPR(r1), FPR(r2), UINT(m4)); - return emit_RRF5(p, 0xb3dc0000, m4, r1, r2); } @@ -4790,9 +3992,6 @@ s390_emit_LEDTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("ledtr", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3d50000, m3, m4, r1, r2); } @@ -4802,9 +4001,6 @@ s390_emit_LDXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) { vassert(m4 == 0); - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("ldxtr", fp_convf_disasm), FPR(r1), MASK(m3), FPR(r2), MASK(m4)); - return emit_RRF2(p, 0xb3dd0000, m3, m4, r1, r2); } @@ -4812,9 +4008,6 @@ s390_emit_LDXTR(UChar *p, UChar m3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_MDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("mdtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3d00000, r3, m4, r1, r2); } @@ -4822,9 +4015,6 @@ s390_emit_MDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_MXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("mxtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3d80000, r3, m4, r1, r2); } @@ -4841,10 +4031,6 @@ emit_E(UChar *p, UInt op) static UChar * s390_emit_PFPO(UChar *p) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) { - S390_DISASM(MNM("pfpo")); - } - return emit_E(p, 0x010a); } @@ -4852,9 +4038,6 @@ s390_emit_PFPO(UChar *p) static UChar * s390_emit_QADTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("qadtr"), FPR(r1), FPR(r3), FPR(r2), UINT(m4)); - return emit_RRF4(p, 0xb3f50000, r3, m4, r1, r2); } @@ -4862,9 +4045,6 @@ s390_emit_QADTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_QAXTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("qaxtr"), FPR(r1), FPR(r3), FPR(r2), UINT(m4)); - return emit_RRF4(p, 0xb3fd0000, r3, m4, r1, r2); } @@ -4872,9 +4052,6 @@ s390_emit_QAXTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_RRDTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("rrdtr"), FPR(r1), FPR(r3), GPR(r2), UINT(m4)); - return emit_RRF4(p, 0xb3f70000, r3, m4, r1, r2); } @@ -4882,9 +4059,6 @@ s390_emit_RRDTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_RRXTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("rrxtr"), FPR(r1), FPR(r3), GPR(r2), UINT(m4)); - return emit_RRF4(p, 0xb3ff0000, r3, m4, r1, r2); } @@ -4892,9 +4066,6 @@ s390_emit_RRXTR(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_SDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("sdtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3d30000, r3, m4, r1, r2); } @@ -4902,9 +4073,6 @@ s390_emit_SDTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_SXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("sxtra", adtra_like_disasm), FPR(r1), FPR(r2), FPR(r3), MASK(m4)); - return emit_RRF4(p, 0xb3db0000, r3, m4, r1, r2); } @@ -4912,9 +4080,6 @@ s390_emit_SXTRA(UChar *p, UChar r3, UChar m4, UChar r1, UChar r2) static UChar * s390_emit_SLDT(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("sldt"), FPR(r1), FPR(r3), UDXB(0, 0, r2)); - return emit_RXF(p, 0xED0000000040ULL, r3, 0, r2, 0, r1); } @@ -4922,9 +4087,6 @@ s390_emit_SLDT(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_SLXT(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("slxt"), FPR(r1), FPR(r3), UDXB(0, 0, r2)); - return emit_RXF(p, 0xED0000000048ULL, r3, 0, r2, 0, r1); } @@ -4932,9 +4094,6 @@ s390_emit_SLXT(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_SRDT(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("srdt"), FPR(r1), FPR(r3), UDXB(0, 0, r2)); - return emit_RXF(p, 0xED0000000041ULL, r3, 0, r2, 0, r1); } @@ -4942,9 +4101,6 @@ s390_emit_SRDT(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_SRXT(UChar *p, UChar r3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("srxt"), FPR(r1), FPR(r3), UDXB(0, 0, r2)); - return emit_RXF(p, 0xED0000000049ULL, r3, 0, r2, 0, r1); } @@ -4952,9 +4108,6 @@ s390_emit_SRXT(UChar *p, UChar r3, UChar r1, UChar r2) static UChar * s390_emit_LOCGR(UChar *p, UChar m3, UChar r1, UChar r2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("locgr", cls_disasm), GPR(r1), GPR(r2), MASK(m3)); - return emit_RRF3(p, 0xb9e20000, m3, r1, r2); } @@ -4962,9 +4115,6 @@ s390_emit_LOCGR(UChar *p, UChar m3, UChar r1, UChar r2) static UChar * s390_emit_LOC(UChar *p, UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("loc", cls_disasm), GPR(r1), SDXB(dh2, dl2, 0, b2), MASK(m3)); - return emit_RSY(p, 0xeb00000000f2ULL, r1, m3, b2, dl2, dh2); } @@ -4972,27 +4122,18 @@ s390_emit_LOC(UChar *p, UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) static UChar * s390_emit_LOCG(UChar *p, UChar r1, UChar m3, UChar b2, UShort dl2, UChar dh2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("locg", cls_disasm), GPR(r1), SDXB(dh2, dl2, 0, b2), MASK(m3)); - return emit_RSY(p, 0xeb00000000e2ULL, r1, m3, b2, dl2, dh2); } static UChar * s390_emit_LOCGHI(UChar *p, UChar r1, UShort i2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("locghi", cls_disasm), GPR(r1), INT((Int)(Short)i2), MASK(m3)); - return emit_RIE(p, 0xec0000000046ULL, r1, i2, m3); } static UChar * s390_emit_RISBG(UChar *p, UChar r1, UChar r2, UChar i3, Char i4, UChar i5) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("risbg", rotate_disasm), GPR(r1), GPR(r2), MASK(i3), MASK(i4), MASK(i5)); - return emit_RIEf(p, 0xec0000000055ULL, r1, r2, i3, i4, i5); } @@ -5074,19 +4215,13 @@ s390_emit_load_32imm(UChar *p, UChar reg, UInt val) static UChar * s390_emit_VL(UChar *p, UChar v1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - /* m3 = 0 --> no alignment indicated */ - S390_DISASM(XMNM("vl", mask0_disasm), VR(v1), UDXB(d2, x2, b2), MASK(0)); - + /* m3 = 0 --> no alignment indicated */ return emit_VRX(p, 0xE70000000006ULL, v1, x2, b2, d2, 0); } static UChar * s390_emit_VLR(UChar *p, UChar v1, UChar v2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vlr"), VR(v1), VR(v2)); - return emit_VRR_VV(p, 0xE70000000056ULL, v1, v2); } @@ -5094,9 +4229,6 @@ s390_emit_VLR(UChar *p, UChar v1, UChar v2) static UChar * s390_emit_VLREP(UChar *p, UChar v1, UChar x2, UChar b2, UShort d2, UShort m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vlrep"), VR(v1), UDXB(d2, x2, b2), UINT(m3)); - return emit_VRX(p, 0xE70000000005ULL, v1, x2, b2, d2, m3); } @@ -5104,10 +4236,7 @@ s390_emit_VLREP(UChar *p, UChar v1, UChar x2, UChar b2, UShort d2, UShort m3) static UChar * s390_emit_VST(UChar *p, UChar v1, UChar x2, UChar b2, UShort d2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - /* As the alignment of the 2nd operand is unknown --> m3 = 0 */ - S390_DISASM(XMNM("vst", mask0_disasm), VR(v1), UDXB(d2, x2, b2), MASK(0)); - + /* As the alignment of the 2nd operand is unknown --> m3 = 0 */ return emit_VRX(p, 0xE7000000000eULL, v1, x2, b2, d2, 0); } @@ -5115,9 +4244,6 @@ s390_emit_VST(UChar *p, UChar v1, UChar x2, UChar b2, UShort d2) static UChar * s390_emit_VLGV(UChar *p, UChar r1, UChar b2, UShort d2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vlgv", va_like_disasm), GPR(r1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); - return emit_VRS(p, 0xE70000000021ULL, r1, b2, d2, v3, m4); } @@ -5125,9 +4251,6 @@ s390_emit_VLGV(UChar *p, UChar r1, UChar b2, UShort d2, UChar v3, UChar m4) static UChar * s390_emit_VLVG(UChar *p, UChar v1, UChar b2, UShort d2, UChar r3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vlvg", va_like_disasm), VR(v1), GPR(r3), UDXB(d2, 0, b2), MASK(m4)); - return emit_VRS(p, 0xE70000000022ULL, v1, b2, d2, r3, m4); } @@ -5135,54 +4258,36 @@ s390_emit_VLVG(UChar *p, UChar v1, UChar b2, UShort d2, UChar r3, UChar m4) static UChar * s390_emit_VPERM(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vperm"), VR(v1), VR(v2), VR(v3), VR(v4)); - return emit_VRR_VVVV(p, 0xE7000000008cULL, v1, v2, v3, v4); } static UChar * s390_emit_VO(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vo"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000006aULL, v1, v2, v3); } static UChar * s390_emit_VOC(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("voc"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000006fULL, v1, v2, v3); } static UChar * s390_emit_VX(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vx"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000006dULL, v1, v2, v3); } static UChar * s390_emit_VN(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vn"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE70000000068ULL, v1, v2, v3); } static UChar* s390_emit_VCEQ(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vceq", vch_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(0)); - return emit_VRR_VVVM(p, 0xE700000000f8ULL, v1, v2, v3, m4); } @@ -5190,9 +4295,6 @@ s390_emit_VCEQ(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) static UChar * s390_emit_VGBM(UChar *p, UChar v1, UShort i2) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vgbm", vgbm_disasm), VR(v1), UINT(i2)); - return emit_VRI_VI(p, 0xE70000000044ULL, v1, i2); } @@ -5200,9 +4302,6 @@ s390_emit_VGBM(UChar *p, UChar v1, UShort i2) static UChar * s390_emit_VPK(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vpk", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000094ULL, v1, v2, v3, m4); } @@ -5210,9 +4309,6 @@ s390_emit_VPK(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) static UChar * s390_emit_VPKS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vpks", vch_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(0)); - return emit_VRR_VVVM(p, 0xE70000000097ULL, v1, v2, v3, m4); } @@ -5220,9 +4316,6 @@ s390_emit_VPKS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) static UChar * s390_emit_VPKLS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vpkls", vch_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(0)); - return emit_VRR_VVVM(p, 0xE70000000095ULL, v1, v2, v3, m4); } @@ -5230,9 +4323,6 @@ s390_emit_VPKLS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) static UChar * s390_emit_VREP(UChar *p, UChar v1, UChar v3, UShort i2, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vrep", va_like_disasm), VR(v1), VR(v3), UINT(i2), MASK(m4)); - return emit_VRI_VVMM(p, 0xE7000000004DULL, v1, v3, i2, m4); } @@ -5240,9 +4330,6 @@ s390_emit_VREP(UChar *p, UChar v1, UChar v3, UShort i2, UChar m4) static UChar * s390_emit_VREPI(UChar *p, UChar v1, UShort i2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vrepi", va_like_disasm), VR(v1), INT((Short)i2), MASK(m3)); - return emit_VRI_VIM(p, 0xE70000000045ULL, v1, i2, m3); } @@ -5250,9 +4337,6 @@ s390_emit_VREPI(UChar *p, UChar v1, UShort i2, UChar m3) static UChar * s390_emit_VUPH(UChar *p, UChar v1, UChar v2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vuph", va_like_disasm), VR(v1), VR(v2), MASK(m3)); - return emit_VRR_VVM(p, 0xE700000000D7ULL, v1, v2, m3); } @@ -5260,9 +4344,6 @@ s390_emit_VUPH(UChar *p, UChar v1, UChar v2, UChar m3) static UChar * s390_emit_VUPLH(UChar *p, UChar v1, UChar v2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vuplh", va_like_disasm), VR(v1), VR(v2), MASK(m3)); - return emit_VRR_VVM(p, 0xE700000000D5ULL, v1, v2, m3); } @@ -5270,9 +4351,6 @@ s390_emit_VUPLH(UChar *p, UChar v1, UChar v2, UChar m3) static UChar* s390_emit_VMRH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmrh", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000061ULL, v1, v2, v3, m4); } @@ -5280,396 +4358,264 @@ s390_emit_VMRH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) static UChar* s390_emit_VMRL(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmrl", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000060ULL, v1, v2, v3, m4); } static UChar * s390_emit_VA(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("va", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000f3ULL, v1, v2, v3, m4); } static UChar * s390_emit_VS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vs", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000f7ULL, v1, v2, v3, m4); } static UChar * s390_emit_VNO(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vno"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000006bULL, v1, v2, v3); } static UChar * s390_emit_VCH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vch", vch_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(0)); - return emit_VRR_VVVM(p, 0xE700000000fbULL, v1, v2, v3, m4); } static UChar * s390_emit_VCHL(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vchl", vch_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(0)); - return emit_VRR_VVVM(p, 0xE700000000f9ULL, v1, v2, v3, m4); } static UChar * s390_emit_VCLZ(UChar *p, UChar v1, UChar v2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vclz", va_like_disasm), VR(v1), VR(v2), MASK(m3)); - return emit_VRR_VVM(p, 0xE70000000053ULL, v1, v2, m3); } static UChar * s390_emit_VCTZ(UChar *p, UChar v1, UChar v2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vctz", va_like_disasm), VR(v1), VR(v2), MASK(m3)); - return emit_VRR_VVM(p, 0xE70000000052ULL, v1, v2, m3); } static UChar * s390_emit_VPOPCT(UChar *p, UChar v1, UChar v2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vpopct", va_like_disasm), VR(v1), VR(v2), MASK(m3)); - return emit_VRR_VVM(p, 0xE70000000050ULL, v1, v2, m3); } static UChar * s390_emit_VMX(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmx", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000ffULL, v1, v2, v3, m4); } static UChar * s390_emit_VMXL(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmxl", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000fdULL, v1, v2, v3, m4); } static UChar * s390_emit_VMN(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmn", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000feULL, v1, v2, v3, m4); } static UChar * s390_emit_VMNL(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmnl", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000fcULL, v1, v2, v3, m4); } static UChar * s390_emit_VAVG(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vavg", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000f2ULL, v1, v2, v3, m4); } static UChar * s390_emit_VAVGL(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vavgl", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000f0ULL, v1, v2, v3, m4); } static UChar * s390_emit_VLP(UChar *p, UChar v1, UChar v2, UChar m3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vlp", va_like_disasm), VR(v1), VR(v2), MASK(m3)); - return emit_VRR_VVM(p, 0xE700000000DFULL, v1, v2, m3); } static UChar * s390_emit_VMH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmh", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000a3ULL, v1, v2, v3, m4); } static UChar * s390_emit_VMLH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmlh", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000a1ULL, v1, v2, v3, m4); } static UChar * s390_emit_VML(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vml", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000a2ULL, v1, v2, v3, m4); } static UChar * s390_emit_VMO(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmo", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000a7ULL, v1, v2, v3, m4); } static UChar * s390_emit_VMLO(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vmlo", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE700000000a5ULL, v1, v2, v3, m4); } static UChar * s390_emit_VESLV(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("veslv", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000070ULL, v1, v2, v3, m4); } static UChar * s390_emit_VESRAV(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vesrav", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE7000000007aULL, v1, v2, v3, m4); } static UChar * s390_emit_VESRLV(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vesrlv", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000078ULL, v1, v2, v3, m4); } static UChar * s390_emit_VESL(UChar *p, UChar v1, UChar b2, UShort d2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vesl", va_like_disasm), VR(v1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); - return emit_VRS(p, 0xE70000000030ULL, v1, b2, d2, v3, m4); } static UChar * s390_emit_VESRA(UChar *p, UChar v1, UChar b2, UShort d2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vesra", va_like_disasm), VR(v1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); - return emit_VRS(p, 0xE7000000003aULL, v1, b2, d2, v3, m4); } static UChar * s390_emit_VESRL(UChar *p, UChar v1, UChar b2, UShort d2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vesrl", va_like_disasm), VR(v1), VR(v3), UDXB(d2, 0, b2), MASK(m4)); - return emit_VRS(p, 0xE70000000038ULL, v1, b2, d2, v3, m4); } static UChar * s390_emit_VERLLV(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("verllv", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000073ULL, v1, v2, v3, m4); } static UChar * s390_emit_VSL(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vsl"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE70000000074ULL, v1, v2, v3); } static UChar * s390_emit_VSRL(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vsrl"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000007cULL, v1, v2, v3); } static UChar * s390_emit_VSRA(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vsra"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000007eULL, v1, v2, v3); } static UChar * s390_emit_VSLB(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vslb"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE70000000075ULL, v1, v2, v3); } static UChar * s390_emit_VSRLB(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vsrlb"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000007dULL, v1, v2, v3); } static UChar * s390_emit_VSRAB(UChar *p, UChar v1, UChar v2, UChar v3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vsrab"), VR(v1), VR(v2), VR(v3)); - return emit_VRR_VVV(p, 0xE7000000007fULL, v1, v2, v3); } static UChar * s390_emit_VSUM(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vsum", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000064ULL, v1, v2, v3, m4); } static UChar * s390_emit_VSUMG(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vsumg", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000065ULL, v1, v2, v3, m4); } static UChar * s390_emit_VSUMQ(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vsumq", va_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4)); - return emit_VRR_VVVM(p, 0xE70000000067ULL, v1, v2, v3, m4); } static UChar * s390_emit_VLVGP(UChar *p, UChar v1, UChar r2, UChar r3) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vlvgp"), VR(v1), GPR(r2), GPR(r3)); - return emit_VRR_VRR(p, 0xE70000000062ULL, v1, r2, r3); } static UChar * s390_emit_VFPSO(UChar *p, UChar v1, UChar v2, UChar m3, UChar m4, UChar m5) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vfpso"), VR(v1), VR(v2), UINT(m3), UINT(m4), UINT(m5)); - return emit_VRR_VVMMM(p, 0xE700000000CCULL, v1, v2, m3, m4, m5); } static UChar * s390_emit_VFA(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vfa"), VR(v1), VR(v2), VR(v3), UINT(m4), UINT(m5)); - return emit_VRR_VVVMM(p, 0xE700000000e3ULL, v1, v2, v3, m4, m5); } static UChar * s390_emit_VFS(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vfs"), VR(v1), VR(v2), VR(v3), UINT(m4), UINT(m5)); - return emit_VRR_VVVMM(p, 0xE700000000e2ULL, v1, v2, v3, m4, m5); } static UChar * s390_emit_VFM(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vfm"), VR(v1), VR(v2), VR(v3), UINT(m4), UINT(m5)); - return emit_VRR_VVVMM(p, 0xE700000000e7ULL, v1, v2, v3, m4, m5); } static UChar * s390_emit_VFD(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vfd"), VR(v1), VR(v2), VR(v3), UINT(m4), UINT(m5)); - return emit_VRR_VVVMM(p, 0xE700000000e5ULL, v1, v2, v3, m4, m5); } static UChar * s390_emit_VFSQ(UChar *p, UChar v1, UChar v2, UChar m3, UChar m4) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(MNM("vfsq"), VR(v1), VR(v2), UINT(m3), UINT(m4)); - return emit_VRR_VVMMM(p, 0xE700000000CEULL, v1, v2, m3, m4, 0); } @@ -5677,9 +4623,6 @@ static UChar * s390_emit_VFMA(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vfma", vfms_like_disasm), VR(v1), VR(v2), VR(v3), VR(v4), MASK(m5), MASK(m6)); - return emit_VRRe_VVVVMM(p, 0xE7000000008fULL, v1, v2, v3, v4, m5, m6); } @@ -5687,9 +4630,6 @@ static UChar * s390_emit_VFMS(UChar *p, UChar v1, UChar v2, UChar v3, UChar v4, UChar m5, UChar m6) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vfms", vfms_like_disasm), VR(v1), VR(v2), VR(v3), VR(v4), MASK(m5), MASK(m6)); - return emit_VRRe_VVVVMM(p, 0xE7000000008eULL, v1, v2, v3, v4, m5, m6); } @@ -5697,9 +4637,6 @@ static UChar * s390_emit_VFCE(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vfce", vfce_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5), MASK(m6)); - return emit_VRR_VVVMMM(p, 0xE700000000e8ULL, v1, v2, v3, m4, m5, m6); } @@ -5707,9 +4644,6 @@ static UChar * s390_emit_VFCH(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vfch", vfce_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5), MASK(m6)); - return emit_VRR_VVVMMM(p, 0xE700000000ebULL, v1, v2, v3, m4, m5, m6); } @@ -5717,9 +4651,6 @@ static UChar * s390_emit_VFCHE(UChar *p, UChar v1, UChar v2, UChar v3, UChar m4, UChar m5, UChar m6) { - if (UNLIKELY(vex_traceflags & VEX_TRACE_ASM)) - S390_DISASM(XMNM("vfche", vfce_like_disasm), VR(v1), VR(v2), VR(v3), MASK(m4), MASK(m5), MASK(m6)); - return emit_VRR_VVVMMM(p, 0xE700000000eaULL, v1, v2, v3, m4, m5, m6); } diff --git a/VEX/priv/objdump/README b/VEX/priv/objdump/README new file mode 100644 index 000000000..9ed56d253 --- /dev/null +++ b/VEX/priv/objdump/README @@ -0,0 +1,16 @@ +Files imported from binutils distribution: 2.45 + +/include/dis-asm.h -> dis-asm.h modified +/include/opcode/s390.h -> s390.h unchanged +/opcodes/dis-init.c -> dis-init.c modified +/opcodes/s390-dis.c -> s390-dis.c modified +/opcodes/s390-opc.c -> s390-opc.c modified + +s390-opc.tab generated from +/opcodes/s390-opc.txt via +/opcodes/mkopc.c + +gcc mkopc.c +./a.out < s390-opc.txt > s390-opc.tab + +Might not be worth the trouble to write an update-objdump script. diff --git a/VEX/priv/objdump/dis-asm.h b/VEX/priv/objdump/dis-asm.h new file mode 100644 index 000000000..4ca3320c1 --- /dev/null +++ b/VEX/priv/objdump/dis-asm.h @@ -0,0 +1,502 @@ +/* Interface between the opcode library and its callers. + + Copyright (C) 1999-2025 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. + + Written by Cygnus Support, 1993. + + The opcode library (libopcodes.a) provides instruction decoders for + a large variety of instruction sets, callable with an identical + interface, for making instruction-processing programs more independent + of the instruction set being processed. */ + +#ifndef DIS_ASM_H +#define DIS_ASM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "stubs.h" + +enum dis_insn_type +{ + dis_noninsn, /* Not a valid instruction. */ + dis_nonbranch, /* Not a branch instruction. */ + dis_branch, /* Unconditional branch. */ + dis_condbranch, /* Conditional branch. */ + dis_jsr, /* Jump to subroutine. */ + dis_condjsr, /* Conditional jump to subroutine. */ + dis_dref, /* Data reference instruction. */ + dis_dref2 /* Two data references in instruction. */ +}; + +/* When printing styled disassembler output, this describes what style + should be used. */ + +enum disassembler_style +{ + /* This is the default style, use this for any additional syntax + (e.g. commas between operands, brackets, etc), or just as a default if + no other style seems appropriate. */ + dis_style_text, + + /* Use this for all instruction mnemonics, or aliases for mnemonics. + These should be things that correspond to real machine + instructions. */ + dis_style_mnemonic, + + /* Some architectures include additional mnemonic like fields within the + instruction operands, e.g. on aarch64 'add w16, w7, w1, lsl #2' where + the 'lsl' is an additional piece of text that describes how the + instruction should behave. This sub-mnemonic style can be used for + these pieces of text. */ + dis_style_sub_mnemonic, + + /* For things that aren't real machine instructions, but rather + assembler directives, e.g. .byte, etc. */ + dis_style_assembler_directive, + + /* Use this for any register names. This may or may-not include any + register prefix, e.g. '$', '%', at the discretion of the target, + though within each target the choice to include prefixes for not + should be kept consistent. If the prefix is not printed with this + style, then dis_style_text should be used. */ + dis_style_register, + + /* Use this for any constant values used within instructions or + directives, unless the value is an absolute address, or an offset + that will be added to an address (no matter where the address comes + from) before use. This style may, or may-not be used for any + prefix to the immediate value, e.g. '$', at the discretion of the + target, though within each target the choice to include these + prefixes should be kept consistent. */ + dis_style_immediate, + + /* The style for the numerical representation of an absolute address. + Anything that is an address offset should use the immediate style. + This style may, or may-not be used for any prefix to the immediate + value, e.g. '$', at the discretion of the target, though within + each target the choice to include these prefixes should be kept + consistent. */ + dis_style_address, + + /* The style for any constant value within an instruction or directive + that represents an offset that will be added to an address before + use. This style may, or may-not be used for any prefix to the + immediate value, e.g. '$', at the discretion of the target, though + within each target the choice to include these prefixes should be + kept consistent. */ + dis_style_address_offset, + + /* The style for a symbol's name. The numerical address of a symbol + should use the address style above, this style is reserved for the + name. */ + dis_style_symbol, + + /* The start of a comment that runs to the end of the line. Anything + printed after a comment start might be styled differently, + e.g. everything might be styled as a comment, regardless of the + actual style used. The disassembler itself should not try to adjust + the style emitted for comment content, e.g. an address emitted within + a comment should still be given dis_style_address, in this way it is + up to the user of the disassembler to decide how comments should be + styled. */ + dis_style_comment_start +}; + +typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2; +typedef int (*fprintf_styled_ftype) (void *, enum disassembler_style, const char*, ...) ATTRIBUTE_FPTR_PRINTF_3; + +/* This struct is passed into the instruction decoding routine, + and is passed back out into each callback. The various fields are used + for conveying information from your main routine into your callbacks, + for passing information into the instruction decoders (such as the + addresses of the callback functions), or for passing information + back from the instruction decoders to their callers. + + It must be initialized before it is first passed; this can be done + by hand, or using one of the initialization macros below. */ + +typedef struct disassemble_info +{ + fprintf_ftype fprintf_func; + fprintf_styled_ftype fprintf_styled_func; + void *stream; +#if 0 + void *application_data; + + /* Target description. We could replace this with a pointer to the bfd, + but that would require one. There currently isn't any such requirement + so to avoid introducing one we record these explicitly. */ + /* The bfd_flavour. This can be bfd_target_unknown_flavour. */ + enum bfd_flavour flavour; + /* The bfd_arch value. */ + enum bfd_architecture arch; + /* The bfd_mach value. */ + unsigned long mach; + /* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */ + enum bfd_endian endian; + /* Endianness of code, for mixed-endian situations such as ARM BE8. */ + enum bfd_endian endian_code; + + /* Some targets need information about the current section to accurately + display insns. If this is NULL, the target disassembler function + will have to make its best guess. */ + asection *section; + + /* An array of pointers to symbols either at the location being disassembled + or at the start of the function being disassembled. The array is sorted + so that the first symbol is intended to be the one used. The others are + present for any misc. purposes. This is not set reliably, but if it is + not NULL, it is correct. */ + asymbol **symbols; + /* Number of symbols in array. */ + int num_symbols; + + /* Symbol table provided for targets that want to look at it. This is + used on Arm to find mapping symbols and determine Arm/Thumb code. */ + asymbol **symtab; + int symtab_pos; + int symtab_size; + + /* For use by the disassembler. + The top 16 bits are reserved for public use (and are documented here). + The bottom 16 bits are for the internal use of the disassembler. */ + unsigned long flags; + /* Set if the disassembler has determined that there are one or more + relocations associated with the instruction being disassembled. */ +#define INSN_HAS_RELOC (1u << 31) + /* Set if the user has requested the disassembly of data as well as code. */ +#define DISASSEMBLE_DATA (1u << 30) + /* Set if the user has specifically set the machine type encoded in the + mach field of this structure. */ +#define USER_SPECIFIED_MACHINE_TYPE (1u << 29) + /* Set if the user has requested wide output. */ +#define WIDE_OUTPUT (1u << 28) + + /* Dynamic relocations, if they have been loaded. */ + arelent **dynrelbuf; + long dynrelcount; + + /* Use internally by the target specific disassembly code. */ + void *private_data; + + /* Function used to get bytes to disassemble. MEMADDR is the + address of the stuff to be disassembled, MYADDR is the address to + put the bytes in, and LENGTH is the number of bytes to read. + INFO is a pointer to this struct. + Returns an errno value or 0 for success. */ + int (*read_memory_func) + (bfd_vma memaddr, bfd_byte *myaddr, unsigned int length, + struct disassemble_info *dinfo); + + /* Function which should be called if we get an error that we can't + recover from. STATUS is the errno value from read_memory_func and + MEMADDR is the address that we were trying to read. INFO is a + pointer to this struct. */ + void (*memory_error_func) + (int status, bfd_vma memaddr, struct disassemble_info *dinfo); +#endif + + /* Function called to print ADDR. */ + void (*print_address_func) + (bfd_vma addr, struct disassemble_info *dinfo); + +#if 0 + /* Function called to determine if there is a symbol at the given ADDR. + If there is, the function returns 1, otherwise it returns 0. + This is used by ports which support an overlay manager where + the overlay number is held in the top part of an address. In + some circumstances we want to include the overlay number in the + address, (normally because there is a symbol associated with + that address), but sometimes we want to mask out the overlay bits. */ + asymbol * (*symbol_at_address_func) + (bfd_vma addr, struct disassemble_info *dinfo); + + /* Function called to check if a SYMBOL is can be displayed to the user. + This is used by some ports that want to hide special symbols when + displaying debugging outout. */ + bool (*symbol_is_valid) + (asymbol *, struct disassemble_info *dinfo); + + /* These are for buffer_read_memory. */ + bfd_byte *buffer; + bfd_vma buffer_vma; + size_t buffer_length; + + /* This variable may be set by the instruction decoder. It suggests + the number of bytes objdump should display on a single line. If + the instruction decoder sets this, it should always set it to + the same value in order to get reasonable looking output. */ + int bytes_per_line; + + /* The next two variables control the way objdump displays the raw data. */ + /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */ + /* output will look like this: + 00: 00000000 00000000 + with the chunks displayed according to "display_endian". */ + int bytes_per_chunk; + enum bfd_endian display_endian; + + /* Number of octets per incremented target address + Normally one, but some DSPs have byte sizes of 16 or 32 bits. */ + unsigned int octets_per_byte; + + /* The number of zeroes we want to see at the end of a section before we + start skipping them. */ + unsigned int skip_zeroes; + + /* The number of zeroes to skip at the end of a section. If the number + of zeroes at the end is between SKIP_ZEROES_AT_END and SKIP_ZEROES, + they will be disassembled. If there are fewer than + SKIP_ZEROES_AT_END, they will be skipped. This is a heuristic + attempt to avoid disassembling zeroes inserted by section + alignment. */ + unsigned int skip_zeroes_at_end; + + /* Whether the disassembler always needs the relocations. */ + bool disassembler_needs_relocs; +#endif + + /* Results from instruction decoders. Not all decoders yet support + this information. This info is set each time an instruction is + decoded, and is only valid for the last such instruction. + + To determine whether this decoder supports this information, set + insn_info_valid to 0, decode an instruction, then check it. */ + + char insn_info_valid; /* Branch info has been set. */ + char branch_delay_insns; /* How many sequential insn's will run before + a branch takes effect. (0 = normal) */ + char data_size; /* Size of data reference in insn, in bytes */ + enum dis_insn_type insn_type; /* Type of instruction */ + bfd_vma target; /* Target address of branch or dref, if known; + zero if unknown. */ + bfd_vma target2; /* Second target address for dref2 */ + + /* Command line options specific to the target disassembler. */ + const char *disassembler_options; + + /* If non-zero then try not disassemble beyond this address, even if + there are values left in the buffer. This address is the address + of the nearest symbol forwards from the start of the disassembly, + and it is assumed that it lies on the boundary between instructions. + If an instruction spans this address then this is an error in the + file being disassembled. */ + bfd_vma stop_vma; + + /* The end range of the current range being disassembled. This is required + in order to notify the disassembler when it's currently handling a + different range than it was before. This prevent unsafe optimizations when + disassembling such as the way mapping symbols are found on AArch64. */ + bfd_vma stop_offset; + + /* Set to true if the disassembler applied styling to the output, + otherwise, set to false. */ + bool created_styled_output; +} disassemble_info; + +#if 0 +/* This struct is used to pass information about valid disassembler + option arguments from the target to the generic GDB functions + that set and display them. */ + +typedef struct +{ + /* Option argument name to use in descriptions. */ + const char *name; + + /* Vector of acceptable option argument values, NULL-terminated. + NULL if any values are accepted. */ + const char **values; +} disasm_option_arg_t; + +/* This struct is used to pass information about valid disassembler + options, their descriptions and arguments from the target to the + generic GDB functions that set and display them. Options are + defined by tuples of vector entries at each index. */ + +typedef struct +{ + /* Vector of option names, NULL-terminated. */ + const char **name; + + /* Vector of option descriptions or NULL if none to be shown. */ + const char **description; + + /* Vector of option argument information pointers or NULL if no + option accepts an argument. NULL entries denote individual + options that accept no argument. */ + const disasm_option_arg_t **arg; +} disasm_options_t; + +/* This struct is used to pass information about valid disassembler + options and arguments from the target to the generic GDB functions + that set and display them. */ + +typedef struct +{ + /* Valid disassembler options. Individual options that support + an argument will refer to entries in the ARGS vector. */ + disasm_options_t options; + + /* Vector of acceptable option arguments, NULL-terminated. This + collects all possible option argument choices, some of which + may be shared by different options from the OPTIONS member. */ + disasm_option_arg_t *args; +} disasm_options_and_args_t; + +/* Standard disassemblers. Disassemble one instruction at the given + target address. Return number of octets processed. */ +typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); + +/* Disassemblers used out side of opcodes library. */ +extern int print_insn_m32c (bfd_vma, disassemble_info *); +extern int print_insn_mep (bfd_vma, disassemble_info *); +extern int print_insn_s12z (bfd_vma, disassemble_info *); +extern int print_insn_sh (bfd_vma, disassemble_info *); +extern int print_insn_sparc (bfd_vma, disassemble_info *); +extern int print_insn_rx (bfd_vma, disassemble_info *); +extern int print_insn_rl78 (bfd_vma, disassemble_info *); +extern int print_insn_rl78_g10 (bfd_vma, disassemble_info *); +extern int print_insn_rl78_g13 (bfd_vma, disassemble_info *); +extern int print_insn_rl78_g14 (bfd_vma, disassemble_info *); + +extern disassembler_ftype arc_get_disassembler (bfd *); +extern disassembler_ftype cris_get_disassembler (bfd *); + +extern void print_aarch64_disassembler_options (FILE *); +extern void print_i386_disassembler_options (FILE *); +extern void print_mips_disassembler_options (FILE *); +extern void print_nfp_disassembler_options (FILE *); +extern void print_ppc_disassembler_options (FILE *); +extern void print_riscv_disassembler_options (FILE *); +extern void print_arm_disassembler_options (FILE *); +extern void print_arc_disassembler_options (FILE *); +extern void print_kvx_disassembler_options(FILE *); +extern void print_s390_disassembler_options (FILE *); +extern void print_wasm32_disassembler_options (FILE *); +extern void print_loongarch_disassembler_options (FILE *); +extern void print_bpf_disassembler_options (FILE *); +extern bool aarch64_symbol_is_valid (asymbol *, struct disassemble_info *); +extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *); +extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *); +extern bool riscv_symbol_is_valid (asymbol *, struct disassemble_info *); +extern void disassemble_init_powerpc (struct disassemble_info *); +#endif +extern void disassemble_init_s390 (struct disassemble_info *); +#if 0 +extern void disassemble_init_wasm32 (struct disassemble_info *); +extern void disassemble_init_nds32 (struct disassemble_info *); +extern const disasm_options_and_args_t *disassembler_options_arc (void); +extern const disasm_options_and_args_t *disassembler_options_arm (void); +extern const disasm_options_and_args_t *disassembler_options_mips (void); +extern const disasm_options_and_args_t *disassembler_options_powerpc (void); +extern const disasm_options_and_args_t *disassembler_options_riscv (void); +extern const disasm_options_and_args_t *disassembler_options_s390 (void); + +/* Fetch the disassembler for a given architecture ARC, endianess (big + endian if BIG is true), bfd_mach value MACH, and ABFD, if that support + is available. ABFD may be NULL. */ +extern disassembler_ftype disassembler (enum bfd_architecture arc, + bool big, unsigned long mach, + bfd *abfd); + +/* Amend the disassemble_info structure as necessary for the target architecture. + Should only be called after initialising the info->arch field. */ +extern void disassemble_init_for_target (struct disassemble_info *); + +/* Tidy any memory allocated by targets, such as info->private_data. */ +extern void disassemble_free_target (struct disassemble_info *); + +/* Set the basic disassembler print functions. */ +extern void disassemble_set_printf (struct disassemble_info *, void *, + fprintf_ftype, fprintf_styled_ftype); + +/* Document any target specific options available from the disassembler. */ +extern void disassembler_usage (FILE *); + +/* Remove whitespace and consecutive commas. */ +extern char *remove_whitespace_and_extra_commas (char *); + +/* Like STRCMP, but treat ',' the same as '\0' so that we match + strings like "foobar" against "foobar,xxyyzz,...". */ +extern int disassembler_options_cmp (const char *, const char *); + +/* A helper function for FOR_EACH_DISASSEMBLER_OPTION. */ +static inline const char * +next_disassembler_option (const char *options) +{ + const char *opt = strchr (options, ','); + if (opt != NULL) + opt++; + return opt; +} + +/* A macro for iterating over each comma separated option in OPTIONS. */ +#define FOR_EACH_DISASSEMBLER_OPTION(OPT, OPTIONS) \ + for ((OPT) = (OPTIONS); \ + (OPT) != NULL; \ + (OPT) = next_disassembler_option (OPT)) + + +/* This block of definitions is for particular callers who read instructions + into a buffer before calling the instruction decoder. */ + +/* Here is a function which callers may wish to use for read_memory_func. + It gets bytes from a buffer. */ +extern int buffer_read_memory + (bfd_vma, bfd_byte *, unsigned int, struct disassemble_info *); + +/* This function goes with buffer_read_memory. + It prints a message using info->fprintf_func and info->stream. */ +extern void perror_memory (int, bfd_vma, struct disassemble_info *); + + +/* Just print the address in hex. This is included for completeness even + though both GDB and objdump provide their own (to print symbolic + addresses). */ +extern void generic_print_address + (bfd_vma, struct disassemble_info *); + +/* Always NULL. */ +extern asymbol *generic_symbol_at_address + (bfd_vma, struct disassemble_info *); + +/* Always true. */ +extern bool generic_symbol_is_valid + (asymbol *, struct disassemble_info *); + +#endif + +/* Method to initialize a disassemble_info struct. This should be + called by all applications creating such a struct. */ +extern void init_disassemble_info (struct disassemble_info *dinfo, void *stream, + fprintf_ftype fprintf_func, + fprintf_styled_ftype fprintf_styled_func); + +/* For compatibility with existing code. */ +#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC, FPRINTF_STYLED_FUNC) \ + init_disassemble_info (&(INFO), (STREAM), (fprintf_ftype) (FPRINTF_FUNC), \ + (fprintf_styled_ftype) (FPRINTF_STYLED_FUNC)) + +#ifdef __cplusplus +} +#endif + +#endif /* ! defined (DIS_ASM_H) */ diff --git a/VEX/priv/objdump/dis-init.c b/VEX/priv/objdump/dis-init.c new file mode 100644 index 000000000..8a10ee31d --- /dev/null +++ b/VEX/priv/objdump/dis-init.c @@ -0,0 +1,56 @@ +/* Initialize "struct disassemble_info". + + Copyright (C) 2003-2025 Free Software Foundation, Inc. + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#include "dis-asm.h" + +void +init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func, + fprintf_styled_ftype fprintf_styled_func) +{ +#if 0 + memset(info, 0, sizeof (*info)); + + info->flavour = bfd_target_unknown_flavour; + info->arch = bfd_arch_unknown; + info->endian = BFD_ENDIAN_UNKNOWN; + info->endian_code = info->endian; + info->octets_per_byte = 1; + info->fprintf_func = fprintf_func; + info->fprintf_styled_func = fprintf_styled_func; + info->stream = stream; + info->read_memory_func = buffer_read_memory; + info->memory_error_func = perror_memory; + info->print_address_func = generic_print_address; + info->symbol_at_address_func = generic_symbol_at_address; + info->symbol_is_valid = generic_symbol_is_valid; + info->display_endian = BFD_ENDIAN_UNKNOWN; + info->created_styled_output = false; +#else + __builtin_memset(info, 0, sizeof (*info)); + + info->fprintf_func = fprintf_func; + info->fprintf_styled_func = fprintf_styled_func; + info->stream = stream; + info->print_address_func = 0; +#endif +} + diff --git a/VEX/priv/objdump/s390-dis.c b/VEX/priv/objdump/s390-dis.c new file mode 100644 index 000000000..eeae533b0 --- /dev/null +++ b/VEX/priv/objdump/s390-dis.c @@ -0,0 +1,701 @@ +/* s390-dis.c -- Disassemble S390 instructions + Copyright (C) 2000-2025 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include +#include "s390.h" +#include "dis-asm.h" +#undef NULL +#include "main_util.h" // vex_strlen +#include "s390_defs.h" // S390_MAX_MNEMONIC_LEN +#include "s390_disasm.h" + +static int opc_index[256]; +static int current_arch_mask = 0; +static int option_use_insn_len_bits_p = 0; +static int option_print_insn_desc = 0; + + +static const char * +padmnm(const char *mnm) +{ + static char buf[S390_MAX_MNEMONIC_LEN + 1]; + + if (vex_strlen(mnm) > S390_MAX_MNEMONIC_LEN) + return "failed: buf too small"; + + vex_sprintf(buf, "%-*s", S390_MAX_MNEMONIC_LEN, mnm); + + return buf; +} + + +#if 0 +typedef struct +{ + const char *name; + const char *description; +} s390_options_t; + +static const s390_options_t options[] = +{ + { "esa" , N_("Disassemble in ESA architecture mode") }, + /* TRANSLATORS: Please do not translate 'z/Architecture' as this is a technical name. */ + { "zarch", N_("Disassemble in z/Architecture mode") }, + { "insnlength", N_("Print unknown instructions according to " + "length from first two bits") }, + { "insndesc", N_("Print instruction description as comment") }, +}; +#endif + +/* Set up index table for first opcode byte. */ + +void +disassemble_init_s390 (struct disassemble_info *info) +{ + int i; + + __builtin_memset (opc_index, 0, sizeof (opc_index)); + + /* Reverse order, such that each opc_index ends up pointing to the + first matching entry instead of the last. */ + for (i = s390_num_opcodes; i--; ) + opc_index[s390_opcodes[i].opcode[0]] = i; + + current_arch_mask = 1 << S390_OPCODE_ZARCH; + option_use_insn_len_bits_p = 0; + option_print_insn_desc = 0; +#if 0 + for (p = info->disassembler_options; p != NULL; ) + { + if (startswith (p, "esa")) + current_arch_mask = 1 << S390_OPCODE_ESA; + else if (startswith (p, "zarch")) + current_arch_mask = 1 << S390_OPCODE_ZARCH; + else if (startswith (p, "insnlength")) + option_use_insn_len_bits_p = 1; + else if (startswith (p, "insndesc")) + option_print_insn_desc = 1; + else + /* xgettext:c-format */ + opcodes_error_handler (_("unknown S/390 disassembler option: %s"), p); + + p = strchr (p, ','); + if (p != NULL) + p++; + } +#endif +} + +/* Derive the length of an instruction from its first byte. */ + +static inline int +s390_insn_length (const bfd_byte *buffer) +{ + /* 00xxxxxx -> 2, 01xxxxxx/10xxxxxx -> 4, 11xxxxxx -> 6. */ + return ((buffer[0] >> 6) + 3) & ~1U; +} + +/* Match the instruction in BUFFER against the given OPCODE, excluding + the first byte. */ + +static inline int +s390_insn_matches_opcode (const bfd_byte *buffer, + const struct s390_opcode *opcode) +{ + return (buffer[1] & opcode->mask[1]) == opcode->opcode[1] + && (buffer[2] & opcode->mask[2]) == opcode->opcode[2] + && (buffer[3] & opcode->mask[3]) == opcode->opcode[3] + && (buffer[4] & opcode->mask[4]) == opcode->opcode[4] + && (buffer[5] & opcode->mask[5]) == opcode->opcode[5]; +} + +union operand_value +{ + int i; + unsigned int u; +}; + +/* Extracts an operand value from an instruction. */ +/* We do not perform the shift operation for larl-type address + operands here since that would lead to an overflow of the 32 bit + integer value. Instead the shift operation is done when printing + the operand. */ + +static inline union operand_value +s390_extract_operand (const bfd_byte *insn, + const struct s390_operand *operand) +{ + union operand_value ret; + unsigned int val; + int bits; + const bfd_byte *orig_insn = insn; + + /* Extract fragments of the operand byte for byte. */ + insn += operand->shift / 8; + bits = (operand->shift & 7) + operand->bits; + val = 0; + do + { + val <<= 8; + val |= (unsigned int) *insn++; + bits -= 8; + } + while (bits > 0); + val >>= -bits; + val &= ((1U << (operand->bits - 1)) << 1) - 1; + + /* Check for special long displacement case. */ + if (operand->bits == 20 && operand->shift == 20) + val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; + + /* Sign extend value if the operand is signed or pc relative. Avoid + integer overflows. */ + if (operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) + { + unsigned int m = 1U << (operand->bits - 1); + + if (val >= m) + ret.i = (int) (val - m) - 1 - (int) (m - 1U); + else + ret.i = (int) val; + } + else if (operand->flags & S390_OPERAND_LENGTH) + /* Length x in an instruction has real length x + 1. */ + ret.u = val + 1; + + else if (operand->flags & S390_OPERAND_VR) + { + /* Extract the extra bits for a vector register operand stored + in the RXB field. */ + unsigned vr = operand->shift == 32 ? 3 + : (unsigned) operand->shift / 4 - 2; + + ret.u = val | ((orig_insn[4] & (1 << (3 - vr))) << (vr + 1)); + } + else + ret.u = val; + + return ret; +} + +/* Return remaining operand count. */ + +static unsigned int +operand_count (const unsigned char *opindex_ptr) +{ + unsigned int count = 0; + + for (; *opindex_ptr != 0; opindex_ptr++) + { + /* Count D(X,B), D(B), and D(L,B) as one operand. Assuming correct + instruction operand definitions simply do not count D, X, and L. */ + if (!(s390_operands[*opindex_ptr].flags & (S390_OPERAND_DISP + | S390_OPERAND_INDEX + | S390_OPERAND_LENGTH))) + count++; + } + + return count; +} + +/* Return true if all remaining instruction operands are optional. */ + +static bool +skip_optargs_p (unsigned int opcode_flags, const unsigned char *opindex_ptr) +{ + if ((opcode_flags & (S390_INSTR_FLAG_OPTPARM | S390_INSTR_FLAG_OPTPARM2))) + { + unsigned int opcount = operand_count (opindex_ptr); + + if (opcount == 1) + return true; + + if ((opcode_flags & S390_INSTR_FLAG_OPTPARM2) && opcount == 2) + return true; + } + + return false; +} + +/* Return true if all remaining instruction operands are optional + and their values are zero. */ + +static bool +skip_optargs_zero_p (const bfd_byte *buffer, unsigned int opcode_flags, + const unsigned char *opindex_ptr) +{ + /* Test if remaining operands are optional. */ + if (!skip_optargs_p (opcode_flags, opindex_ptr)) + return false; + + /* Test if remaining operand values are zero. */ + for (; *opindex_ptr != 0; opindex_ptr++) + { + const struct s390_operand *operand = &s390_operands[*opindex_ptr]; + union operand_value value = s390_extract_operand (buffer, operand); + + if (value.u != 0) + return false; + } + + return true; +} + +/* Print the S390 instruction in BUFFER, assuming that it matches the + given OPCODE. */ + +static void +s390_print_insn_with_opcode (bfd_vma memaddr, + struct disassemble_info *info, + const bfd_byte *buffer, + const struct s390_opcode *opcode) +{ + const unsigned char *opindex; + char separator; + + /* Mnemonic. */ + info->fprintf_styled_func (info->stream, dis_style_mnemonic, + "%s", padmnm(opcode->name)); + + /* Operands. */ + separator = ' '; // mnemonics are padded to the right and have same width + for (opindex = opcode->operands; *opindex != 0; opindex++) + { + const struct s390_operand *operand = s390_operands + *opindex; + union operand_value val = s390_extract_operand (buffer, operand); + unsigned long flags = operand->flags; + + /* Omit index register 0, except for vector index register 0. */ + if ((flags & S390_OPERAND_INDEX) && !(flags & S390_OPERAND_VR) + && val.u == 0) + continue; + /* Omit base register 0, if no or omitted index register 0. */ + if ((flags & S390_OPERAND_BASE) && val.u == 0 && separator == '(') + { + separator = ','; + continue; + } + + /* Omit optional last operands with a value of zero, except if + within an addressing operand sequence D(X,B), D(B), and D(L,B). + Index and base register operands with a value of zero are + handled separately, as they may not be omitted unconditionally. */ + if (!(operand->flags & (S390_OPERAND_BASE + | S390_OPERAND_INDEX + | S390_OPERAND_LENGTH)) + && skip_optargs_zero_p (buffer, opcode->flags, opindex)) + break; + + if (flags & S390_OPERAND_GPR) + { + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + if ((flags & (S390_OPERAND_BASE | S390_OPERAND_INDEX)) + && val.u == 0) + info->fprintf_styled_func (info->stream, dis_style_register, + "%u", val.u); + else + info->fprintf_styled_func (info->stream, dis_style_register, + "%%r%u", val.u); + } + else if (flags & S390_OPERAND_FPR) + { + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + info->fprintf_styled_func (info->stream, dis_style_register, + "%%f%u", val.u); + } + else if (flags & S390_OPERAND_VR) + { + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + info->fprintf_styled_func (info->stream, dis_style_register, + "%%v%u", val.u); + } + else if (flags & S390_OPERAND_AR) + { + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + info->fprintf_styled_func (info->stream, dis_style_register, + "%%a%u", val.u); + } + else if (flags & S390_OPERAND_CR) + { + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + info->fprintf_styled_func (info->stream, dis_style_register, + "%%c%u", val.u); + } + else if (flags & S390_OPERAND_PCREL) + { + bfd_vma target = memaddr + val.i + val.i; + + /* Provide info for jump visualization. May be evaluated by p_a_f(). */ + info->target = target; + + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + info->print_address_func (target, info); + } + else if (flags & S390_OPERAND_SIGNED) + { + enum disassembler_style style; + + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + style = ((flags & S390_OPERAND_DISP) + ? dis_style_address_offset : dis_style_immediate); + info->fprintf_styled_func (info->stream, style, "%i", val.i); + } + else + { + enum disassembler_style style; + + if (!(flags & S390_OPERAND_LENGTH)) + { + union operand_value insn_opval; + + /* Mask any constant operand bits set in insn template. */ + insn_opval = s390_extract_operand (opcode->opcode, operand); + val.u &= ~insn_opval.u; + } + + if ((opcode->flags & S390_INSTR_FLAG_OPTPARM) + && val.u == 0 + && opindex[1] == 0) + break; + + info->fprintf_styled_func (info->stream, dis_style_text, + "%c", separator); + style = ((flags & S390_OPERAND_DISP) + ? dis_style_address_offset : dis_style_immediate); + info->fprintf_styled_func (info->stream, style, "%u", val.u); + } + + if (flags & S390_OPERAND_DISP) + separator = '('; + else if (flags & S390_OPERAND_BASE) + { + info->fprintf_styled_func (info->stream, dis_style_text, ")"); + separator = ','; + } + else + separator = ','; + } + + /* Optional: instruction name. */ + if (option_print_insn_desc && opcode->description + && opcode->description[0] != '\0') + info->fprintf_styled_func (info->stream, dis_style_comment_start, "\t# %s", + opcode->description); +} + +/* Check whether opcode A's mask is more specific than that of B. */ + +static int +opcode_mask_more_specific (const struct s390_opcode *a, + const struct s390_opcode *b) +{ + return (((int) a->mask[0] + a->mask[1] + a->mask[2] + + a->mask[3] + a->mask[4] + a->mask[5]) + > ((int) b->mask[0] + b->mask[1] + b->mask[2] + + b->mask[3] + b->mask[4] + b->mask[5])); +} + +/* Print a S390 instruction. */ + +static int +print_insn_s390 (bfd_vma memaddr, const bfd_byte *buffer, + struct disassemble_info *info) +{ + const struct s390_opcode *opcode = NULL; + + /* Set some defaults for the insn info. */ + info->insn_info_valid = 0; + info->branch_delay_insns = 0; + info->data_size = 0; + info->insn_type = dis_nonbranch; + info->target = 0; + info->target2 = 0; + +#if 0 + /* Every S390 instruction is max 6 bytes long. */ + memset (buffer, 0, 6); + status = info->read_memory_func (memaddr, buffer, 6, info); + if (status != 0) + { + for (bufsize = 0; bufsize < 6; bufsize++) + if (info->read_memory_func (memaddr, buffer, bufsize + 1, info) != 0) + break; + if (bufsize <= 0) + { + info->memory_error_func (status, memaddr, info); + return -1; + } + opsize = s390_insn_length (buffer); + status = opsize > bufsize; + } + else + { + bufsize = 6; + opsize = s390_insn_length (buffer); + } +#endif + int status = 0; + int opsize = s390_insn_length (buffer); + + if (status == 0) + { + const struct s390_opcode *op; + + /* Find the "best match" in the opcode table. */ + for (op = s390_opcodes + opc_index[buffer[0]]; + op != s390_opcodes + s390_num_opcodes + && op->opcode[0] == buffer[0]; + op++) + { + if ((op->modes & current_arch_mask) + && s390_insn_matches_opcode (buffer, op) + && (opcode == NULL + || opcode_mask_more_specific (op, opcode))) + opcode = op; + } + + if (opcode != NULL) + { + /* Provide info for jump visualization. Must be done before print. */ + switch (opcode->flags & S390_INSTR_FLAG_CLASS_MASK) + { + case S390_INSTR_FLAGS_CLASS_JUMP: + info->insn_type = dis_branch; + break; + case S390_INSTR_FLAGS_CLASS_CONDJUMP: + info->insn_type = dis_condbranch; + break; + case S390_INSTR_FLAGS_CLASS_JUMPSR: + info->insn_type = dis_jsr; + break; + default: + info->insn_type = dis_nonbranch; + } + info->insn_info_valid = 1; + + /* The instruction is valid. Print it and return its size. */ + s390_print_insn_with_opcode (memaddr, info, buffer, opcode); + return opsize; + } + } + return 0; // failed +} + +#if 0 + /* For code sections it makes sense to skip unknown instructions + according to their length bits. */ + if (status == 0 + && option_use_insn_len_bits_p + && info->section != NULL + && (info->section->flags & SEC_CODE)) + bytes_to_dump = opsize; + else + /* By default unknown instructions are printed as .long's/.short' + depending on how many bytes are available. */ + bytes_to_dump = bufsize >= 4 ? 4 : bufsize; + + if (bytes_to_dump == 0) + return 0; + + info->insn_type = dis_noninsn; + info->insn_info_valid = 1; + + /* Fall back to hex print. */ + switch (bytes_to_dump) + { + case 4: + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + value = (value << 8) + (unsigned int) buffer[2]; + value = (value << 8) + (unsigned int) buffer[3]; + info->fprintf_styled_func (info->stream, dis_style_assembler_directive, + ".long"); + info->fprintf_styled_func (info->stream, dis_style_text, + "\t"); + info->fprintf_styled_func (info->stream, dis_style_immediate, + "0x%08x", value); + return 4; + case 2: + value = (unsigned int) buffer[0]; + value = (value << 8) + (unsigned int) buffer[1]; + info->fprintf_styled_func (info->stream, dis_style_assembler_directive, + ".short"); + info->fprintf_styled_func (info->stream, dis_style_text, + "\t"); + info->fprintf_styled_func (info->stream, dis_style_immediate, + "0x%04x", value); + return 2; + default: + info->fprintf_styled_func (info->stream, dis_style_assembler_directive, + ".byte"); + info->fprintf_styled_func (info->stream, dis_style_text, + "\t"); + info->fprintf_styled_func (info->stream, dis_style_immediate, + "0x%02x", (unsigned int) buffer[0]); + for (i = 1; i < bytes_to_dump; i++) + info->fprintf_styled_func (info->stream, dis_style_immediate, + "0x%02x", (unsigned int) buffer[i]); + return bytes_to_dump; + } + return 0; +} + +const disasm_options_and_args_t * +disassembler_options_s390 (void) +{ + static disasm_options_and_args_t *opts_and_args; + + if (opts_and_args == NULL) + { + size_t i, num_options = ARRAY_SIZE (options); + disasm_options_t *opts; + + opts_and_args = XNEW (disasm_options_and_args_t); + opts_and_args->args = NULL; + + opts = &opts_and_args->options; + opts->name = XNEWVEC (const char *, num_options + 1); + opts->description = XNEWVEC (const char *, num_options + 1); + opts->arg = NULL; + for (i = 0; i < num_options; i++) + { + opts->name[i] = options[i].name; + opts->description[i] = _(options[i].description); + } + /* The array we return must be NULL terminated. */ + opts->name[i] = NULL; + opts->description[i] = NULL; + } + + return opts_and_args; +} + +void +print_s390_disassembler_options (FILE *stream) +{ + unsigned int i, max_len = 0; + fprintf (stream, _("\n\ +The following S/390 specific disassembler options are supported for use\n\ +with the -M switch (multiple options should be separated by commas):\n")); + + for (i = 0; i < ARRAY_SIZE (options); i++) + { + unsigned int len = strlen (options[i].name); + if (max_len < len) + max_len = len; + } + + for (i = 0, max_len++; i < ARRAY_SIZE (options); i++) + fprintf (stream, " %s%*c %s\n", + options[i].name, + (int)(max_len - strlen (options[i].name)), ' ', + _(options[i].description)); +} +#endif + + +/* Pseudo FILE object for strings. */ +typedef struct { + char buf[128]; // holds the disassembled insn; large enough + size_t pos; + size_t alloc; + unsigned (*val_vsprintf)(char *, const char *, va_list); // == vex_vsprintf + struct disassemble_info *info; +} SFILE; + +static unsigned +sprintf_cb(SFILE *f, enum disassembler_style style, const char *fmt, ...) +{ + va_list args; + unsigned space = f->alloc - f->pos; + unsigned n; + + va_start(args, fmt); + n = f->val_vsprintf(f->buf + f->pos, fmt, args); + va_end(args); + + if (space <= n) + vassert(0); + + f->pos += n; + + return n; +} + +static void +objdump_print_pcrel(bfd_vma addr, struct disassemble_info *info) +{ + /* this really is a signed offset in bytes */ + long long offset = (long long)addr; + + (*info->fprintf_styled_func)(info->stream, dis_style_text, + (offset < 0) ? ".%lld" : ".+%lld", offset); +} + + +static void +s390_disasm_init(SFILE *dis, unsigned (*fp)(char *, const char *, va_list)) +{ + static struct disassemble_info info; + + init_disassemble_info(&info, dis, NULL, + (fprintf_styled_ftype) sprintf_cb); + disassemble_init_s390(&info); + info.print_address_func = objdump_print_pcrel; + + /* Initialise the SFILE object */ + dis->val_vsprintf = fp; + dis->pos = 0; + dis->alloc = sizeof dis->buf; + dis->buf[0] = '\0'; + dis->info = &info; +} + + +void +s390_disasm(const unsigned char insn[]) +{ + static int initialised = 0; + static SFILE disasm; + + if (! initialised) { + initialised = 1; + s390_disasm_init(&disasm, vex_vsprintf); + } + + disasm.pos = 0; /* reset */ + disasm.buf[0] = '\0'; + + /* Passing 0 as an address which is only used for symbolically print + a PC-relative operand like so . That means: in + objdump_print_pcrel we get the offset and can write it out relative to + the current address: .+offset of .-offset */ + int rc = print_insn_s390(/* address */ 0, insn, disasm.info); + + vex_printf("%s\n", (rc == 0) ? "disassemly failed" : disasm.buf); +} diff --git a/VEX/priv/objdump/s390-opc.c b/VEX/priv/objdump/s390-opc.c new file mode 100644 index 000000000..f351aadc4 --- /dev/null +++ b/VEX/priv/objdump/s390-opc.c @@ -0,0 +1,814 @@ +/* s390-opc.c -- S390 opcode list + Copyright (C) 2000-2025 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of the GNU opcodes library. + + This library is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3, or (at your option) + any later version. + + It is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY + or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, + MA 02110-1301, USA. */ + +#include "stubs.h" +#include "s390.h" + +/* This file holds the S390 opcode table. The opcode table + includes almost all of the extended instruction mnemonics. This + permits the disassembler to use them, and simplifies the assembler + logic, at the cost of increasing the table size. The table is + strictly constant data, so the compiler should be able to put it in + the .text section. + + This file also holds the operand table. All knowledge about + inserting operands into instructions and vice-versa is kept in this + file. */ + +/* Build-time checks are preferrable over runtime ones. Use this construct + in preference where possible. */ +#ifndef static_assert +#define static_assert(e) ((void)sizeof (struct { int _:1 - 2 * !(e); })) +#endif + +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/* The operands table. + The fields are bits, shift, insert, extract, flags. */ + +const struct s390_operand s390_operands[] = +{ +#define UNUSED 0 + { 0, 0, 0 }, /* Indicates the end of the operand list */ + +/* General purpose register operands. */ + +#define R_8 (UNUSED + 1) /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR }, +#define R_12 (R_8 + 1) /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR }, +#define R_16 (R_12 + 1) /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR }, +#define R_20 (R_16 + 1) /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR }, +#define R_24 (R_20 + 1) /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR }, +#define R_28 (R_24 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR }, +#define R_CP16_28 (R_28 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ +#define R_32 (R_CP16_28+1) /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR }, + +/* General purpose register pair operands. */ + +#define RE_8 (R_32 + 1) /* GPR starting at position 8 */ + { 4, 8, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_12 (RE_8 + 1) /* GPR starting at position 12 */ + { 4, 12, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_16 (RE_12 + 1) /* GPR starting at position 16 */ + { 4, 16, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_20 (RE_16 + 1) /* GPR starting at position 20 */ + { 4, 20, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_24 (RE_20 + 1) /* GPR starting at position 24 */ + { 4, 24, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_28 (RE_24 + 1) /* GPR starting at position 28 */ + { 4, 28, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, +#define RE_32 (RE_28 + 1) /* GPR starting at position 32 */ + { 4, 32, S390_OPERAND_GPR | S390_OPERAND_REG_PAIR }, + +/* Floating point register operands. */ + +#define F_8 (RE_32 + 1) /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR }, +#define F_12 (F_8 + 1) /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR }, +#define F_16 (F_12 + 1) /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR }, +#define F_24 (F_16 + 1) /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR }, +#define F_28 (F_24 + 1) /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR }, +#define F_32 (F_28 + 1) /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR }, + +/* Floating point register pair operands. */ + +#define FE_8 (F_32 + 1) /* FPR starting at position 8 */ + { 4, 8, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_12 (FE_8 + 1) /* FPR starting at position 12 */ + { 4, 12, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_16 (FE_12 + 1) /* FPR starting at position 16 */ + { 4, 16, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_24 (FE_16 + 1) /* FPR starting at position 24 */ + { 4, 24, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_28 (FE_24 + 1) /* FPR starting at position 28 */ + { 4, 28, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, +#define FE_32 (FE_28 + 1) /* FPR starting at position 32 */ + { 4, 32, S390_OPERAND_FPR | S390_OPERAND_REG_PAIR }, + +/* Vector register operands. */ + +/* For each of these operands and additional bit in the RXB operand is + needed. */ + +#define V_8 (FE_32 + 1) /* Vector reg. starting at position 8 */ + { 4, 8, S390_OPERAND_VR }, +#define V_12 (V_8 + 1) /* Vector reg. starting at position 12 */ + { 4, 12, S390_OPERAND_VR }, +#define V_CP16_12 (V_12 + 1) /* Vector reg. starting at position 12 */ + { 4, 12, S390_OPERAND_VR | S390_OPERAND_CP16 }, /* with a copy at pos 16 */ +#define V_16 (V_CP16_12+1) /* Vector reg. starting at position 16 */ + { 4, 16, S390_OPERAND_VR }, +#define V_32 (V_16 + 1) /* Vector reg. starting at position 32 */ + { 4, 32, S390_OPERAND_VR }, + +/* Access register operands. */ + +#define A_8 (V_32 + 1) /* Access reg. starting at position 8 */ + { 4, 8, S390_OPERAND_AR }, +#define A_12 (A_8 + 1) /* Access reg. starting at position 12 */ + { 4, 12, S390_OPERAND_AR }, +#define A_24 (A_12 + 1) /* Access reg. starting at position 24 */ + { 4, 24, S390_OPERAND_AR }, +#define A_28 (A_24 + 1) /* Access reg. starting at position 28 */ + { 4, 28, S390_OPERAND_AR }, + +/* Control register operands. */ + +#define C_8 (A_28 + 1) /* Control reg. starting at position 8 */ + { 4, 8, S390_OPERAND_CR }, +#define C_12 (C_8 + 1) /* Control reg. starting at position 12 */ + { 4, 12, S390_OPERAND_CR }, + +/* Base register operands. */ + +#define B_16 (C_12 + 1) /* Base register starting at position 16 */ + { 4, 16, S390_OPERAND_BASE | S390_OPERAND_GPR }, +#define B_32 (B_16 + 1) /* Base register starting at position 32 */ + { 4, 32, S390_OPERAND_BASE | S390_OPERAND_GPR }, + +#define X_12 (B_32 + 1) /* Index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_GPR }, + +#define VX_12 (X_12+1) /* Vector index register starting at position 12 */ + { 4, 12, S390_OPERAND_INDEX | S390_OPERAND_VR }, + +/* Address displacement operands. */ + +#define D_20 (VX_12 + 1) /* Displacement starting at position 20 */ + { 12, 20, S390_OPERAND_DISP }, +#define D_36 (D_20 + 1) /* Displacement starting at position 36 */ + { 12, 36, S390_OPERAND_DISP }, +#define D20_20 (D_36 + 1) /* 20 bit displacement starting at 20 */ + { 20, 20, S390_OPERAND_DISP | S390_OPERAND_SIGNED }, + +/* Length operands. */ + +#define L4_8 (D20_20 + 1) /* 4 bit length starting at position 8 */ + { 4, 8, S390_OPERAND_LENGTH }, +#define L4_12 (L4_8 + 1) /* 4 bit length starting at position 12 */ + { 4, 12, S390_OPERAND_LENGTH }, +#define L8_8 (L4_12 + 1) /* 8 bit length starting at position 8 */ + { 8, 8, S390_OPERAND_LENGTH }, + +/* Signed immediate operands. */ + +#define I8_8 (L8_8 + 1) /* 8 bit signed value starting at 8 */ + { 8, 8, S390_OPERAND_SIGNED }, +#define I8_32 (I8_8 + 1) /* 8 bit signed value starting at 32 */ + { 8, 32, S390_OPERAND_SIGNED }, +#define I12_12 (I8_32 + 1) /* 12 bit signed value starting at 12 */ + { 12, 12, S390_OPERAND_SIGNED }, +#define I16_16 (I12_12 + 1) /* 16 bit signed value starting at 16 */ + { 16, 16, S390_OPERAND_SIGNED }, +#define I16_32 (I16_16 + 1) /* 16 bit signed value starting at 32 */ + { 16, 32, S390_OPERAND_SIGNED }, +#define I24_24 (I16_32 + 1) /* 24 bit signed value starting at 24 */ + { 24, 24, S390_OPERAND_SIGNED }, +#define I32_16 (I24_24 + 1) /* 32 bit signed value starting at 16 */ + { 32, 16, S390_OPERAND_SIGNED }, + +/* Unsigned immediate operands. */ + +#define U4_8 (I32_16 + 1) /* 4 bit unsigned value starting at 8 */ + { 4, 8, 0 }, +#define U4_12 (U4_8 + 1) /* 4 bit unsigned value starting at 12 */ + { 4, 12, 0 }, +#define U4_16 (U4_12 + 1) /* 4 bit unsigned value starting at 16 */ + { 4, 16, 0 }, +#define U4_20 (U4_16 + 1) /* 4 bit unsigned value starting at 20 */ + { 4, 20, 0 }, +#define U4_24 (U4_20 + 1) /* 4 bit unsigned value starting at 24 */ + { 4, 24, 0 }, +#define U4_28 (U4_24+1) /* 4 bit unsigned value starting at 28 */ + { 4, 28, 0 }, +#define U4_32 (U4_28+1) /* 4 bit unsigned value starting at 32 */ + { 4, 32, 0 }, +#define U4_36 (U4_32 + 1) /* 4 bit unsigned value starting at 36 */ + { 4, 36, 0 }, +#define U8_8 (U4_36 + 1) /* 8 bit unsigned value starting at 8 */ + { 8, 8, 0 }, +#define U8_16 (U8_8 + 1) /* 8 bit unsigned value starting at 16 */ + { 8, 16, 0 }, +#define U8_24 (U8_16 + 1) /* 8 bit unsigned value starting at 24 */ + { 8, 24, 0 }, +#define U8_28 (U8_24 + 1) /* 8 bit unsigned value starting at 28 */ + { 8, 28, 0 }, +#define U8_32 (U8_28 + 1) /* 8 bit unsigned value starting at 32 */ + { 8, 32, 0 }, +#define U12_16 (U8_32 + 1) /* 12 bit unsigned value starting at 16 */ + { 12, 16, 0 }, +#define U16_16 (U12_16 + 1) /* 16 bit unsigned value starting at 16 */ + { 16, 16, 0 }, +#define U16_20 (U16_16 + 1) /* 16 bit unsigned value starting at 20 */ + { 16, 20, 0 }, +#define U16_32 (U16_20 + 1) /* 16 bit unsigned value starting at 32 */ + { 16, 32, 0 }, +#define U32_16 (U16_32 + 1) /* 32 bit unsigned value starting at 16 */ + { 32, 16, 0 }, + +/* PC-relative address operands. */ + +#define J12_12 (U32_16 + 1) /* 12 bit PC relative offset at 12 */ + { 12, 12, S390_OPERAND_PCREL }, +#define J16_16 (J12_12 + 1) /* 16 bit PC relative offset at 16 */ + { 16, 16, S390_OPERAND_PCREL }, +#define J16_32 (J16_16 + 1) /* 16 bit PC relative offset at 32 */ + { 16, 32, S390_OPERAND_PCREL }, +#define J24_24 (J16_32 + 1) /* 24 bit PC relative offset at 24 */ + { 24, 24, S390_OPERAND_PCREL }, +#define J32_16 (J24_24 + 1) /* 32 bit PC relative offset at 16 */ + { 32, 16, S390_OPERAND_PCREL }, + +}; + +static inline void ATTRIBUTE_UNUSED +unused_s390_operands_static_asserts (void) +{ + static_assert (ARRAY_SIZE (s390_operands) - 1 == J32_16); +} + +/* Macros used to form opcodes. */ + +/* 8/16/48 bit opcodes. */ +#define OP8(x) { x, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define OP16(x) { x >> 8, x & 255, 0x00, 0x00, 0x00, 0x00 } +#define OP32(x) { x >> 24, (x >> 16) & 255, (x >> 8) & 255, x & 255, \ + 0x00, 0x00 } +#define OP48(x) { x >> 40, (x >> 32) & 255, (x >> 24) & 255, \ + (x >> 16) & 255, (x >> 8) & 255, x & 255} + +/* The new format of the INSTR_x_y and MASK_x_y defines is based + on the following rules: + 1) the middle part of the definition (x in INSTR_x_y) is the official + names of the instruction format that you can find in the principals + of operation. + 2) the last part of the definition (y in INSTR_x_y) gives you an idea + which operands the binary represenation of the instruction has. + The meanings of the letters in y are: + a - access register + c - control register + d - displacement, 12 bit + f - floating pointer register + fe - fpr extended operand, a valid floating pointer register pair + i - signed integer, 4, 8, 16 or 32 bit + l - length, 4 or 8 bit + p - pc relative + r - general purpose register + re - gpr extended operand, a valid general purpose register pair + u - unsigned integer, 4, 8, 16 or 32 bit + m - mode field, 4 bit + 0 - operand skipped. + The order of the letters reflects the layout of the format in + storage and not the order of the paramaters of the instructions. + The use of the letters is not a 100% match with the PoP but it is + quite close. + + For example the instruction "mvo" is defined in the PoP as follows: + + MVO D1(L1,B1),D2(L2,B2) [SS] + + -------------------------------------- + | 'F1' | L1 | L2 | B1 | D1 | B2 | D2 | + -------------------------------------- + 0 8 12 16 20 32 36 + + The instruction format is: INSTR_SS_LLRDRD / MASK_SS_LLRDRD. */ + +#define INSTR_E 2, { 0,0,0,0,0,0 } /* e.g. pr */ +#define INSTR_IE_UU 4, { U4_24,U4_28,0,0,0,0 } /* e.g. niai */ +#define INSTR_MII_UPP 6, { U4_8,J12_12,J24_24 } /* e.g. bprp */ +#define INSTR_RIE_RRP 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxhg */ +#define INSTR_RIE_RRPU 6, { R_8,R_12,U4_32,J16_16,0,0 } /* e.g. crj */ +#define INSTR_RIE_RRP0 6, { R_8,R_12,J16_16,0,0,0 } /* e.g. cgrjne */ +#define INSTR_RIE_RRI0 6, { R_8,R_12,I16_16,0,0,0 } /* e.g. ahik */ +#define INSTR_RIE_RUPI 6, { R_8,I8_32,U4_12,J16_16,0,0 } /* e.g. cij */ +#define INSTR_RIE_R0PI 6, { R_8,I8_32,J16_16,0,0,0 } /* e.g. cijne */ +#define INSTR_RIE_RUPU 6, { R_8,U8_32,U4_12,J16_16,0,0 } /* e.g. clij */ +#define INSTR_RIE_R0PU 6, { R_8,U8_32,J16_16,0,0,0 } /* e.g. clijne */ +#define INSTR_RIE_R0IU 6, { R_8,I16_16,U4_32,0,0,0 } /* e.g. cit */ +#define INSTR_RIE_R0I0 6, { R_8,I16_16,0,0,0,0 } /* e.g. citne */ +#define INSTR_RIE_R0UU 6, { R_8,U16_16,U4_32,0,0,0 } /* e.g. clfit */ +#define INSTR_RIE_R0U0 6, { R_8,U16_16,0,0,0,0 } /* e.g. clfitne */ +#define INSTR_RIE_RUI0 6, { R_8,I16_16,U4_12,0,0,0 } /* e.g. lochi */ +#define INSTR_RIE_RRUUU 6, { R_8,R_12,U8_16,U8_24,U8_32,0 } /* e.g. rnsbg */ +#define INSTR_RIE_RRUUU2 INSTR_RIE_RRUUU /* e.g. risbgz */ +#define INSTR_RIE_RRUUU3 INSTR_RIE_RRUUU /* e.g. risbhg */ +#define INSTR_RIE_RRUUU4 INSTR_RIE_RRUUU /* e.g. rnsbgt */ +#define INSTR_RIL_0P 6, { J32_16,0,0,0,0 } /* e.g. jg */ +#define INSTR_RIL_RP 6, { R_8,J32_16,0,0,0,0 } /* e.g. brasl */ +#define INSTR_RIL_UP 6, { U4_8,J32_16,0,0,0,0 } /* e.g. brcl */ +#define INSTR_RIL_RI 6, { R_8,I32_16,0,0,0,0 } /* e.g. afi */ +#define INSTR_RIL_RU 6, { R_8,U32_16,0,0,0,0 } /* e.g. alfi */ +#define INSTR_RI_0P 4, { J16_16,0,0,0,0,0 } /* e.g. j */ +#define INSTR_RI_RI 4, { R_8,I16_16,0,0,0,0 } /* e.g. ahi */ +#define INSTR_RI_RP 4, { R_8,J16_16,0,0,0,0 } /* e.g. brct */ +#define INSTR_RI_RU 4, { R_8,U16_16,0,0,0,0 } /* e.g. tml */ +#define INSTR_RI_UP 4, { U4_8,J16_16,0,0,0,0 } /* e.g. brc */ +#define INSTR_RIS_RURDI 6, { R_8,I8_32,U4_12,D_20,B_16,0 } /* e.g. cib */ +#define INSTR_RIS_R0RDI 6, { R_8,I8_32,D_20,B_16,0,0 } /* e.g. cibne */ +#define INSTR_RIS_RURDU 6, { R_8,U8_32,U4_12,D_20,B_16,0 } /* e.g. clib */ +#define INSTR_RIS_R0RDU 6, { R_8,U8_32,D_20,B_16,0,0 } /* e.g. clibne*/ +#define INSTR_RRE_00 4, { 0,0,0,0,0,0 } /* e.g. palb */ +#define INSTR_RRE_0R 4, { R_28,0,0,0,0,0 } /* e.g. tb */ +#define INSTR_RRE_AA 4, { A_24,A_28,0,0,0,0 } /* e.g. cpya */ +#define INSTR_RRE_AR 4, { A_24,R_28,0,0,0,0 } /* e.g. sar */ +#define INSTR_RRE_F0 4, { F_24,0,0,0,0,0 } /* e.g. lzer */ +#define INSTR_RRE_FE0 4, { FE_24,0,0,0,0,0 } /* e.g. lzxr */ +#define INSTR_RRE_FF 4, { F_24,F_28,0,0,0,0 } /* e.g. debr */ +#define INSTR_RRE_FEF 4, { FE_24,F_28,0,0,0,0 } /* e.g. lxdbr */ +#define INSTR_RRE_FFE 4, { F_24,FE_28,0,0,0,0 } /* e.g. lexr */ +#define INSTR_RRE_FEFE 4, { FE_24,FE_28,0,0,0,0 } /* e.g. dxr */ +#define INSTR_RRE_R0 4, { R_24,0,0,0,0,0 } /* e.g. ipm */ +#define INSTR_RRE_RA 4, { R_24,A_28,0,0,0,0 } /* e.g. ear */ +#define INSTR_RRE_RF 4, { R_24,F_28,0,0,0,0 } /* e.g. lgdr */ +#define INSTR_RRE_RFE 4, { R_24,FE_28,0,0,0,0 } /* e.g. csxtr */ +#define INSTR_RRE_RR 4, { R_24,R_28,0,0,0,0 } /* e.g. lura */ +#define INSTR_RRE_RER 4, { RE_24,R_28,0,0,0,0 } /* e.g. tre */ +#define INSTR_RRE_RERE 4, { RE_24,RE_28,0,0,0,0 } /* e.g. cuse */ +#define INSTR_RRE_FR 4, { F_24,R_28,0,0,0,0 } /* e.g. ldgr */ +#define INSTR_RRE_FER 4, { FE_24,R_28,0,0,0,0 } /* e.g. cxfbr */ +#define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ +#define INSTR_RRF_FE0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. myr */ +#define INSTR_RRF_F0FF2 4, { F_24,F_16,F_28,0,0,0 } /* e.g. cpsdr */ +#define INSTR_RRF_F0FR 4, { F_24,F_16,R_28,0,0,0 } /* e.g. iedtr */ +#define INSTR_RRF_FE0FER 4, { FE_24,FE_16,R_28,0,0,0 } /* e.g. iextr */ +#define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ +#define INSTR_RRF_FEUFEFE 4, { FE_24,FE_16,FE_28,U4_20,0,0 } /* e.g. qaxtr */ +#define INSTR_RRF_FUFF2 4, { F_24,F_28,F_16,U4_20,0,0 } /* e.g. adtra */ +#define INSTR_RRF_FEUFEFE2 4, { FE_24,FE_28,FE_16,U4_20,0,0 } /* e.g. axtra */ +#define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. ipte */ +#define INSTR_RRF_RURR2 4, { R_24,R_16,R_28,U4_20,0,0 } /* e.g. lptea */ +#define INSTR_RRF_R0RR 4, { R_24,R_16,R_28,0,0,0 } /* e.g. idte */ +#define INSTR_RRF_R0RR2 4, { R_24,R_28,R_16,0,0,0 } /* e.g. ark */ +#define INSTR_RRF_R0RER 4, { RE_24,R_28,R_16,0,0,0 } /* e.g. mgrk */ +#define INSTR_RRF_R0RR3 4, { R_24,R_28,R_16,0,0,0 } /* e.g. selrz */ +#define INSTR_RRF_R0RR4 4, { R_24,R_CP16_28,0,0,0,0 } /* e.g. notr */ +#define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. fidbr */ +#define INSTR_RRF_U0FEFE 4, { FE_24,U4_16,FE_28,0,0,0 } /* e.g. fixbr */ +#define INSTR_RRF_U0RF 4, { R_24,U4_16,F_28,0,0,0 } /* e.g. cfebr */ +#define INSTR_RRF_U0RFE 4, { R_24,U4_16,FE_28,0,0,0 } /* e.g. cfxbr */ +#define INSTR_RRF_UUFF 4, { F_24,U4_16,F_28,U4_20,0,0 } /* e.g. fidtr */ +#define INSTR_RRF_UUFFE 4, { F_24,U4_16,FE_28,U4_20,0,0 } /* e.g. ldxtr */ +#define INSTR_RRF_UUFEFE 4, { FE_24,U4_16,FE_28,U4_20,0,0 } /* e.g. fixtr */ +#define INSTR_RRF_0UFF 4, { F_24,F_28,U4_20,0,0,0 } /* e.g. ldetr */ +#define INSTR_RRF_0UFEF 4, { FE_24,F_28,U4_20,0,0,0 } /* e.g. lxdtr */ +#define INSTR_RRF_FFRU 4, { F_24,F_16,R_28,U4_20,0,0 } /* e.g. rrdtr */ +#define INSTR_RRF_FEFERU 4, { FE_24,FE_16,R_28,U4_20,0,0 } /* e.g. rrxtr */ +#define INSTR_RRF_U0RR 4, { R_24,R_28,U4_16,0,0,0 } /* e.g. sske */ +#define INSTR_RRF_U0RER 4, { RE_24,R_28,U4_16,0,0,0 } /* e.g. trte */ +#define INSTR_RRF_U0RERE 4, { RE_24,RE_28,U4_16,0,0,0 } /* e.g. cu24 */ +#define INSTR_RRF_00RR 4, { R_24,R_28,0,0,0,0 } /* e.g. clrtne */ +#define INSTR_RRF_0URF 4, { R_24,F_28,U4_20,0,0,0 } /* e.g. csdtr */ +#define INSTR_RRF_0UREFE 4, { RE_24,FE_28,U4_20,0,0,0 } /* e.g. csxtr */ +#define INSTR_RRF_UUFR 4, { F_24,U4_16,R_28,U4_20,0,0 } /* e.g. cdgtra */ +#define INSTR_RRF_UUFER 4, { FE_24,U4_16,R_28,U4_20,0,0 } /* e.g. cxfbra */ +#define INSTR_RRF_UURF 4, { R_24,U4_16,F_28,U4_20,0,0 } /* e.g. cgdtra */ +#define INSTR_RRF_UURFE 4, { R_24,U4_16,FE_28,U4_20,0,0 } /* e.g. cfxbra */ +#define INSTR_RR_0R 2, { R_12, 0,0,0,0,0 } /* e.g. br */ +#define INSTR_RR_FF 2, { F_8,F_12,0,0,0,0 } /* e.g. adr */ +#define INSTR_RR_FEF 2, { FE_8,F_12,0,0,0,0 } /* e.g. mxdr */ +#define INSTR_RR_FFE 2, { F_8,FE_12,0,0,0,0 } /* e.g. ldxr */ +#define INSTR_RR_FEFE 2, { FE_8,FE_12,0,0,0,0 } /* e.g. axr */ +#define INSTR_RR_R0 2, { R_8, 0,0,0,0,0 } /* e.g. spm */ +#define INSTR_RR_RR 2, { R_8,R_12,0,0,0,0 } /* e.g. lr */ +#define INSTR_RR_RER 2, { RE_8,R_12,0,0,0,0 } /* e.g. dr */ +#define INSTR_RR_U0 2, { U8_8, 0,0,0,0,0 } /* e.g. svc */ +#define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ +#define INSTR_RRR_F0FF 4, { F_24,F_28,F_16,0,0,0 } /* e.g. ddtr */ +#define INSTR_RRR_FE0FEFE 4, { FE_24,FE_28,FE_16,0,0,0 } /* e.g. axtr */ +#define INSTR_RRS_RRRDU 6, { R_8,R_12,U4_32,D_20,B_16 } /* e.g. crb */ +#define INSTR_RRS_RRRD0 6, { R_8,R_12,D_20,B_16,0 } /* e.g. crbne */ +#define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ +#define INSTR_RSE_RERERD 6, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. mvclu */ +#define INSTR_RSE_CCRD 6, { C_8,C_12,D_20,B_16,0,0 } /* e.g. stctg */ +#define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSL_R0RD 6, { D_20,L4_8,B_16,0,0,0 } /* e.g. tp */ +#define INSTR_RSL_LRDFU 6, { F_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cdzt */ +#define INSTR_RSL_LRDFEU 6, { FE_32,D_20,L8_8,B_16,U4_36,0 } /* e.g. cxzt */ +#define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ +#define INSTR_RSY_RERERD 6, { RE_8,RE_12,D20_20,B_16,0,0 } /* e.g. cdsy */ +#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSY_RURD2 6, { R_8,D20_20,B_16,U4_12,0,0 } /* e.g. loc */ +#define INSTR_RSY_R0RD 6, { R_8,D20_20,B_16,0,0,0 } /* e.g. locne */ +#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ +#define INSTR_RSY_CCRD 6, { C_8,C_12,D20_20,B_16,0,0 } /* e.g. stctg */ +#define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ +#define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ +#define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ +#define INSTR_RS_RE0RD 4, { RE_8,D_20,B_16,0,0,0 } /* e.g. slda */ +#define INSTR_RS_RRRD 4, { R_8,R_12,D_20,B_16,0,0 } /* e.g. cs */ +#define INSTR_RS_RERERD 4, { RE_8,RE_12,D_20,B_16,0,0 } /* e.g. cds */ +#define INSTR_RS_RURD 4, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icm */ +#define INSTR_RXE_FRRD 6, { F_8,D_20,X_12,B_16,0,0 } /* e.g. adb */ +#define INSTR_RXE_FERRD 6, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. lxdb */ +#define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ +#define INSTR_RXE_RRRDU 6, { R_8,D_20,X_12,B_16,U4_32,0 } /* e.g. lcbb */ +#define INSTR_RXE_RERRD 6, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. dsg */ +#define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ +#define INSTR_RXF_FRRDFE 6, { FE_32,F_8,D_20,X_12,B_16,0 } /* e.g. my */ +#define INSTR_RXF_FERRDFE 6, { FE_32,FE_8,D_20,X_12,B_16,0 } /* e.g. slxt */ +#define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ +#define INSTR_RXY_RERRD 6, { RE_8,D20_20,X_12,B_16,0,0 } /* e.g. dsg */ +#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ +#define INSTR_RXY_URRD 6, { U4_8,D20_20,X_12,B_16,0,0 } /* e.g. pfd */ +#define INSTR_RXY_0RRD 6, { D20_20,X_12,B_16,0,0 } /* e.g. bic */ +#define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ +#define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ +#define INSTR_RX_FERRD 4, { FE_8,D_20,X_12,B_16,0,0 } /* e.g. mxd */ +#define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ +#define INSTR_RX_RERRD 4, { RE_8,D_20,X_12,B_16,0,0 } /* e.g. d */ +#define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ +#define INSTR_SI_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. lpsw */ +#define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +#define INSTR_SIY_RD 6, { D20_20,B_16,0,0,0,0 } /* e.g. lpswey*/ +#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ +#define INSTR_SIY_IRD 6, { D20_20,B_16,I8_8,0,0,0 } /* e.g. asi */ +#define INSTR_SIL_RDI 6, { D_20,B_16,I16_32,0,0,0 } /* e.g. chhsi */ +#define INSTR_SIL_RDU 6, { D_20,B_16,U16_32,0,0,0 } /* e.g. clfhsi */ +#define INSTR_SMI_U0RDP 6, { U4_8,J16_32,D_20,B_16,0,0 } /* e.g. bpp */ +#define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvcdk */ +#define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ +#define INSTR_SS_L2RDRD 6, { D_20,B_16,D_36,L8_8,B_32,0 } /* e.g. pka */ +#define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ +#define INSTR_SS_LLRDRD 6, { D_20,L4_8,B_16,D_36,L4_12,B_32 } /* e.g. pack */ +#define INSTR_SS_RRRDRD 6, { D_20,R_8,B_16,D_36,B_32,R_12 } /* e.g. mvck */ +#define INSTR_SS_RRRDRD2 6, { R_8,D_20,B_16,R_12,D_36,B_32 } /* e.g. plo */ +#define INSTR_SS_RRRDRD3 6, { R_8,R_12,D_20,B_16,D_36,B_32 } /* e.g. lmd */ +#define INSTR_SSF_RRDRD 6, { D_20,B_16,D_36,B_32,R_8,0 } /* e.g. mvcos */ +#define INSTR_SSF_RRDRD2 6, { R_8,D_20,B_16,D_36,B_32,0 } /* e.g. cal */ +#define INSTR_SSF_RERDRD2 6, { RE_8,D_20,B_16,D_36,B_32,0 } /* e.g. lpd */ +#define INSTR_S_00 4, { 0,0,0,0,0,0 } /* e.g. hsch */ +#define INSTR_S_RD 4, { D_20,B_16,0,0,0,0 } /* e.g. stck */ +#define INSTR_VRV_VVXRDU 6, { V_8,D_20,VX_12,B_16,U4_32,0 } /* e.g. vgef */ +#define INSTR_VRI_V0U 6, { V_8,U16_16,0,0,0,0 } /* e.g. vgbm */ +#define INSTR_VRI_V 6, { V_8,0,0,0,0,0 } /* e.g. vzero */ +#define INSTR_VRI_V0UUU 6, { V_8,U8_16,U8_24,U4_32,0,0 } /* e.g. vgm */ +#define INSTR_VRI_V0UU 6, { V_8,U8_16,U8_24,0,0,0 } /* e.g. vgmb */ +#define INSTR_VRI_V0UU2 6, { V_8,U16_16,U4_32,0,0,0 } /* e.g. vlip */ +#define INSTR_VRI_VVUU 6, { V_8,V_12,U16_16,U4_32,0,0 } /* e.g. vrep */ +#define INSTR_VRI_VVU 6, { V_8,V_12,U16_16,0,0,0 } /* e.g. vrepb */ +#define INSTR_VRI_VVU2 6, { V_8,V_12,U12_16,0,0,0 } /* e.g. vftcidb */ +#define INSTR_VRI_V0IU 6, { V_8,I16_16,U4_32,0,0,0 } /* e.g. vrepi */ +#define INSTR_VRI_V0I 6, { V_8,I16_16,0,0,0,0 } /* e.g. vrepib */ +#define INSTR_VRI_VVV0UU 6, { V_8,V_12,V_16,U8_24,U4_32,0 } /* e.g. verim */ +#define INSTR_VRI_VVV0UU2 6, { V_8,V_12,V_16,U8_28,U4_24,0 } /* e.g. vap */ +#define INSTR_VRI_VVV0U 6, { V_8,V_12,V_16,U8_24,0,0 } /* e.g. verimb*/ +#define INSTR_VRI_VVUUU 6, { V_8,V_12,U12_16,U4_32,U4_28,0 } /* e.g. vftci */ +#define INSTR_VRI_VVUUU2 6, { V_8,V_12,U8_28,U8_16,U4_24,0 } /* e.g. vpsop */ +#define INSTR_VRI_VR0UU 6, { V_8,R_12,U8_28,U4_24,0,0 } /* e.g. vcvd */ +#define INSTR_VRI_VV0UU 6, { V_8,V_12,U8_28,U4_24,0,0 } /* e.g. vcvdq */ +#define INSTR_VRI_VVV0UV 6, { V_8,V_12,V_16,V_32,U8_24,0 } /* e.g. veval */ +#define INSTR_VRX_VRRD 6, { V_8,D_20,X_12,B_16,0,0 } /* e.g. vl */ +#define INSTR_VRX_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vlr */ +#define INSTR_VRX_VRRDU 6, { V_8,D_20,X_12,B_16,U4_32,0 } /* e.g. vlrep */ +#define INSTR_VRS_RVRDU 6, { R_8,V_12,D_20,B_16,U4_32,0 } /* e.g. vlgv */ +#define INSTR_VRS_RVRD 6, { R_8,V_12,D_20,B_16,0,0 } /* e.g. vlgvb */ +#define INSTR_VRS_VVRDU 6, { V_8,V_12,D_20,B_16,U4_32,0 } /* e.g. verll */ +#define INSTR_VRS_VVRD 6, { V_8,V_12,D_20,B_16,0,0 } /* e.g. vlm */ +#define INSTR_VRS_VRRDU 6, { V_8,R_12,D_20,B_16,U4_32,0 } /* e.g. vlvg */ +#define INSTR_VRS_VRRD 6, { V_8,R_12,D_20,B_16,0,0 } /* e.g. vlvgb */ +#define INSTR_VRS_RRDV 6, { V_32,R_12,D_20,B_16,0,0 } /* e.g. vlrlr */ +#define INSTR_VRR_VRR 6, { V_8,R_12,R_16,0,0,0 } /* e.g. vlvgp */ +#define INSTR_VRR_VVV0U 6, { V_8,V_12,V_16,U4_32,0,0 } /* e.g. vmrh */ +#define INSTR_VRR_VVV0U0 6, { V_8,V_12,V_16,U4_24,0,0 } /* e.g. vfaeb */ +#define INSTR_VRR_VVV0U02 6, { V_8,V_12,V_16,U4_28,0,0 } /* e.g. vd */ +#define INSTR_VRR_VVV0U1 INSTR_VRR_VVV0U0 /* e.g. vfaebs*/ +#define INSTR_VRR_VVV0U2 INSTR_VRR_VVV0U0 /* e.g. vfaezb*/ +#define INSTR_VRR_VVV0U3 INSTR_VRR_VVV0U0 /* e.g. vfaezbs*/ +#define INSTR_VRR_VVV 6, { V_8,V_12,V_16,0,0,0 } /* e.g. vmrhb */ +#define INSTR_VRR_VVV2 6, { V_8,V_CP16_12,0,0,0,0 } /* e.g. vnot */ +#define INSTR_VRR_VV0U 6, { V_8,V_12,U4_32,0,0,0 } /* e.g. vseg */ +#define INSTR_VRR_VV0U2 6, { V_8,V_12,U4_24,0,0,0 } /* e.g. vistrb*/ +#define INSTR_VRR_VV0UU 6, { V_8,V_12,U4_28,U4_24,0,0 } /* e.g. vcdgb */ +#define INSTR_VRR_VV0UU2 6, { V_8,V_12,U4_32,U4_28,0,0 } /* e.g. wfc */ +#define INSTR_VRR_VV0UU8 INSTR_VRR_VV0UU /* e.g. wcdgb */ +#define INSTR_VRR_VV 6, { V_8,V_12,0,0,0,0 } /* e.g. vsegb */ +#define INSTR_VRR_VVVUU0V 6, { V_8,V_12,V_16,V_32,U4_20,U4_24 } /* e.g. vstrc */ +#define INSTR_VRR_VVVU0V 6, { V_8,V_12,V_16,V_32,U4_20,0 } /* e.g. vac */ +#define INSTR_VRR_VVVU0VB 6, { V_8,V_12,V_16,V_32,U4_24,0 } /* e.g. vstrcb*/ +#define INSTR_VRR_VVVU0VB1 INSTR_VRR_VVVU0VB /* e.g. vstrcbs*/ +#define INSTR_VRR_VVVU0VB2 INSTR_VRR_VVVU0VB /* e.g. vstrczb*/ +#define INSTR_VRR_VVVU0VB3 INSTR_VRR_VVVU0VB /* e.g. vstrczbs*/ +#define INSTR_VRR_VVV0V 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vacq */ +#define INSTR_VRR_VVV0U0U 6, { V_8,V_12,V_16,U4_32,U4_24,0 } /* e.g. vfae */ +#define INSTR_VRR_VVVV 6, { V_8,V_12,V_16,V_32,0,0 } /* e.g. vfmadb*/ +#define INSTR_VRR_VVV0UUU 6, { V_8,V_12,V_16,U4_32,U4_28,U4_24 }/* e.g. vfch */ +#define INSTR_VRR_VVV0UU 6, { V_8,V_12,V_16,U4_32,U4_28,0 } /* e.g. vfa */ +#define INSTR_VRR_VV0UUU 6, { V_8,V_12,U4_32,U4_28,U4_24,0 } /* e.g. vcdg */ +#define INSTR_VRR_VVVU0UV 6, { V_8,V_12,V_16,V_32,U4_28,U4_20 } /* e.g. vfma */ +#define INSTR_VRR_VV0U0U 6, { V_8,V_12,U4_32,U4_24,0,0 } /* e.g. vistr */ +#define INSTR_VRR_0V 6, { V_12,0,0,0,0,0 } /* e.g. vtp */ +#define INSTR_VRR_0V0U 6, { V_12,U16_20,0,0,0,0 } /* e.g. vtp */ +#define INSTR_VRR_0VVU 6, { V_12,V_16,U16_20,0,0,0 } /* e.g. vtz */ +#define INSTR_VRR_0VV0U 6, { V_12,V_16,U4_24,0,0,0 } /* e.g. vcp */ +#define INSTR_VRR_RV0U 6, { R_8,V_12,U4_24,0,0,0 } /* e.g. vcvb */ +#define INSTR_VRR_RV0UU 6, { R_8,V_12,U4_24,U4_28,0,0 } /* e.g. vcvb */ +#define INSTR_VSI_URDV 6, { V_32,D_20,B_16,U8_8,0,0 } /* e.g. vlrl */ + +#define MASK_E { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_IE_UU { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_MII_UPP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIE_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRP0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RRI0 { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_RIE_RUPI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RUPU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0PU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_R0IU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0I0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_R0UU { 0xff, 0x0f, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RIE_R0U0 { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_RUI0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RIE_RRUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIE_RRUUU2 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } +#define MASK_RIE_RRUUU3 { 0xff, 0x00, 0x00, 0x80, 0x00, 0xff } +#define MASK_RIE_RRUUU4 { 0xff, 0x00, 0x80, 0x00, 0x00, 0xff } +#define MASK_RIL_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIL_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_0P { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_RU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RI_UP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RIS_RURDI { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDI { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_RURDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RIS_R0RDU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RRE_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_RRE_0R { 0xff, 0xff, 0xff, 0xf0, 0x00, 0x00 } +#define MASK_RRE_AA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_AR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_F0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FE0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_FF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FEF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FEFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_R0 { 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00 } +#define MASK_RRE_RA { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RF { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RFE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_RERE { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRE_FER { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FE0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FF2 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_F0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FE0FER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FEUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FUFF2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FEUFEFE2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_RURR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR2 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR3 { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR4 { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFEFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UFEF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_FFRU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_FEFERU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RER { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_U0RERE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRF_00RR { 0xff, 0xff, 0xff, 0x00, 0x00, 0x00 } +#define MASK_RRF_0URF { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_0UREFE { 0xff, 0xff, 0xf0, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UUFER { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UURF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_UURFE { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_0R { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FEF { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_FEFE { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_R0 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_RER { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_U0 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRR_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRR_FE0FEFE { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } +#define MASK_RRS_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RRS_RRRD0 { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RERERD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_CCRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_R0RD { 0xff, 0x0f, 0x00, 0x00, 0xff, 0xff } +#define MASK_RSL_LRDFU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSL_LRDFEU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RE0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RERERD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_FERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXE_RRRDU { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXE_RERRD { 0xff, 0x00, 0x00, 0x00, 0xff, 0xff } +#define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_FRRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_FERRDFE { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x0f, 0xff } +#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +#define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_FERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_RERRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIY_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIY_IRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_SIL_RDI { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIL_RDU { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SMI_U0RDP { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_L2RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_LLRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SS_RRRDRD3 { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RRDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SSF_RERDRD2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } +#define MASK_S_00 { 0xff, 0xff, 0xff, 0xff, 0x00, 0x00 } +#define MASK_S_RD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_VRV_VVXRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_V0U { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_V { 0xff, 0x0f, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRI_V0UUU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_V0UU { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_V0UU2 { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVU { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_VVU2 { 0xff, 0x00, 0x00, 0x0f, 0xf0, 0xff } +#define MASK_VRI_V0IU { 0xff, 0x0f, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_V0I { 0xff, 0x0f, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRI_VVV0UU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0UU2 { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0U { 0xff, 0x00, 0x0f, 0x00, 0xf0, 0xff } +#define MASK_VRI_VVUUU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VVUUU2 { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRI_VR0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRI_VV0UU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRI_VVV0UV { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRX_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRX_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRX_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_RVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_RVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_VVRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_VVRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_VRRDU { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRS_VRRD { 0xff, 0x00, 0x00, 0x00, 0xf0, 0xff } +#define MASK_VRS_RRDV { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRR_VRR { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVV0U { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } +#define MASK_VRR_VVV0U0 { 0xff, 0x00, 0x0f, 0x0f, 0xf0, 0xff } +#define MASK_VRR_VVV0U02 { 0xff, 0x00, 0x0f, 0xf0, 0xf0, 0xff } +#define MASK_VRR_VVV0U1 { 0xff, 0x00, 0x0f, 0x1f, 0xf0, 0xff } +#define MASK_VRR_VVV0U2 { 0xff, 0x00, 0x0f, 0x2f, 0xf0, 0xff } +#define MASK_VRR_VVV0U3 { 0xff, 0x00, 0x0f, 0x3f, 0xf0, 0xff } +#define MASK_VRR_VVV { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVV2 { 0xff, 0x00, 0x0f, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVV0V { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } +#define MASK_VRR_VV0U { 0xff, 0x00, 0xff, 0xff, 0x00, 0xff } +#define MASK_VRR_VV0U2 { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } +#define MASK_VRR_VV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +#define MASK_VRR_VV0UU2 { 0xff, 0x00, 0xff, 0xf0, 0x00, 0xff } +#define MASK_VRR_VV0UU8 { 0xff, 0x00, 0xff, 0x08, 0xf0, 0xff } +#define MASK_VRR_VV { 0xff, 0x00, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRR_VVVUU0V { 0xff, 0x00, 0x00, 0x0f, 0x00, 0xff } +#define MASK_VRR_VVVU0V { 0xff, 0x00, 0x00, 0xff, 0x00, 0xff } +#define MASK_VRR_VVVU0VB { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } +#define MASK_VRR_VVVU0VB1 { 0xff, 0x00, 0x0f, 0x1f, 0x00, 0xff } +#define MASK_VRR_VVVU0VB2 { 0xff, 0x00, 0x0f, 0x2f, 0x00, 0xff } +#define MASK_VRR_VVVU0VB3 { 0xff, 0x00, 0x0f, 0x3f, 0x00, 0xff } +#define MASK_VRR_VVV0U0U { 0xff, 0x00, 0x0f, 0x0f, 0x00, 0xff } +#define MASK_VRR_VVVV { 0xff, 0x00, 0x0f, 0xff, 0x00, 0xff } +#define MASK_VRR_VVV0UUU { 0xff, 0x00, 0x0f, 0x00, 0x00, 0xff } +#define MASK_VRR_VVV0UU { 0xff, 0x00, 0x0f, 0xf0, 0x00, 0xff } +#define MASK_VRR_VV0UUU { 0xff, 0x00, 0xff, 0x00, 0x00, 0xff } +#define MASK_VRR_VVVU0UV { 0xff, 0x00, 0x00, 0xf0, 0x00, 0xff } +#define MASK_VRR_VV0U0U { 0xff, 0x00, 0xff, 0x0f, 0x00, 0xff } +#define MASK_VRR_0V { 0xff, 0xf0, 0xff, 0xff, 0xf0, 0xff } +#define MASK_VRR_0V0U { 0xff, 0xf0, 0xf0, 0x00, 0x00, 0xff } +#define MASK_VRR_0VVU { 0xff, 0xf0, 0x00, 0x00, 0x00, 0xff } +#define MASK_VRR_0VV0U { 0xff, 0xf0, 0x0f, 0x0f, 0xf0, 0xff } +#define MASK_VRR_RV0U { 0xff, 0x00, 0xff, 0x0f, 0xf0, 0xff } +#define MASK_VRR_RV0UU { 0xff, 0x00, 0xff, 0x00, 0xf0, 0xff } +#define MASK_VSI_URDV { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } + + +/* The opcode formats table (blueprints for .insn pseudo mnemonic). */ + +const struct s390_opcode s390_opformats[] = + { + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0, 256, NULL }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 256, NULL }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0, 256, NULL }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0, 256, NULL }, + { "rilu", OP8(0x00LL), MASK_RIL_RU, INSTR_RIL_RU, 3, 0, 256, NULL }, + { "ris", OP8(0x00LL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 3, 6, 256, NULL }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 256, NULL }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 256, NULL }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 256, NULL }, + { "rrs", OP8(0x00LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 3, 6, 256, NULL }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 256, NULL }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0, 256, NULL }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 256, NULL }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 256, NULL }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 256, NULL }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0, 256, NULL }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR, 3, 0, 256, NULL }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 256, NULL }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0, 256, NULL }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 256, NULL }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3, 256, NULL }, + { "sil", OP8(0x00LL), MASK_SIL_RDI, INSTR_SIL_RDI, 3, 6, 256, NULL }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 256, NULL }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 256, NULL }, + { "ssf", OP8(0x00LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 3, 0, 256, NULL }, + { "vrv", OP8(0x00LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 3, 9, 256, NULL }, + { "vri", OP8(0x00LL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 3, 9, 256, NULL }, + { "vrx", OP8(0x00LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 3, 9, 256, NULL }, + { "vrs", OP8(0x00LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 3, 9, 256, NULL }, + { "vrr", OP8(0x00LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 3, 9, 256, NULL }, + { "vsi", OP8(0x00LL), MASK_VSI_URDV, INSTR_VSI_URDV, 3, 10, 256, NULL }, +}; + +const int s390_num_opformats = + sizeof (s390_opformats) / sizeof (s390_opformats[0]); + +#include "s390-opc.tab" diff --git a/VEX/priv/objdump/s390-opc.tab b/VEX/priv/objdump/s390-opc.tab new file mode 100644 index 000000000..f15035fea --- /dev/null +++ b/VEX/priv/objdump/s390-opc.tab @@ -0,0 +1,2793 @@ +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +/* The opcode table. This file was generated by s390-mkopc. + + The format of the opcode table is: + + NAME OPCODE MASK OPERANDS + + Name is the name of the instruction. + OPCODE is the instruction opcode. + MASK is the opcode mask; this is used to tell the disassembler + which bits in the actual opcode must match OPCODE. + OPERANDS is the list of operands. + + The disassembler reads the table in order and prints the first + instruction which matches. + MODE_BITS - zarch or esa + MIN_CPU - number of the min cpu level required + FLAGS - instruction flags. + DESCRIPTION - description of the instruction. */ + +const struct s390_opcode s390_opcodes[] = + { + { "dp", OP8(0xfdLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "divide decimal" }, + { "mp", OP8(0xfcLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "multiply decimal" }, + { "sp", OP8(0xfbLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "subtract decimal" }, + { "ap", OP8(0xfaLL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "add decimal" }, + { "cp", OP8(0xf9LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "compare decimal" }, + { "zap", OP8(0xf8LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "zero and add" }, + { "unpk", OP8(0xf3LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "unpack" }, + { "pack", OP8(0xf2LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "pack" }, + { "mvo", OP8(0xf1LL), MASK_SS_LLRDRD, INSTR_SS_LLRDRD, 3, 0, 0, "move with offset" }, + { "srp", OP8(0xf0LL), MASK_SS_LIRDRD, INSTR_SS_LIRDRD, 3, 0, 0, "shift and round decimal" }, + { "lmd", OP8(0xefLL), MASK_SS_RRRDRD3, INSTR_SS_RRRDRD3, 2, 2, 0, "load multiple disjoint" }, + { "plo", OP8(0xeeLL), MASK_SS_RRRDRD2, INSTR_SS_RRRDRD2, 3, 0, 0, "perform locked operation" }, + { "cxpt", OP48(0xed00000000afLL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 9, 0, "convert from packed to extended dfp" }, + { "cdpt", OP48(0xed00000000aeLL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 9, 0, "convert from packed to long dfp" }, + { "cpxt", OP48(0xed00000000adLL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 9, 0, "convert from extended dfp to packed" }, + { "cpdt", OP48(0xed00000000acLL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 9, 0, "convert from long dfp to packed" }, + { "cxzt", OP48(0xed00000000abLL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 8, 0, "convert from zoned extended" }, + { "cdzt", OP48(0xed00000000aaLL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 8, 0, "convert from zoned long" }, + { "czxt", OP48(0xed00000000a9LL), MASK_RSL_LRDFEU, INSTR_RSL_LRDFEU, 2, 8, 0, "convert to zoned extended" }, + { "czdt", OP48(0xed00000000a8LL), MASK_RSL_LRDFU, INSTR_RSL_LRDFU, 2, 8, 0, "convert to zoned long" }, + { "stdy", OP48(0xed0000000067LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0, "store (long) with long offset" }, + { "stey", OP48(0xed0000000066LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0, "store (short) with long offset" }, + { "ldy", OP48(0xed0000000065LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0, "load (long) with long offset" }, + { "ley", OP48(0xed0000000064LL), MASK_RXY_FRRD, INSTR_RXY_FRRD, 2, 3, 0, "load (short) with long offset" }, + { "tdgxt", OP48(0xed0000000059LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 2, 5, 0, "test data group extended dfp" }, + { "tdcxt", OP48(0xed0000000058LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 2, 5, 0, "test data class extended dfp" }, + { "tdgdt", OP48(0xed0000000055LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0, "test data group long dfp" }, + { "tdcdt", OP48(0xed0000000054LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0, "test data class long dfp" }, + { "tdget", OP48(0xed0000000051LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0, "test data group short dfp" }, + { "tdcet", OP48(0xed0000000050LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 2, 5, 0, "test data class short dfp" }, + { "srxt", OP48(0xed0000000049LL), MASK_RXF_FERRDFE, INSTR_RXF_FERRDFE, 2, 5, 0, "shift coefficient right extended dfp" }, + { "slxt", OP48(0xed0000000048LL), MASK_RXF_FERRDFE, INSTR_RXF_FERRDFE, 2, 5, 0, "shift coefficient left extended dfp" }, + { "srdt", OP48(0xed0000000041LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5, 0, "shift coefficient right long dfp" }, + { "sldt", OP48(0xed0000000040LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 5, 0, "shift coefficient left long dfp" }, + { "msd", OP48(0xed000000003fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0, "multiply and subtract long hfp" }, + { "mad", OP48(0xed000000003eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0, "multiply and add long hfp" }, + { "myh", OP48(0xed000000003dLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0, "multiply unnormalized long hfp high" }, + { "mayh", OP48(0xed000000003cLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0, "multiply and add unnormalized long hfp high" }, + { "my", OP48(0xed000000003bLL), MASK_RXF_FRRDFE, INSTR_RXF_FRRDFE, 2, 4, 0, "multiply unnormalized long hfp" }, + { "may", OP48(0xed000000003aLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0, "multiply and add unnormalized long hfp" }, + { "myl", OP48(0xed0000000039LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0, "multiply unnormalized long hfp low" }, + { "mayl", OP48(0xed0000000038LL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 2, 4, 0, "multiply and add unnormalized long hfp low" }, + { "mee", OP48(0xed0000000037LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "multiply short hfp" }, + { "sqd", OP48(0xed0000000035LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "square root long hfp" }, + { "sqe", OP48(0xed0000000034LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "square root short hfp" }, + { "mse", OP48(0xed000000002fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0, "multiply and subttract short hfp" }, + { "mae", OP48(0xed000000002eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 3, 0, "multiply and add short hfp" }, + { "lxe", OP48(0xed0000000026LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0, "load lengthened short to extended hfp" }, + { "lxd", OP48(0xed0000000025LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0, "load lengthened long to extended hfp" }, + { "lde", OP48(0xed0000000024LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "load lengthened short to long hfp" }, + { "msdb", OP48(0xed000000001fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0, "multiply and subtract long bfp" }, + { "madb", OP48(0xed000000001eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0, "multiply and add long bfp" }, + { "ddb", OP48(0xed000000001dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "divide long bfp" }, + { "mdb", OP48(0xed000000001cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "multiply long bfp" }, + { "sdb", OP48(0xed000000001bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "subtract long bfp" }, + { "adb", OP48(0xed000000001aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "add long bfp" }, + { "cdb", OP48(0xed0000000019LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "compare long bfp" }, + { "kdb", OP48(0xed0000000018LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "compare and signal long bfp" }, + { "meeb", OP48(0xed0000000017LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "multiply short bfp" }, + { "sqdb", OP48(0xed0000000015LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "square root long bfp" }, + { "sqeb", OP48(0xed0000000014LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "square root short bfp" }, + { "tcxb", OP48(0xed0000000012LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0, "test data class extended bfp" }, + { "tcdb", OP48(0xed0000000011LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "test data class long bfp" }, + { "tceb", OP48(0xed0000000010LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "test data class short bfp" }, + { "mseb", OP48(0xed000000000fLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0, "multiply and subtract short bfp" }, + { "maeb", OP48(0xed000000000eLL), MASK_RXF_FRRDF, INSTR_RXF_FRRDF, 3, 0, 0, "multiply and add short bfp" }, + { "deb", OP48(0xed000000000dLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "divide short bfp" }, + { "mdeb", OP48(0xed000000000cLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "multiply short to long bfp" }, + { "seb", OP48(0xed000000000bLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "subtract short bfp" }, + { "aeb", OP48(0xed000000000aLL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "add short bfp" }, + { "ceb", OP48(0xed0000000009LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "compare short bfp" }, + { "keb", OP48(0xed0000000008LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "compare and signal short bfp" }, + { "mxdb", OP48(0xed0000000007LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0, "multiply long to extended bfp" }, + { "lxeb", OP48(0xed0000000006LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0, "load lengthened short to extended bfp" }, + { "lxdb", OP48(0xed0000000005LL), MASK_RXE_FERRD, INSTR_RXE_FERRD, 3, 0, 0, "load lengthened long to extended bfp" }, + { "ldeb", OP48(0xed0000000004LL), MASK_RXE_FRRD, INSTR_RXE_FRRD, 3, 0, 0, "load lengthened short to long bfp" }, + { "lochhino", OP48(0xec0e0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not overflow / if not ones" }, + { "locghino", OP48(0xec0e00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not overflow / if not ones" }, + { "lochino", OP48(0xec0e00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not overflow / if not ones" }, + { "lochhinh", OP48(0xec0d0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on A not high" }, + { "lochhinp", OP48(0xec0d0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not plus" }, + { "locghinh", OP48(0xec0d00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on A not high" }, + { "locghinp", OP48(0xec0d00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not plus" }, + { "lochinh", OP48(0xec0d00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on A not high" }, + { "lochinp", OP48(0xec0d00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not plus" }, + { "clibnh", OP48(0xec0c000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on A not high" }, + { "clible", OP48(0xec0c000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on low or equal" }, + { "cibnh", OP48(0xec0c000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on A not high" }, + { "cible", OP48(0xec0c000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on low or equal" }, + { "clgibnh", OP48(0xec0c000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on A not high" }, + { "clgible", OP48(0xec0c000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on low or equal" }, + { "cgibnh", OP48(0xec0c000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on A not high" }, + { "cgible", OP48(0xec0c000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on low or equal" }, + { "clijnh", OP48(0xec0c0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on A not high" }, + { "clijle", OP48(0xec0c0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on low or equal" }, + { "cijnh", OP48(0xec0c0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on A not high" }, + { "cijle", OP48(0xec0c0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on low or equal" }, + { "clgijnh", OP48(0xec0c0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on A not high" }, + { "clgijle", OP48(0xec0c0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on low or equal" }, + { "cgijnh", OP48(0xec0c0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on A not high" }, + { "cgijle", OP48(0xec0c0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on low or equal" }, + { "lochhile", OP48(0xec0c0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on low or equal" }, + { "locghile", OP48(0xec0c00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on low or equal" }, + { "lochile", OP48(0xec0c00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on low or equal" }, + { "lochhinl", OP48(0xec0b0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on A not low" }, + { "lochhinm", OP48(0xec0b0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not minus / if not mixed" }, + { "locghinl", OP48(0xec0b00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on A not low" }, + { "locghinm", OP48(0xec0b00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not minus / if not mixed" }, + { "lochinl", OP48(0xec0b00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on A not low" }, + { "lochinm", OP48(0xec0b00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not minus / if not mixed" }, + { "clibnl", OP48(0xec0a000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on A not low" }, + { "clibhe", OP48(0xec0a000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on high or equal" }, + { "cibnl", OP48(0xec0a000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on A not low" }, + { "cibhe", OP48(0xec0a000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on high or equal" }, + { "clgibnl", OP48(0xec0a000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on A not low" }, + { "clgibhe", OP48(0xec0a000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on high or equal" }, + { "cgibnl", OP48(0xec0a000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on A not low" }, + { "cgibhe", OP48(0xec0a000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on high or equal" }, + { "clijnl", OP48(0xec0a0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on A not low" }, + { "clijhe", OP48(0xec0a0000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on high or equal" }, + { "cijnl", OP48(0xec0a0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on A not low" }, + { "cijhe", OP48(0xec0a0000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on high or equal" }, + { "clgijnl", OP48(0xec0a0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on A not low" }, + { "clgijhe", OP48(0xec0a0000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on high or equal" }, + { "cgijnl", OP48(0xec0a0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on A not low" }, + { "cgijhe", OP48(0xec0a0000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on high or equal" }, + { "lochhihe", OP48(0xec0a0000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on high or equal" }, + { "locghihe", OP48(0xec0a00000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on high or equal" }, + { "lochihe", OP48(0xec0a00000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on high or equal" }, + { "lochhinlh", OP48(0xec090000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not low or high" }, + { "locghinlh", OP48(0xec0900000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not low or high" }, + { "lochinlh", OP48(0xec0900000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not low or high" }, + { "clibe", OP48(0xec08000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on A equal B" }, + { "clibnlh", OP48(0xec08000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on not low or high" }, + { "cibe", OP48(0xec08000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on A equal B" }, + { "cibnlh", OP48(0xec08000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on not low or high" }, + { "clgibe", OP48(0xec08000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on A equal B" }, + { "clgibnlh", OP48(0xec08000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on not low or high" }, + { "cgibe", OP48(0xec08000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on A equal B" }, + { "cgibnlh", OP48(0xec08000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on not low or high" }, + { "clije", OP48(0xec080000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on A equal B" }, + { "clijnlh", OP48(0xec080000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on not low or high" }, + { "cije", OP48(0xec080000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on A equal B" }, + { "cijnlh", OP48(0xec080000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on not low or high" }, + { "clgije", OP48(0xec080000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on A equal B" }, + { "clgijnlh", OP48(0xec080000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on not low or high" }, + { "cgije", OP48(0xec080000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on A equal B" }, + { "cgijnlh", OP48(0xec080000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on not low or high" }, + { "lochhie", OP48(0xec080000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on A equal B" }, + { "lochhiz", OP48(0xec080000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on zero / if zeros" }, + { "locghie", OP48(0xec0800000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on A equal B" }, + { "locghiz", OP48(0xec0800000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on zero / if zeros" }, + { "lochie", OP48(0xec0800000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on A equal B" }, + { "lochiz", OP48(0xec0800000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on zero / if zeros" }, + { "lochhine", OP48(0xec070000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on A not equal B" }, + { "lochhinz", OP48(0xec070000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not zero / if not zeros" }, + { "locghine", OP48(0xec0700000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on A not equal B" }, + { "locghinz", OP48(0xec0700000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not zero / if not zeros" }, + { "lochine", OP48(0xec0700000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on A not equal B" }, + { "lochinz", OP48(0xec0700000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not zero / if not zeros" }, + { "clibne", OP48(0xec06000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on A not equal B" }, + { "cliblh", OP48(0xec06000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on low or high" }, + { "cibne", OP48(0xec06000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on A not equal B" }, + { "ciblh", OP48(0xec06000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on low or high" }, + { "clgibne", OP48(0xec06000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on A not equal B" }, + { "clgiblh", OP48(0xec06000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on low or high" }, + { "cgibne", OP48(0xec06000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on A not equal B" }, + { "cgiblh", OP48(0xec06000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on low or high" }, + { "clijne", OP48(0xec060000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on A not equal B" }, + { "clijlh", OP48(0xec060000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on low or high" }, + { "cijne", OP48(0xec060000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on A not equal B" }, + { "cijlh", OP48(0xec060000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on low or high" }, + { "clgijne", OP48(0xec060000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on A not equal B" }, + { "clgijlh", OP48(0xec060000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on low or high" }, + { "cgijne", OP48(0xec060000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on A not equal B" }, + { "cgijlh", OP48(0xec060000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on low or high" }, + { "lochhilh", OP48(0xec060000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on low or high" }, + { "locghilh", OP48(0xec0600000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on low or high" }, + { "lochilh", OP48(0xec0600000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on low or high" }, + { "lochhinhe", OP48(0xec050000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not high or equal" }, + { "locghinhe", OP48(0xec0500000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not high or equal" }, + { "lochinhe", OP48(0xec0500000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not high or equal" }, + { "clibl", OP48(0xec04000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on A low" }, + { "clibnhe", OP48(0xec04000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on not high or equal" }, + { "cibl", OP48(0xec04000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on A low" }, + { "cibnhe", OP48(0xec04000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on not high or equal" }, + { "clgibl", OP48(0xec04000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on A low" }, + { "clgibnhe", OP48(0xec04000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on not high or equal" }, + { "cgibl", OP48(0xec04000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on A low" }, + { "cgibnhe", OP48(0xec04000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on not high or equal" }, + { "clijl", OP48(0xec040000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on A low" }, + { "clijnhe", OP48(0xec040000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on not high or equal" }, + { "cijl", OP48(0xec040000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on A low" }, + { "cijnhe", OP48(0xec040000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on not high or equal" }, + { "clgijl", OP48(0xec040000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on A low" }, + { "clgijnhe", OP48(0xec040000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on not high or equal" }, + { "cgijl", OP48(0xec040000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on A low" }, + { "cgijnhe", OP48(0xec040000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on not high or equal" }, + { "lochhil", OP48(0xec040000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on A low" }, + { "lochhim", OP48(0xec040000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on minus / if mixed" }, + { "locghil", OP48(0xec0400000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on A low" }, + { "locghim", OP48(0xec0400000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on minus / if mixed" }, + { "lochil", OP48(0xec0400000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on A low" }, + { "lochim", OP48(0xec0400000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on minus / if mixed" }, + { "lochhinle", OP48(0xec030000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on not low or equal" }, + { "locghinle", OP48(0xec0300000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on not low or equal" }, + { "lochinle", OP48(0xec0300000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on not low or equal" }, + { "clibh", OP48(0xec02000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on A high" }, + { "clibnle", OP48(0xec02000000ffLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (32<8) on not low or equal" }, + { "cibh", OP48(0xec02000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on A high" }, + { "cibnle", OP48(0xec02000000feLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (32<8) on not low or equal" }, + { "clgibh", OP48(0xec02000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on A high" }, + { "clgibnle", OP48(0xec02000000fdLL), MASK_RIS_R0RDU, INSTR_RIS_R0RDU, 2, 6, 0, "compare logical immediate and branch (64<8) on not low or equal" }, + { "cgibh", OP48(0xec02000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on A high" }, + { "cgibnle", OP48(0xec02000000fcLL), MASK_RIS_R0RDI, INSTR_RIS_R0RDI, 2, 6, 0, "compare immediate and branch (64<8) on not low or equal" }, + { "clijh", OP48(0xec020000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on A high" }, + { "clijnle", OP48(0xec020000007fLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (32<8) on not low or equal" }, + { "cijh", OP48(0xec020000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on A high" }, + { "cijnle", OP48(0xec020000007eLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (32<8) on not low or equal" }, + { "clgijh", OP48(0xec020000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on A high" }, + { "clgijnle", OP48(0xec020000007dLL), MASK_RIE_R0PU, INSTR_RIE_R0PU, 2, 6, 112, "compare logical immediate and branch relative (64<8) on not low or equal" }, + { "cgijh", OP48(0xec020000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on A high" }, + { "cgijnle", OP48(0xec020000007cLL), MASK_RIE_R0PI, INSTR_RIE_R0PI, 2, 6, 112, "compare immediate and branch relative (64<8) on not low or equal" }, + { "lochhih", OP48(0xec020000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on A high" }, + { "lochhip", OP48(0xec020000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on plus" }, + { "locghih", OP48(0xec0200000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on A high" }, + { "locghip", OP48(0xec0200000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on plus" }, + { "lochih", OP48(0xec0200000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on A high" }, + { "lochip", OP48(0xec0200000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on plus" }, + { "lochhio", OP48(0xec010000004eLL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword high immediate on condition on overflow / if ones" }, + { "locghio", OP48(0xec0100000046LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr on overflow / if ones" }, + { "lochio", OP48(0xec0100000042LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr on overflow / if ones" }, + { "rxsbgt", OP48(0xec0080000057LL), MASK_RIE_RRUUU4, INSTR_RIE_RRUUU4, 2, 6, 1, "rotate then exclusive or selected bits and test results" }, + { "rosbgt", OP48(0xec0080000056LL), MASK_RIE_RRUUU4, INSTR_RIE_RRUUU4, 2, 6, 1, "rotate then or selected bits and test results" }, + { "rnsbgt", OP48(0xec0080000054LL), MASK_RIE_RRUUU4, INSTR_RIE_RRUUU4, 2, 6, 1, "rotate then and selected bits and test results" }, + { "risbhgz", OP48(0xec000080005dLL), MASK_RIE_RRUUU3, INSTR_RIE_RRUUU3, 2, 7, 1, "rotate then insert selected bits high and zero remaining bits" }, + { "risbgnz", OP48(0xec0000800059LL), MASK_RIE_RRUUU2, INSTR_RIE_RRUUU2, 2, 8, 1, "rotate then insert selected bits and zero remaining bits nocc" }, + { "risbgz", OP48(0xec0000800055LL), MASK_RIE_RRUUU2, INSTR_RIE_RRUUU2, 2, 6, 1, "rotate then insert selected bits and zero remaining bits" }, + { "risblgz", OP48(0xec0000800051LL), MASK_RIE_RRUUU3, INSTR_RIE_RRUUU3, 2, 7, 1, "rotate then insert selected bits low and zero remaining bits" }, + { "clrbnh", OP48(0xec000000c0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on A not high" }, + { "clrble", OP48(0xec000000c0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on low or equal" }, + { "crbnh", OP48(0xec000000c0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on A not high" }, + { "crble", OP48(0xec000000c0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on low or equal" }, + { "clgrbnh", OP48(0xec000000c0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on A not high" }, + { "clgrble", OP48(0xec000000c0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on low or equal" }, + { "cgrbnh", OP48(0xec000000c0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on A not high" }, + { "cgrble", OP48(0xec000000c0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on low or equal" }, + { "clrjnh", OP48(0xec000000c077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on A not high" }, + { "clrjle", OP48(0xec000000c077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on low or equal" }, + { "crjnh", OP48(0xec000000c076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on A not high" }, + { "crjle", OP48(0xec000000c076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on low or equal" }, + { "clfitnh", OP48(0xec000000c073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on A not high" }, + { "clfitle", OP48(0xec000000c073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on low or equal" }, + { "citnh", OP48(0xec000000c072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on A not high" }, + { "citle", OP48(0xec000000c072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on low or equal" }, + { "clgitnh", OP48(0xec000000c071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on A not high" }, + { "clgitle", OP48(0xec000000c071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on low or equal" }, + { "cgitnh", OP48(0xec000000c070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on A not high" }, + { "cgitle", OP48(0xec000000c070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on low or equal" }, + { "clgrjnh", OP48(0xec000000c065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on A not high" }, + { "clgrjle", OP48(0xec000000c065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on low or equal" }, + { "cgrjnh", OP48(0xec000000c064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on A not high" }, + { "cgrjle", OP48(0xec000000c064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on low or equal" }, + { "clrbnl", OP48(0xec000000a0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on A not low" }, + { "clrbhe", OP48(0xec000000a0f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on high or equal" }, + { "crbnl", OP48(0xec000000a0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on A not low" }, + { "crbhe", OP48(0xec000000a0f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on high or equal" }, + { "clgrbnl", OP48(0xec000000a0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on A not low" }, + { "clgrbhe", OP48(0xec000000a0e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on high or equal" }, + { "cgrbnl", OP48(0xec000000a0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on A not low" }, + { "cgrbhe", OP48(0xec000000a0e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on high or equal" }, + { "clrjnl", OP48(0xec000000a077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on A not low" }, + { "clrjhe", OP48(0xec000000a077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on high or equal" }, + { "crjnl", OP48(0xec000000a076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on A not low" }, + { "crjhe", OP48(0xec000000a076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on high or equal" }, + { "clfitnl", OP48(0xec000000a073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on A not low" }, + { "clfithe", OP48(0xec000000a073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on high or equal" }, + { "citnl", OP48(0xec000000a072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on A not low" }, + { "cithe", OP48(0xec000000a072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on high or equal" }, + { "clgitnl", OP48(0xec000000a071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on A not low" }, + { "clgithe", OP48(0xec000000a071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on high or equal" }, + { "cgitnl", OP48(0xec000000a070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on A not low" }, + { "cgithe", OP48(0xec000000a070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on high or equal" }, + { "clgrjnl", OP48(0xec000000a065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on A not low" }, + { "clgrjhe", OP48(0xec000000a065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on high or equal" }, + { "cgrjnl", OP48(0xec000000a064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on A not low" }, + { "cgrjhe", OP48(0xec000000a064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on high or equal" }, + { "clrbe", OP48(0xec00000080f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on A equal B" }, + { "clrbnlh", OP48(0xec00000080f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on not low or high" }, + { "crbe", OP48(0xec00000080f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on A equal B" }, + { "crbnlh", OP48(0xec00000080f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on not low or high" }, + { "clgrbe", OP48(0xec00000080e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on A equal B" }, + { "clgrbnlh", OP48(0xec00000080e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on not low or high" }, + { "cgrbe", OP48(0xec00000080e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on A equal B" }, + { "cgrbnlh", OP48(0xec00000080e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on not low or high" }, + { "clrje", OP48(0xec0000008077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on A equal B" }, + { "clrjnlh", OP48(0xec0000008077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on not low or high" }, + { "crje", OP48(0xec0000008076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on A equal B" }, + { "crjnlh", OP48(0xec0000008076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on not low or high" }, + { "clfite", OP48(0xec0000008073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on A equal B" }, + { "clfitnlh", OP48(0xec0000008073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on not low or high" }, + { "cite", OP48(0xec0000008072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on A equal B" }, + { "citnlh", OP48(0xec0000008072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on not low or high" }, + { "clgite", OP48(0xec0000008071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on A equal B" }, + { "clgitnlh", OP48(0xec0000008071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on not low or high" }, + { "cgite", OP48(0xec0000008070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on A equal B" }, + { "cgitnlh", OP48(0xec0000008070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on not low or high" }, + { "clgrje", OP48(0xec0000008065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on A equal B" }, + { "clgrjnlh", OP48(0xec0000008065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on not low or high" }, + { "cgrje", OP48(0xec0000008064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on A equal B" }, + { "cgrjnlh", OP48(0xec0000008064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on not low or high" }, + { "clrbne", OP48(0xec00000060f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on A not equal B" }, + { "clrblh", OP48(0xec00000060f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on low or high" }, + { "crbne", OP48(0xec00000060f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on A not equal B" }, + { "crblh", OP48(0xec00000060f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on low or high" }, + { "clgrbne", OP48(0xec00000060e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on A not equal B" }, + { "clgrblh", OP48(0xec00000060e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on low or high" }, + { "cgrbne", OP48(0xec00000060e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on A not equal B" }, + { "cgrblh", OP48(0xec00000060e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on low or high" }, + { "clrjne", OP48(0xec0000006077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on A not equal B" }, + { "clrjlh", OP48(0xec0000006077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on low or high" }, + { "crjne", OP48(0xec0000006076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on A not equal B" }, + { "crjlh", OP48(0xec0000006076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on low or high" }, + { "clfitne", OP48(0xec0000006073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on A not equal B" }, + { "clfitlh", OP48(0xec0000006073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on low or high" }, + { "citne", OP48(0xec0000006072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on A not equal B" }, + { "citlh", OP48(0xec0000006072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on low or high" }, + { "clgitne", OP48(0xec0000006071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on A not equal B" }, + { "clgitlh", OP48(0xec0000006071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on low or high" }, + { "cgitne", OP48(0xec0000006070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on A not equal B" }, + { "cgitlh", OP48(0xec0000006070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on low or high" }, + { "clgrjne", OP48(0xec0000006065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on A not equal B" }, + { "clgrjlh", OP48(0xec0000006065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on low or high" }, + { "cgrjne", OP48(0xec0000006064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on A not equal B" }, + { "cgrjlh", OP48(0xec0000006064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on low or high" }, + { "clrbl", OP48(0xec00000040f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on A low" }, + { "clrbnhe", OP48(0xec00000040f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on not high or equal" }, + { "crbl", OP48(0xec00000040f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on A low" }, + { "crbnhe", OP48(0xec00000040f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on not high or equal" }, + { "clgrbl", OP48(0xec00000040e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on A low" }, + { "clgrbnhe", OP48(0xec00000040e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on not high or equal" }, + { "cgrbl", OP48(0xec00000040e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on A low" }, + { "cgrbnhe", OP48(0xec00000040e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on not high or equal" }, + { "clrjl", OP48(0xec0000004077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on A low" }, + { "clrjnhe", OP48(0xec0000004077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on not high or equal" }, + { "crjl", OP48(0xec0000004076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on A low" }, + { "crjnhe", OP48(0xec0000004076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on not high or equal" }, + { "clfitl", OP48(0xec0000004073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on A low" }, + { "clfitnhe", OP48(0xec0000004073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on not high or equal" }, + { "citl", OP48(0xec0000004072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on A low" }, + { "citnhe", OP48(0xec0000004072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on not high or equal" }, + { "clgitl", OP48(0xec0000004071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on A low" }, + { "clgitnhe", OP48(0xec0000004071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on not high or equal" }, + { "cgitl", OP48(0xec0000004070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on A low" }, + { "cgitnhe", OP48(0xec0000004070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on not high or equal" }, + { "clgrjl", OP48(0xec0000004065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on A low" }, + { "clgrjnhe", OP48(0xec0000004065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on not high or equal" }, + { "cgrjl", OP48(0xec0000004064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on A low" }, + { "cgrjnhe", OP48(0xec0000004064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on not high or equal" }, + { "clrbh", OP48(0xec00000020f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on A high" }, + { "clrbnle", OP48(0xec00000020f7LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (32) on not low or equal" }, + { "crbh", OP48(0xec00000020f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on A high" }, + { "crbnle", OP48(0xec00000020f6LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (32) on not low or equal" }, + { "clgrbh", OP48(0xec00000020e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on A high" }, + { "clgrbnle", OP48(0xec00000020e5LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare logical and branch (64) on not low or equal" }, + { "cgrbh", OP48(0xec00000020e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on A high" }, + { "cgrbnle", OP48(0xec00000020e4LL), MASK_RRS_RRRD0, INSTR_RRS_RRRD0, 2, 6, 0, "compare and branch (64) on not low or equal" }, + { "clrjh", OP48(0xec0000002077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on A high" }, + { "clrjnle", OP48(0xec0000002077LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (32) on not low or equal" }, + { "crjh", OP48(0xec0000002076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on A high" }, + { "crjnle", OP48(0xec0000002076LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (32) on not low or equal" }, + { "clfith", OP48(0xec0000002073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on A high" }, + { "clfitnle", OP48(0xec0000002073LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (32<16) on not low or equal" }, + { "cith", OP48(0xec0000002072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on A high" }, + { "citnle", OP48(0xec0000002072LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (32<16) on not low or equal" }, + { "clgith", OP48(0xec0000002071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on A high" }, + { "clgitnle", OP48(0xec0000002071LL), MASK_RIE_R0U0, INSTR_RIE_R0U0, 2, 6, 0, "compare logical and trap (64<16) on not low or equal" }, + { "cgith", OP48(0xec0000002070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on A high" }, + { "cgitnle", OP48(0xec0000002070LL), MASK_RIE_R0I0, INSTR_RIE_R0I0, 2, 6, 0, "compare immediate and trap (64<16) on not low or equal" }, + { "clgrjh", OP48(0xec0000002065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on A high" }, + { "clgrjnle", OP48(0xec0000002065LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare logical and branch relative (64) on not low or equal" }, + { "cgrjh", OP48(0xec0000002064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on A high" }, + { "cgrjnle", OP48(0xec0000002064LL), MASK_RIE_RRP0, INSTR_RIE_RRP0, 2, 6, 112, "compare and branch relative (64) on not low or equal" }, + { "clib", OP48(0xec00000000ffLL), MASK_RIS_RURDU, INSTR_RIS_RURDU, 2, 6, 0, "compare logical immediate and branch (32<8)" }, + { "cib", OP48(0xec00000000feLL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 2, 6, 0, "compare immediate and branch (32<8)" }, + { "clgib", OP48(0xec00000000fdLL), MASK_RIS_RURDU, INSTR_RIS_RURDU, 2, 6, 0, "compare logical immediate and branch (64<8)" }, + { "cgib", OP48(0xec00000000fcLL), MASK_RIS_RURDI, INSTR_RIS_RURDI, 2, 6, 0, "compare immediate and branch (64<8)" }, + { "clrb", OP48(0xec00000000f7LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0, "compare logical and branch (32)" }, + { "crb", OP48(0xec00000000f6LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0, "compare and branch (32)" }, + { "clgrb", OP48(0xec00000000e5LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0, "compare logical and branch (64)" }, + { "cgrb", OP48(0xec00000000e4LL), MASK_RRS_RRRDU, INSTR_RRS_RRRDU, 2, 6, 0, "compare and branch (64)" }, + { "alghsik", OP48(0xec00000000dbLL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0, "add logical immediate 3 operands 64 bit" }, + { "alhsik", OP48(0xec00000000daLL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0, "add logical immediate 3 operands 32 bit" }, + { "aghik", OP48(0xec00000000d9LL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0, "add immediate 3 operands 64 bit" }, + { "ahik", OP48(0xec00000000d8LL), MASK_RIE_RRI0, INSTR_RIE_RRI0, 2, 7, 0, "add immediate 3 operands 32 bit" }, + { "clij", OP48(0xec000000007fLL), MASK_RIE_RUPU, INSTR_RIE_RUPU, 2, 6, 112, "compare logical immediate and branch relative (32<8)" }, + { "cij", OP48(0xec000000007eLL), MASK_RIE_RUPI, INSTR_RIE_RUPI, 2, 6, 112, "compare immediate and branch relative (32<8)" }, + { "clgij", OP48(0xec000000007dLL), MASK_RIE_RUPU, INSTR_RIE_RUPU, 2, 6, 112, "compare logical immediate and branch relative (64<8)" }, + { "cgij", OP48(0xec000000007cLL), MASK_RIE_RUPI, INSTR_RIE_RUPI, 2, 6, 112, "compare immediate and branch relative (64<8)" }, + { "clrj", OP48(0xec0000000077LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 112, "compare logical and branch relative (32)" }, + { "crj", OP48(0xec0000000076LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 112, "compare and branch relative (32)" }, + { "clfit", OP48(0xec0000000073LL), MASK_RIE_R0UU, INSTR_RIE_R0UU, 2, 6, 0, "compare logical and trap (32<16)" }, + { "cit", OP48(0xec0000000072LL), MASK_RIE_R0IU, INSTR_RIE_R0IU, 2, 6, 0, "compare immediate and trap (32<16)" }, + { "clgit", OP48(0xec0000000071LL), MASK_RIE_R0UU, INSTR_RIE_R0UU, 2, 6, 0, "compare logical and trap (64<16)" }, + { "cgit", OP48(0xec0000000070LL), MASK_RIE_R0IU, INSTR_RIE_R0IU, 2, 6, 0, "compare immediate and trap (64<16)" }, + { "clgrj", OP48(0xec0000000065LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 112, "compare logical and branch relative (64)" }, + { "cgrj", OP48(0xec0000000064LL), MASK_RIE_RRPU, INSTR_RIE_RRPU, 2, 6, 112, "compare and branch relative (64)" }, + { "risbhg", OP48(0xec000000005dLL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 7, 1, "rotate then insert selected bits high" }, + { "risbgn", OP48(0xec0000000059LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 8, 1, "rotate then insert selected bits nocc" }, + { "rxsbg", OP48(0xec0000000057LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 1, "rotate then exclusive or selected bits" }, + { "rosbg", OP48(0xec0000000056LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 1, "rotate then or selected bits" }, + { "risbg", OP48(0xec0000000055LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 1, "rotate then insert selected bits" }, + { "rnsbg", OP48(0xec0000000054LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 6, 1, "rotate then and selected bits" }, + { "risblg", OP48(0xec0000000051LL), MASK_RIE_RRUUU, INSTR_RIE_RRUUU, 2, 7, 1, "rotate then insert selected bits low" }, + { "lochhi", OP48(0xec000000004eLL), MASK_RIE_RUI0, INSTR_RIE_RUI0, 2, 9, 0, "load halfword high immediate on condition" }, + { "locghi", OP48(0xec0000000046LL), MASK_RIE_RUI0, INSTR_RIE_RUI0, 2, 9, 0, "load halfword immediate on condition into 64 bit gpr" }, + { "brxlg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 112, "branch relative on index low or equal 64" }, + { "jxleg", OP48(0xec0000000045LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 112, "branch relative on index low or equal 64" }, + { "brxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 112, "branch relative on index high 64" }, + { "jxhg", OP48(0xec0000000044LL), MASK_RIE_RRP, INSTR_RIE_RRP, 2, 2, 112, "branch relative on index high 64" }, + { "lochi", OP48(0xec0000000042LL), MASK_RIE_RUI0, INSTR_RIE_RUI0, 2, 9, 0, "load halfword immediate on condition into 32 bit gpr" }, + { "stocno", OP48(0xeb0e000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not overflow / if not ones" }, + { "locno", OP48(0xeb0e000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not overflow / if not ones" }, + { "stocgno", OP48(0xeb0e000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not overflow / if not ones" }, + { "locgno", OP48(0xeb0e000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not overflow / if not ones" }, + { "stocfhno", OP48(0xeb0e000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not overflow / if not ones" }, + { "locfhno", OP48(0xeb0e000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not overflow / if not ones" }, + { "stocnh", OP48(0xeb0d000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on A not high" }, + { "stocnp", OP48(0xeb0d000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not plus" }, + { "locnh", OP48(0xeb0d000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on A not high" }, + { "locnp", OP48(0xeb0d000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not plus" }, + { "stocgnh", OP48(0xeb0d000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on A not high" }, + { "stocgnp", OP48(0xeb0d000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not plus" }, + { "locgnh", OP48(0xeb0d000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on A not high" }, + { "locgnp", OP48(0xeb0d000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not plus" }, + { "stocfhnh", OP48(0xeb0d000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on A not high" }, + { "stocfhnp", OP48(0xeb0d000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not plus" }, + { "locfhnh", OP48(0xeb0d000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on A not high" }, + { "locfhnp", OP48(0xeb0d000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not plus" }, + { "stocle", OP48(0xeb0c000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on low or equal" }, + { "locle", OP48(0xeb0c000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on low or equal" }, + { "stocgle", OP48(0xeb0c000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on low or equal" }, + { "locgle", OP48(0xeb0c000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on low or equal" }, + { "stocfhle", OP48(0xeb0c000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on low or equal" }, + { "locfhle", OP48(0xeb0c000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on low or equal" }, + { "clgtnh", OP48(0xeb0c0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on A not high" }, + { "clgtle", OP48(0xeb0c0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on low or equal" }, + { "cltnh", OP48(0xeb0c00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on A not high" }, + { "cltle", OP48(0xeb0c00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on low or equal" }, + { "stocnl", OP48(0xeb0b000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on A not low" }, + { "stocnm", OP48(0xeb0b000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not minus / if not mixed" }, + { "locnl", OP48(0xeb0b000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on A not low" }, + { "locnm", OP48(0xeb0b000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not minus / if not mixed" }, + { "stocgnl", OP48(0xeb0b000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on A not low" }, + { "stocgnm", OP48(0xeb0b000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not minus / if not mixed" }, + { "locgnl", OP48(0xeb0b000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on A not low" }, + { "locgnm", OP48(0xeb0b000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not minus / if not mixed" }, + { "stocfhnl", OP48(0xeb0b000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on A not low" }, + { "stocfhnm", OP48(0xeb0b000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not minus / if not mixed" }, + { "locfhnl", OP48(0xeb0b000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on A not low" }, + { "locfhnm", OP48(0xeb0b000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not minus / if not mixed" }, + { "stoche", OP48(0xeb0a000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on high or equal" }, + { "loche", OP48(0xeb0a000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on high or equal" }, + { "stocghe", OP48(0xeb0a000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on high or equal" }, + { "locghe", OP48(0xeb0a000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on high or equal" }, + { "stocfhhe", OP48(0xeb0a000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on high or equal" }, + { "locfhhe", OP48(0xeb0a000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on high or equal" }, + { "clgtnl", OP48(0xeb0a0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on A not low" }, + { "clgthe", OP48(0xeb0a0000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on high or equal" }, + { "cltnl", OP48(0xeb0a00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on A not low" }, + { "clthe", OP48(0xeb0a00000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on high or equal" }, + { "stocnlh", OP48(0xeb09000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not low or high" }, + { "locnlh", OP48(0xeb09000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not low or high" }, + { "stocgnlh", OP48(0xeb09000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not low or high" }, + { "locgnlh", OP48(0xeb09000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not low or high" }, + { "stocfhnlh", OP48(0xeb09000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not low or high" }, + { "locfhnlh", OP48(0xeb09000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not low or high" }, + { "stoce", OP48(0xeb08000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on A equal B" }, + { "stocz", OP48(0xeb08000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on zero / if zeros" }, + { "loce", OP48(0xeb08000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on A equal B" }, + { "locz", OP48(0xeb08000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on zero / if zeros" }, + { "stocge", OP48(0xeb08000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on A equal B" }, + { "stocgz", OP48(0xeb08000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on zero / if zeros" }, + { "locge", OP48(0xeb08000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on A equal B" }, + { "locgz", OP48(0xeb08000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on zero / if zeros" }, + { "stocfhe", OP48(0xeb08000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on A equal B" }, + { "stocfhz", OP48(0xeb08000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on zero / if zeros" }, + { "locfhe", OP48(0xeb08000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on A equal B" }, + { "locfhz", OP48(0xeb08000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on zero / if zeros" }, + { "clgte", OP48(0xeb080000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on A equal B" }, + { "clgtnlh", OP48(0xeb080000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on not low or high" }, + { "clte", OP48(0xeb0800000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on A equal B" }, + { "cltnlh", OP48(0xeb0800000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on not low or high" }, + { "stocne", OP48(0xeb07000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on A not equal B" }, + { "stocnz", OP48(0xeb07000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not zero / if not zeros" }, + { "locne", OP48(0xeb07000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on A not equal B" }, + { "locnz", OP48(0xeb07000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not zero / if not zeros" }, + { "stocgne", OP48(0xeb07000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on A not equal B" }, + { "stocgnz", OP48(0xeb07000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not zero / if not zeros" }, + { "locgne", OP48(0xeb07000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on A not equal B" }, + { "locgnz", OP48(0xeb07000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not zero / if not zeros" }, + { "stocfhne", OP48(0xeb07000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on A not equal B" }, + { "stocfhnz", OP48(0xeb07000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not zero / if not zeros" }, + { "locfhne", OP48(0xeb07000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on A not equal B" }, + { "locfhnz", OP48(0xeb07000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not zero / if not zeros" }, + { "stoclh", OP48(0xeb06000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on low or high" }, + { "loclh", OP48(0xeb06000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on low or high" }, + { "stocglh", OP48(0xeb06000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on low or high" }, + { "locglh", OP48(0xeb06000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on low or high" }, + { "stocfhlh", OP48(0xeb06000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on low or high" }, + { "locfhlh", OP48(0xeb06000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on low or high" }, + { "clgtne", OP48(0xeb060000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on A not equal B" }, + { "clgtlh", OP48(0xeb060000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on low or high" }, + { "cltne", OP48(0xeb0600000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on A not equal B" }, + { "cltlh", OP48(0xeb0600000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on low or high" }, + { "stocnhe", OP48(0xeb05000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not high or equal" }, + { "locnhe", OP48(0xeb05000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not high or equal" }, + { "stocgnhe", OP48(0xeb05000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not high or equal" }, + { "locgnhe", OP48(0xeb05000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not high or equal" }, + { "stocfhnhe", OP48(0xeb05000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not high or equal" }, + { "locfhnhe", OP48(0xeb05000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not high or equal" }, + { "stocl", OP48(0xeb04000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on A low" }, + { "stocm", OP48(0xeb04000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on minus / if mixed" }, + { "locl", OP48(0xeb04000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on A low" }, + { "locm", OP48(0xeb04000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on minus / if mixed" }, + { "stocgl", OP48(0xeb04000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on A low" }, + { "stocgm", OP48(0xeb04000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on minus / if mixed" }, + { "locgl", OP48(0xeb04000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on A low" }, + { "locgm", OP48(0xeb04000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on minus / if mixed" }, + { "stocfhl", OP48(0xeb04000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on A low" }, + { "stocfhm", OP48(0xeb04000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on minus / if mixed" }, + { "locfhl", OP48(0xeb04000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on A low" }, + { "locfhm", OP48(0xeb04000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on minus / if mixed" }, + { "clgtl", OP48(0xeb040000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on A low" }, + { "clgtnhe", OP48(0xeb040000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on not high or equal" }, + { "cltl", OP48(0xeb0400000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on A low" }, + { "cltnhe", OP48(0xeb0400000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on not high or equal" }, + { "stocnle", OP48(0xeb03000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on not low or equal" }, + { "locnle", OP48(0xeb03000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on not low or equal" }, + { "stocgnle", OP48(0xeb03000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on not low or equal" }, + { "locgnle", OP48(0xeb03000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on not low or equal" }, + { "stocfhnle", OP48(0xeb03000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on not low or equal" }, + { "locfhnle", OP48(0xeb03000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on not low or equal" }, + { "stoch", OP48(0xeb02000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on A high" }, + { "stocp", OP48(0xeb02000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on plus" }, + { "loch", OP48(0xeb02000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on A high" }, + { "locp", OP48(0xeb02000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on plus" }, + { "stocgh", OP48(0xeb02000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on A high" }, + { "stocgp", OP48(0xeb02000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on plus" }, + { "locgh", OP48(0xeb02000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on A high" }, + { "locgp", OP48(0xeb02000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on plus" }, + { "stocfhh", OP48(0xeb02000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on A high" }, + { "stocfhp", OP48(0xeb02000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on plus" }, + { "locfhh", OP48(0xeb02000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on A high" }, + { "locfhp", OP48(0xeb02000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on plus" }, + { "clgth", OP48(0xeb020000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on A high" }, + { "clgtnle", OP48(0xeb020000002bLL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 64 bit reg-mem on not low or equal" }, + { "clth", OP48(0xeb0200000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on A high" }, + { "cltnle", OP48(0xeb0200000023LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 8, 0, "compare logical and trap 32 bit reg-mem on not low or equal" }, + { "stoco", OP48(0xeb01000000f3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 32 bit on overflow / if ones" }, + { "loco", OP48(0xeb01000000f2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 32 bit on overflow / if ones" }, + { "stocgo", OP48(0xeb01000000e3LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "store on condition 64 bit on overflow / if ones" }, + { "locgo", OP48(0xeb01000000e2LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 7, 0, "load on condition 64 bit on overflow / if ones" }, + { "stocfho", OP48(0xeb01000000e1LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "store high on condition on overflow / if ones" }, + { "locfho", OP48(0xeb01000000e0LL), MASK_RSY_R0RD, INSTR_RSY_R0RD, 2, 9, 0, "load high on condition from memory on overflow / if ones" }, + { "laal", OP48(0xeb00000000faLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and add logical 32 bit" }, + { "laa", OP48(0xeb00000000f8LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and add 32 bit" }, + { "lax", OP48(0xeb00000000f7LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and exclusive or 32 bit" }, + { "lao", OP48(0xeb00000000f6LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and or 32 bit" }, + { "lan", OP48(0xeb00000000f4LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and and 32 bit" }, + { "stoc", OP48(0xeb00000000f3LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0, "store on condition 32 bit" }, + { "loc", OP48(0xeb00000000f2LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0, "load on condition 32 bit" }, + { "laalg", OP48(0xeb00000000eaLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and add logical 64 bit" }, + { "laag", OP48(0xeb00000000e8LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and add 64 bit" }, + { "laxg", OP48(0xeb00000000e7LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and exclusive or 64 bit" }, + { "laog", OP48(0xeb00000000e6LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and or 64 bit" }, + { "lang", OP48(0xeb00000000e4LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "load and and 64 bit" }, + { "stocg", OP48(0xeb00000000e3LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0, "store on condition 64 bit" }, + { "locg", OP48(0xeb00000000e2LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 7, 0, "load on condition 64 bit" }, + { "stocfh", OP48(0xeb00000000e1LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 9, 0, "store high on condition" }, + { "locfh", OP48(0xeb00000000e0LL), MASK_RSY_RURD2, INSTR_RSY_RURD2, 2, 9, 0, "load high on condition from memory" }, + { "sllk", OP48(0xeb00000000dfLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "shift left single logical 3 operands 32 bit" }, + { "srlk", OP48(0xeb00000000deLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "shift right single logical 3 operands 32 bit" }, + { "slak", OP48(0xeb00000000ddLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "shift left single 3 operands 32 bit" }, + { "srak", OP48(0xeb00000000dcLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 7, 0, "shift right single 3 operands 32 bit" }, + { "tp", OP48(0xeb00000000c0LL), MASK_RSL_R0RD, INSTR_RSL_R0RD, 3, 0, 0, "test decimal" }, + { "stamy", OP48(0xeb000000009bLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3, 0, "store access multiple with long offset" }, + { "lamy", OP48(0xeb000000009aLL), MASK_RSY_AARD, INSTR_RSY_AARD, 2, 3, 0, "load access multiple" }, + { "lmy", OP48(0xeb0000000098LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "load multiple with long offset" }, + { "lmh", OP48(0xeb0000000096LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "load multiple high" }, + { "lmh", OP48(0xeb0000000096LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "load multiple high" }, + { "stmy", OP48(0xeb0000000090LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "store multiple with long offset" }, + { "clclu", OP48(0xeb000000008fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0, "compare logical long unicode with long offset" }, + { "mvclu", OP48(0xeb000000008eLL), MASK_RSY_RERERD, INSTR_RSY_RERERD, 3, 3, 0, "move long unicode" }, + { "mvclu", OP48(0xeb000000008eLL), MASK_RSE_RERERD, INSTR_RSE_RERERD, 3, 0, 0, "move long unicode" }, + { "icmy", OP48(0xeb0000000081LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0, "insert characters with long offset" }, + { "icmh", OP48(0xeb0000000080LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0, "insert characters under mask high with long offset" }, + { "icmh", OP48(0xeb0000000080LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2, 0, "insert characters under mask high" }, + { "algsi", OP48(0xeb000000007eLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0, "add logical with signed immediate (64<8)" }, + { "agsi", OP48(0xeb000000007aLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0, "add immediate (64<8)" }, + { "lpswey", OP48(0xeb0000000071LL), MASK_SIY_RD, INSTR_SIY_RD, 2, 12, 0, "load PSW extended" }, + { "alsi", OP48(0xeb000000006eLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0, "add logical with signed immediate (32<8)" }, + { "asi", OP48(0xeb000000006aLL), MASK_SIY_IRD, INSTR_SIY_IRD, 2, 6, 0, "add immediate (32<8)" }, + { "xiy", OP48(0xeb0000000057LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0, "exclusive or immediate with long offset" }, + { "oiy", OP48(0xeb0000000056LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0, "or immediate with long offset" }, + { "cliy", OP48(0xeb0000000055LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0, "compare logical immediate with long offset" }, + { "niy", OP48(0xeb0000000054LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0, "and immediate with long offset" }, + { "mviy", OP48(0xeb0000000052LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0, "move immediate with long offset" }, + { "tmy", OP48(0xeb0000000051LL), MASK_SIY_URD, INSTR_SIY_URD, 2, 3, 0, "test under mask with long offset" }, + { "ecag", OP48(0xeb000000004cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 6, 0, "extract cache attribute" }, + { "bxleg", OP48(0xeb0000000045LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "branch on index low or equal 64" }, + { "bxleg", OP48(0xeb0000000045LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "branch on index low or equal 64" }, + { "bxhg", OP48(0xeb0000000044LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "branch on index high 64" }, + { "bxhg", OP48(0xeb0000000044LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "branch on index high 64" }, + { "cdsg", OP48(0xeb000000003eLL), MASK_RSY_RERERD, INSTR_RSY_RERERD, 2, 3, 0, "compare double and swap with long offset 64" }, + { "cdsg", OP48(0xeb000000003eLL), MASK_RSE_RERERD, INSTR_RSE_RERERD, 2, 2, 0, "compare double and swap 64" }, + { "cdsy", OP48(0xeb0000000031LL), MASK_RSY_RERERD, INSTR_RSY_RERERD, 2, 3, 0, "compare double and swap with long offset" }, + { "csg", OP48(0xeb0000000030LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "compare and swap with long offset 64" }, + { "csg", OP48(0xeb0000000030LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "compare and swap 64" }, + { "lctlg", OP48(0xeb000000002fLL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3, 0, "load control 64" }, + { "lctlg", OP48(0xeb000000002fLL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2, 0, "load control 64" }, + { "stcmy", OP48(0xeb000000002dLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0, "store characters under mask with long offset" }, + { "stcmh", OP48(0xeb000000002cLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0, "store characters under mask high with long offset" }, + { "stcmh", OP48(0xeb000000002cLL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2, 0, "store characters under mask high" }, + { "clgt", OP48(0xeb000000002bLL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 8, 0, "compare logical and trap 64 bit reg-mem" }, + { "stmh", OP48(0xeb0000000026LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "store multiple high" }, + { "stmh", OP48(0xeb0000000026LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "store multiple high" }, + { "stctg", OP48(0xeb0000000025LL), MASK_RSY_CCRD, INSTR_RSY_CCRD, 2, 3, 0, "store control 64" }, + { "stctg", OP48(0xeb0000000025LL), MASK_RSE_CCRD, INSTR_RSE_CCRD, 2, 2, 0, "store control 64" }, + { "stmg", OP48(0xeb0000000024LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "store multiple with long offset 64" }, + { "stmg", OP48(0xeb0000000024LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "store multiple 64" }, + { "clt", OP48(0xeb0000000023LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 8, 0, "compare logical and trap 32 bit reg-mem" }, + { "clmy", OP48(0xeb0000000021LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0, "compare logical characters under mask with long offset" }, + { "clmh", OP48(0xeb0000000020LL), MASK_RSY_RURD, INSTR_RSY_RURD, 2, 3, 0, "compare logical characters under mask high with long offset" }, + { "clmh", OP48(0xeb0000000020LL), MASK_RSE_RURD, INSTR_RSE_RURD, 2, 2, 0, "compare logical characters under mask high" }, + { "rll", OP48(0xeb000000001dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3, 0, "rotate left single logical 32" }, + { "rll", OP48(0xeb000000001dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 2, 0, "rotate left single logical 32" }, + { "rllg", OP48(0xeb000000001cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "rotate left single logical 64" }, + { "rllg", OP48(0xeb000000001cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "rotate left single logical 64" }, + { "pfcr", OP48(0xeb0000000016LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 13, 0, "perform functions with concurrent results" }, + { "csy", OP48(0xeb0000000014LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "compare and swap with long offset" }, + { "tracg", OP48(0xeb000000000fLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "trace 64" }, + { "tracg", OP48(0xeb000000000fLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "trace 64" }, + { "sllg", OP48(0xeb000000000dLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "shift left single logical 64" }, + { "sllg", OP48(0xeb000000000dLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "shift left single logical 64" }, + { "srlg", OP48(0xeb000000000cLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "shift right single logical 64" }, + { "srlg", OP48(0xeb000000000cLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "shift right single logical 64" }, + { "slag", OP48(0xeb000000000bLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "shift left single 64" }, + { "slag", OP48(0xeb000000000bLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "shift left single 64" }, + { "srag", OP48(0xeb000000000aLL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "shift right single 64" }, + { "srag", OP48(0xeb000000000aLL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "shift right single 64" }, + { "lmg", OP48(0xeb0000000004LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 2, 3, 0, "load multiple with long offset 64" }, + { "lmg", OP48(0xeb0000000004LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 2, 2, 0, "load multiple 64" }, + { "unpka", OP8(0xeaLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "unpack ascii" }, + { "pka", OP8(0xe9LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0, 0, "pack ascii" }, + { "mvcin", OP8(0xe8LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "move inverse" }, + { "vone", OP48(0xe700ffff0044LL), MASK_VRI_V, INSTR_VRI_V, 2, 9, 8, "vector set to ones" }, + { "wfnmaxb", OP48(0xe7000408009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp negative multiply and add scalar extended" }, + { "wfnmsxb", OP48(0xe7000408009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp negative multiply and subtract scalar extended" }, + { "wfmaxb", OP48(0xe7000408008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp multiply and add scalar extended" }, + { "wfmsxb", OP48(0xe7000408008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp multiply and subtract scalar extended" }, + { "vsbiq", OP48(0xe700040000bfLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector subtract with borrow indication quadword" }, + { "vsbcbiq", OP48(0xe700040000bdLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector subtract with borrow compute borrow indication quadword" }, + { "vacq", OP48(0xe700040000bbLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector add with carry quadword" }, + { "vacccq", OP48(0xe700040000b9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector add with carry compute carry quadword" }, + { "vmahq", OP48(0xe700040000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add high quadword" }, + { "vmalq", OP48(0xe700040000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add low quadword" }, + { "vmalhq", OP48(0xe700040000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add logical high quadword" }, + { "vblendq", OP48(0xe70004000089LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector blend quadword" }, + { "wfnmadb", OP48(0xe7000308009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp negative multiply and add scalar long" }, + { "wfnmsdb", OP48(0xe7000308009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp negative multiply and subtract scalar long" }, + { "wfmadb", OP48(0xe7000308008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8, "vector fp multiply and add long" }, + { "wfmsdb", OP48(0xe7000308008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8, "vector fp multiply and subtract long" }, + { "vgfmag", OP48(0xe700030000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector galois field multiply sum and accumulate doubleword" }, + { "vmslg", OP48(0xe700030000b8LL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 10, 0, "vector multiply sum logical double word" }, + { "vmaog", OP48(0xe700030000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add odd doubleword" }, + { "vmaeg", OP48(0xe700030000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add even doubleword" }, + { "vmalog", OP48(0xe700030000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add logical odd doubleword" }, + { "vmaleg", OP48(0xe700030000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add logical even doubleword" }, + { "vmahg", OP48(0xe700030000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add high doubleword" }, + { "vmalg", OP48(0xe700030000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add low doubleword" }, + { "vmalhg", OP48(0xe700030000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector multiply and add logical high doubleword" }, + { "vfnmadb", OP48(0xe7000300009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "vector fp negative multiply and add long" }, + { "vfnmsdb", OP48(0xe7000300009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "vector fp negative multiply and subtract long" }, + { "vfmadb", OP48(0xe7000300008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8, "vector fp multiply and add long" }, + { "vfmsdb", OP48(0xe7000300008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 9, 8, "vector fp multiply and subtract long" }, + { "vblendg", OP48(0xe70003000089LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector blend doubleword" }, + { "vstrczfs", OP48(0xe7000230008aLL), MASK_VRR_VVVU0VB3, INSTR_VRR_VVVU0VB3, 2, 9, 9, "vector string range compare word" }, + { "vstrszf", OP48(0xe7000220008bLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 11, 0, "vector string search word zero" }, + { "vstrczf", OP48(0xe7000220008aLL), MASK_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB2, 2, 9, 9, "vector string range compare word" }, + { "vstrcfs", OP48(0xe7000210008aLL), MASK_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB1, 2, 9, 9, "vector string range compare word" }, + { "wfnmasb", OP48(0xe7000208009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp negative multiply and add scalar short" }, + { "wfnmssb", OP48(0xe7000208009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp negative multiply and subtract scalar short" }, + { "wfmasb", OP48(0xe7000208008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp multiply and add scalar short" }, + { "wfmssb", OP48(0xe7000208008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "scalar vector fp multiply and subtract scalar short" }, + { "vgfmaf", OP48(0xe700020000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector galois field multiply sum and accumulate word" }, + { "vmaof", OP48(0xe700020000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add odd word" }, + { "vmaef", OP48(0xe700020000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add even word" }, + { "vmalof", OP48(0xe700020000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical odd word" }, + { "vmalef", OP48(0xe700020000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical even word" }, + { "vmahf", OP48(0xe700020000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add high word" }, + { "vmalf", OP48(0xe700020000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add low word" }, + { "vmalhf", OP48(0xe700020000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical high word" }, + { "vfnmasb", OP48(0xe7000200009fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "vector fp negative multiply and add short" }, + { "vfnmssb", OP48(0xe7000200009eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "vector fp negative multiply and subtract short" }, + { "vfmasb", OP48(0xe7000200008fLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "vector fp multiply and add short" }, + { "vfmssb", OP48(0xe7000200008eLL), MASK_VRR_VVVV, INSTR_VRR_VVVV, 2, 10, 0, "vector fp multiply and subtract short" }, + { "vstrsf", OP48(0xe7000200008bLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 11, 1, "vector string search word" }, + { "vstrcf", OP48(0xe7000200008aLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 9, 9, "vector string range compare word" }, + { "vblendf", OP48(0xe70002000089LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector blend word" }, + { "vstrczhs", OP48(0xe7000130008aLL), MASK_VRR_VVVU0VB3, INSTR_VRR_VVVU0VB3, 2, 9, 9, "vector string range compare halfword" }, + { "vstrszh", OP48(0xe7000120008bLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 11, 0, "vector string search halfword zero" }, + { "vstrczh", OP48(0xe7000120008aLL), MASK_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB2, 2, 9, 9, "vector string range compare halfword" }, + { "vstrchs", OP48(0xe7000110008aLL), MASK_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB1, 2, 9, 9, "vector string range compare halfword" }, + { "vgfmah", OP48(0xe700010000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector galois field multiply sum and accumulate halfword" }, + { "vmaoh", OP48(0xe700010000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add odd halfword" }, + { "vmaeh", OP48(0xe700010000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add even halfword" }, + { "vmaloh", OP48(0xe700010000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical odd halfword" }, + { "vmaleh", OP48(0xe700010000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical even halfword" }, + { "vmahh", OP48(0xe700010000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add high halfword" }, + { "vmalhw", OP48(0xe700010000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add low halfword" }, + { "vmalhh", OP48(0xe700010000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical high halfword" }, + { "vstrsh", OP48(0xe7000100008bLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 11, 1, "vector string search halfword" }, + { "vstrch", OP48(0xe7000100008aLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 9, 9, "vector string range compare halfword" }, + { "vblendh", OP48(0xe70001000089LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector blend halfword" }, + { "vfaezfs", OP48(0xe70000302082LL), MASK_VRR_VVV0U3, INSTR_VRR_VVV0U3, 2, 9, 9, "vector find any element equal" }, + { "vfenezfs", OP48(0xe70000302081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal word" }, + { "vfeezfs", OP48(0xe70000302080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal word" }, + { "vfaezhs", OP48(0xe70000301082LL), MASK_VRR_VVV0U3, INSTR_VRR_VVV0U3, 2, 9, 9, "vector find any element equal" }, + { "vfenezhs", OP48(0xe70000301081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal halfword" }, + { "vfeezhs", OP48(0xe70000301080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal halfword" }, + { "vstrczbs", OP48(0xe7000030008aLL), MASK_VRR_VVVU0VB3, INSTR_VRR_VVVU0VB3, 2, 9, 9, "vector string range compare byte" }, + { "vfaezbs", OP48(0xe70000300082LL), MASK_VRR_VVV0U3, INSTR_VRR_VVV0U3, 2, 9, 9, "vector find any element equal" }, + { "vfenezbs", OP48(0xe70000300081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal byte" }, + { "vfeezbs", OP48(0xe70000300080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal byte" }, + { "wflpxb", OP48(0xe700002840ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp perform sign operation scalar extended" }, + { "wflpdb", OP48(0xe700002830ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp perform sign operation long" }, + { "wflpsb", OP48(0xe700002820ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp perform sign operation scalar short" }, + { "vflpdb", OP48(0xe700002030ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp perform sign operation long" }, + { "vflpsb", OP48(0xe700002020ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector fp perform sign operation short" }, + { "vfaezf", OP48(0xe70000202082LL), MASK_VRR_VVV0U2, INSTR_VRR_VVV0U2, 2, 9, 9, "vector find any element equal" }, + { "vfenezf", OP48(0xe70000202081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal word" }, + { "vfeezf", OP48(0xe70000202080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal word" }, + { "vfaezh", OP48(0xe70000201082LL), MASK_VRR_VVV0U2, INSTR_VRR_VVV0U2, 2, 9, 9, "vector find any element equal" }, + { "vfenezh", OP48(0xe70000201081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal halfword" }, + { "vfeezh", OP48(0xe70000201080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal halfword" }, + { "vstrszb", OP48(0xe7000020008bLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 11, 0, "vector string search byte zero" }, + { "vstrczb", OP48(0xe7000020008aLL), MASK_VRR_VVVU0VB2, INSTR_VRR_VVVU0VB2, 2, 9, 9, "vector string range compare byte" }, + { "vfaezb", OP48(0xe70000200082LL), MASK_VRR_VVV0U2, INSTR_VRR_VVV0U2, 2, 9, 9, "vector find any element equal" }, + { "vfenezb", OP48(0xe70000200081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal byte" }, + { "vfeezb", OP48(0xe70000200080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal byte" }, + { "wfkhxbs", OP48(0xe700001c40ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high scalar extended" }, + { "wfkhexbs", OP48(0xe700001c40eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high or equal scalar extended" }, + { "wfkexbs", OP48(0xe700001c40e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal equal scalar extended" }, + { "wfkhdbs", OP48(0xe700001c30ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high long" }, + { "wfkhedbs", OP48(0xe700001c30eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high or equal long" }, + { "wfkedbs", OP48(0xe700001c30e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal equal long" }, + { "wfkhsbs", OP48(0xe700001c20ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high scalar short" }, + { "wfkhesbs", OP48(0xe700001c20eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high or equal scalar short" }, + { "wfkesbs", OP48(0xe700001c20e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar fp compare and signal equal scalar short" }, + { "wfchxbs", OP48(0xe700001840ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high scalar extended" }, + { "wfchexbs", OP48(0xe700001840eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high or equal scalar extended" }, + { "wfcexbs", OP48(0xe700001840e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare equal scalar extended" }, + { "wflnxb", OP48(0xe700001840ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp perform sign operation scalar extended" }, + { "wfchdbs", OP48(0xe700001830ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high long" }, + { "wfchedbs", OP48(0xe700001830eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high or equal long" }, + { "wfcedbs", OP48(0xe700001830e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare equal long" }, + { "wflndb", OP48(0xe700001830ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp perform sign operation long" }, + { "wfchsbs", OP48(0xe700001820ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high scalar short" }, + { "wfchesbs", OP48(0xe700001820eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high or equal scalar short" }, + { "wfcesbs", OP48(0xe700001820e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar fp compare equal scalar short" }, + { "wflnsb", OP48(0xe700001820ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp perform sign operation scalar short" }, + { "vfkhdbs", OP48(0xe700001430ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high long" }, + { "vfkhedbs", OP48(0xe700001430eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high or equal long" }, + { "vfkedbs", OP48(0xe700001430e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal equal long" }, + { "vfkhsbs", OP48(0xe700001420ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare and signal high short" }, + { "vfkhesbs", OP48(0xe700001420eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare and signal high or equal short" }, + { "vfkesbs", OP48(0xe700001420e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare and signal equal short" }, + { "vchqs", OP48(0xe700001040fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector compare high quadword" }, + { "vchlqs", OP48(0xe700001040f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector compare high logical quadword" }, + { "vceqqs", OP48(0xe700001040f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector compare equal quadword" }, + { "vchgs", OP48(0xe700001030fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high double word" }, + { "vchlgs", OP48(0xe700001030f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical double word" }, + { "vceqgs", OP48(0xe700001030f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal double word" }, + { "vfchdbs", OP48(0xe700001030ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high long" }, + { "vfchedbs", OP48(0xe700001030eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high or equal long" }, + { "vfcedbs", OP48(0xe700001030e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare equal long" }, + { "vflndb", OP48(0xe700001030ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp perform sign operation long" }, + { "vpksgs", OP48(0xe70000103097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack saturate double word" }, + { "vpklsgs", OP48(0xe70000103095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack logical saturate double word" }, + { "vchfs", OP48(0xe700001020fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high word" }, + { "vchlfs", OP48(0xe700001020f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical word" }, + { "vceqfs", OP48(0xe700001020f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal word" }, + { "vfchsbs", OP48(0xe700001020ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare high short" }, + { "vfchesbs", OP48(0xe700001020eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare high or equal short" }, + { "vfcesbs", OP48(0xe700001020e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare equal short" }, + { "vflnsb", OP48(0xe700001020ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector fp perform sign operation short" }, + { "vpksfs", OP48(0xe70000102097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack saturate word" }, + { "vpklsfs", OP48(0xe70000102095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack logical saturate word" }, + { "vfaefs", OP48(0xe70000102082LL), MASK_VRR_VVV0U1, INSTR_VRR_VVV0U1, 2, 9, 9, "vector find any element equal" }, + { "vfenefs", OP48(0xe70000102081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal word" }, + { "vfeefs", OP48(0xe70000102080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal word" }, + { "vistrfs", OP48(0xe7000010205cLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector isolate string word" }, + { "vchhs", OP48(0xe700001010fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high half word" }, + { "vchlhs", OP48(0xe700001010f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical half word" }, + { "vceqhs", OP48(0xe700001010f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal half word" }, + { "vpkshs", OP48(0xe70000101097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack saturate halfword" }, + { "vpklshs", OP48(0xe70000101095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack logical saturate halfword" }, + { "vfaehs", OP48(0xe70000101082LL), MASK_VRR_VVV0U1, INSTR_VRR_VVV0U1, 2, 9, 9, "vector find any element equal" }, + { "vfenehs", OP48(0xe70000101081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal halfword" }, + { "vfeehs", OP48(0xe70000101080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal halfword" }, + { "vistrhs", OP48(0xe7000010105cLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector isolate string halfword" }, + { "vchbs", OP48(0xe700001000fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high byte" }, + { "vchlbs", OP48(0xe700001000f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical byte" }, + { "vceqbs", OP48(0xe700001000f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal byte" }, + { "vstrcbs", OP48(0xe7000010008aLL), MASK_VRR_VVVU0VB1, INSTR_VRR_VVVU0VB1, 2, 9, 9, "vector string range compare byte" }, + { "vfaebs", OP48(0xe70000100082LL), MASK_VRR_VVV0U1, INSTR_VRR_VVV0U1, 2, 9, 9, "vector find any element equal" }, + { "vfenebs", OP48(0xe70000100081LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element not equal byte" }, + { "vfeebs", OP48(0xe70000100080LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector find element equal byte" }, + { "vistrbs", OP48(0xe7000010005cLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector isolate string byte" }, + { "wfkhxb", OP48(0xe700000c40ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high scalar extended" }, + { "wfkhexb", OP48(0xe700000c40eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high or equal scalar extended" }, + { "wfkexb", OP48(0xe700000c40e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal equal scalar extended" }, + { "wfkhdb", OP48(0xe700000c30ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high long" }, + { "wfkhedb", OP48(0xe700000c30eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high or equal long" }, + { "wfkedb", OP48(0xe700000c30e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal equal long" }, + { "wfkhsb", OP48(0xe700000c20ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high scalar short" }, + { "wfkhesb", OP48(0xe700000c20eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal high or equal scalar short" }, + { "wfkesb", OP48(0xe700000c20e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare and signal equal scalar short" }, + { "wfmaxxb", OP48(0xe700000840efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "scalar fp maximum scalar extended" }, + { "wfminxb", OP48(0xe700000840eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "scalar fp minimum scalar extended" }, + { "wfchxb", OP48(0xe700000840ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high scalar extended" }, + { "wfchexb", OP48(0xe700000840eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high or equal scalar extended" }, + { "wfcexb", OP48(0xe700000840e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare equal scalar extended" }, + { "wfmxb", OP48(0xe700000840e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp multiply scalar extended" }, + { "wfdxb", OP48(0xe700000840e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp divide scalar extended" }, + { "wfaxb", OP48(0xe700000840e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp add scalar extended" }, + { "wfsxb", OP48(0xe700000840e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp subtract scalar extended" }, + { "wfsqxb", OP48(0xe700000840ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp square root scalar extended" }, + { "wfpsoxb", OP48(0xe700000840ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 10, 0, "scalar vector fp perform sign operation scalar extended" }, + { "wflcxb", OP48(0xe700000840ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp perform sign operation scalar extended" }, + { "wfixb", OP48(0xe700000840c7LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0, "scalar vector load fp integer scalar extended" }, + { "wflrx", OP48(0xe700000840c5LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0, "scalar vector fp load rounded extended" }, + { "wftcixb", OP48(0xe7000008404aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 10, 0, "scalar vector fp test data class immediate scalar extended" }, + { "wfmaxdb", OP48(0xe700000830efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "scalar fp maximum scalar long" }, + { "wfmindb", OP48(0xe700000830eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "scalar fp minimum scalar long" }, + { "wfchdb", OP48(0xe700000830ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high long" }, + { "wfchedb", OP48(0xe700000830eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high or equal long" }, + { "wfcedb", OP48(0xe700000830e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare equal long" }, + { "wfmdb", OP48(0xe700000830e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp multiply long" }, + { "wfddb", OP48(0xe700000830e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp divide long" }, + { "wfadb", OP48(0xe700000830e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp add long" }, + { "wfsdb", OP48(0xe700000830e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp subtract long" }, + { "wfsqdb", OP48(0xe700000830ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp square root long" }, + { "wfpsodb", OP48(0xe700000830ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 8, "vector fp perform sign operation long" }, + { "wflcdb", OP48(0xe700000830ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp perform sign operation long" }, + { "wfidb", OP48(0xe700000830c7LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8, "vector load fp integer long" }, + { "wflrd", OP48(0xe700000830c5LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0, "scalar vector fp load rounded long" }, + { "wledb", OP48(0xe700000830c5LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8, "vector fp load rounded long to short" }, + { "wflld", OP48(0xe700000830c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp load lengthened long" }, + { "wcdgb", OP48(0xe700000830c3LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8, "vector fp convert from fixed 64 bit" }, + { "wcgdb", OP48(0xe700000830c2LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8, "vector fp convert to fixed 64 bit" }, + { "wcdlgb", OP48(0xe700000830c1LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8, "vector fp convert from logical 64 bit" }, + { "wclgdb", OP48(0xe700000830c0LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 9, 8, "vector fp convert to logical 64 bit" }, + { "wftcidb", OP48(0xe7000008304aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 9, 8, "vector fp test data class immediate" }, + { "wfmaxsb", OP48(0xe700000820efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "scalar fp maximum scalar short" }, + { "wfminsb", OP48(0xe700000820eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "scalar fp minimum scalar short" }, + { "wfchsb", OP48(0xe700000820ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high scalar short" }, + { "wfchesb", OP48(0xe700000820eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare high or equal scalar short" }, + { "wfcesb", OP48(0xe700000820e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp compare equal scalar short" }, + { "wfmsb", OP48(0xe700000820e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp multiply scalar short" }, + { "wfdsb", OP48(0xe700000820e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp divide scalar short" }, + { "wfasb", OP48(0xe700000820e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp add scalar short" }, + { "wfssb", OP48(0xe700000820e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "scalar vector fp subtract scalar short" }, + { "wfsqsb", OP48(0xe700000820ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp square root scalar short" }, + { "wfpsosb", OP48(0xe700000820ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 10, 0, "scalar vector fp perform sign operation scalar short" }, + { "wflcsb", OP48(0xe700000820ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp perform sign operation scalar short" }, + { "wfisb", OP48(0xe700000820c7LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 10, 0, "scalar vector load fp integer scalar short" }, + { "wflls", OP48(0xe700000820c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp load lengthened short" }, + { "wldeb", OP48(0xe700000820c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp load lengthened short to long" }, + { "wcefb", OP48(0xe700000820c3LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0, "vector fp convert from fixed 32 bit" }, + { "wcfeb", OP48(0xe700000820c2LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0, "vector fp convert to fixed 32 bit" }, + { "wcelfb", OP48(0xe700000820c1LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0, "vector fp convert from logical 32 bit" }, + { "wclfeb", OP48(0xe700000820c0LL), MASK_VRR_VV0UU8, INSTR_VRR_VV0UU8, 2, 11, 0, "vector fp convert to logical 32 bit" }, + { "wftcisb", OP48(0xe7000008204aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 10, 0, "scalar vector fp test data class immediate scalar short" }, + { "vfkhdb", OP48(0xe700000430ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high long" }, + { "vfkhedb", OP48(0xe700000430eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal high or equal long" }, + { "vfkedb", OP48(0xe700000430e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 8, "vector fp compare and signal equal long" }, + { "vfkhsb", OP48(0xe700000420ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare and signal high short" }, + { "vfkhesb", OP48(0xe700000420eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare and signal high or equal short" }, + { "vfkesb", OP48(0xe700000420e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare and signal equal short" }, + { "vllezlf", OP48(0xe70000006004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 10, 0, "vector load logical word element and zero - left aligned" }, + { "vmxq", OP48(0xe700000040ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector maximum quadword" }, + { "vmnq", OP48(0xe700000040feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector minimum quadword" }, + { "vmxlq", OP48(0xe700000040fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector maximum logical quadword" }, + { "vmnlq", OP48(0xe700000040fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector minimum logical quadword" }, + { "vchq", OP48(0xe700000040fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector compare high quadword" }, + { "vchlq", OP48(0xe700000040f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector compare high logical quadword" }, + { "vceqq", OP48(0xe700000040f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector compare equal quadword" }, + { "vsq", OP48(0xe700000040f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract quadword" }, + { "vscbiq", OP48(0xe700000040f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract compute borrow indication quadword" }, + { "vaq", OP48(0xe700000040f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add quad word" }, + { "vavgq", OP48(0xe700000040f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector average quadword" }, + { "vaccq", OP48(0xe700000040f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add compute carry quadword" }, + { "vavglq", OP48(0xe700000040f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector average logical quadword" }, + { "vlpq", OP48(0xe700000040dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector load positive quadword" }, + { "vlcq", OP48(0xe700000040deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector load complement quadword" }, + { "vecq", OP48(0xe700000040dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector element compare quadword" }, + { "veclq", OP48(0xe700000040d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector element compare logical quadword" }, + { "wfcxb", OP48(0xe700000040cbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp compare scalar extended" }, + { "wfkxb", OP48(0xe700000040caLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp compare and signal scalar extended" }, + { "vrq", OP48(0xe700000040b3LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector remainder quadword" }, + { "vdq", OP48(0xe700000040b2LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector divide quadword" }, + { "vrlq", OP48(0xe700000040b1LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector remainder logical quadword" }, + { "vdlq", OP48(0xe700000040b0LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector divide logical quadword" }, + { "vmhq", OP48(0xe700000040a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply high quadword" }, + { "vmlq", OP48(0xe700000040a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply low quadword" }, + { "vmlhq", OP48(0xe700000040a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply logical high quadword" }, + { "vgemq", OP48(0xe70000004054LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector generate element masks quadword" }, + { "vclzq", OP48(0xe70000004053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector count leading zeros quadword" }, + { "vctzq", OP48(0xe70000004052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector count trailing zeros quadword" }, + { "vmxg", OP48(0xe700000030ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum doubleword" }, + { "vmng", OP48(0xe700000030feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum doubleword" }, + { "vmxlg", OP48(0xe700000030fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum logical doubleword" }, + { "vmnlg", OP48(0xe700000030fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum logical doubleword" }, + { "vchg", OP48(0xe700000030fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high double word" }, + { "vchlg", OP48(0xe700000030f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical double word" }, + { "vceqg", OP48(0xe700000030f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal double word" }, + { "vsg", OP48(0xe700000030f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract doubleword" }, + { "vscbig", OP48(0xe700000030f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract compute borrow indication doubleword" }, + { "vag", OP48(0xe700000030f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add double word" }, + { "vavgg", OP48(0xe700000030f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average double word" }, + { "vaccg", OP48(0xe700000030f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add compute carry doubleword" }, + { "vavglg", OP48(0xe700000030f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average logical double word" }, + { "vfmaxdb", OP48(0xe700000030efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "vector fp maximum long" }, + { "vfmindb", OP48(0xe700000030eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "vector fp minimum long" }, + { "vfchdb", OP48(0xe700000030ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high long" }, + { "vfchedb", OP48(0xe700000030eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare high or equal long" }, + { "vfcedb", OP48(0xe700000030e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp compare equal long" }, + { "vfmdb", OP48(0xe700000030e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp multiply long" }, + { "vfddb", OP48(0xe700000030e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp divide long" }, + { "vfadb", OP48(0xe700000030e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp add long" }, + { "vfsdb", OP48(0xe700000030e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector fp subtract long" }, + { "vlpg", OP48(0xe700000030dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load positive doubleword" }, + { "vlcg", OP48(0xe700000030deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load complement doubleword" }, + { "vecg", OP48(0xe700000030dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare double word" }, + { "veclg", OP48(0xe700000030d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare logical double word" }, + { "vuphg", OP48(0xe700000030d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector unpack high doubleword" }, + { "vuplg", OP48(0xe700000030d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector unpack low doubleword" }, + { "vuplhg", OP48(0xe700000030d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector unpack logical high doubleword" }, + { "vupllg", OP48(0xe700000030d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector unpack logical low doubleword" }, + { "vfsqdb", OP48(0xe700000030ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp square root long" }, + { "vfpsodb", OP48(0xe700000030ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 8, "vector fp perform sign operation long" }, + { "vflcdb", OP48(0xe700000030ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp perform sign operation long" }, + { "wfcdb", OP48(0xe700000030cbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp compare scalar long" }, + { "wfkdb", OP48(0xe700000030caLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp compare and signal scalar long" }, + { "vfidb", OP48(0xe700000030c7LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8, "vector load fp integer long" }, + { "vflrd", OP48(0xe700000030c5LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 10, 0, "vector fp load rounded long" }, + { "vledb", OP48(0xe700000030c5LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8, "vector fp load rounded long to short" }, + { "vcdgb", OP48(0xe700000030c3LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8, "vector fp convert from fixed 64 bit" }, + { "vcgdb", OP48(0xe700000030c2LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8, "vector fp convert to fixed 64 bit" }, + { "vcdlgb", OP48(0xe700000030c1LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8, "vector fp convert from logical 64 bit" }, + { "vclgdb", OP48(0xe700000030c0LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 9, 8, "vector fp convert to logical 64 bit" }, + { "vgfmg", OP48(0xe700000030b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector galois field multiply sum doubleword" }, + { "vrg", OP48(0xe700000030b3LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector remainder doubleword" }, + { "vdg", OP48(0xe700000030b2LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector divide doubleword" }, + { "vrlg", OP48(0xe700000030b1LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector remainder logical doubleword" }, + { "vdlg", OP48(0xe700000030b0LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector divide logical doubleword" }, + { "vmog", OP48(0xe700000030a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply odd doubleword" }, + { "vmeg", OP48(0xe700000030a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply even doubleword" }, + { "vmlog", OP48(0xe700000030a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply logical odd doubleword" }, + { "vmleg", OP48(0xe700000030a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply logical even doubleword" }, + { "vmhg", OP48(0xe700000030a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply high doubleword" }, + { "vmlg", OP48(0xe700000030a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply low doubleword" }, + { "vmlhg", OP48(0xe700000030a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 13, 0, "vector multiply logical high doubleword" }, + { "vpksg", OP48(0xe70000003097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack saturate double word" }, + { "vpklsg", OP48(0xe70000003095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack logical saturate double word" }, + { "vpkg", OP48(0xe70000003094LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack double word" }, + { "vesravg", OP48(0xe7000000307aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right arithmetic reg doubleword" }, + { "vesrlvg", OP48(0xe70000003078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right logical reg doubleword" }, + { "verllvg", OP48(0xe70000003073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element rotate left logical reg doubleword" }, + { "verimg", OP48(0xe70000003072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8, "vector element rotate and insert under mask doubleword" }, + { "veslvg", OP48(0xe70000003070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift left reg doubleword" }, + { "vsumqg", OP48(0xe70000003067LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector sum across quadword - doubleword elements" }, + { "vmrhg", OP48(0xe70000003061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge high double word" }, + { "vmrlg", OP48(0xe70000003060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge low double word" }, + { "vgemg", OP48(0xe70000003054LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector generate element masks doubleword" }, + { "vclzg", OP48(0xe70000003053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count leading zeros doubleword" }, + { "vctzg", OP48(0xe70000003052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count trailing zeros doubleword" }, + { "vpopctg", OP48(0xe70000003050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector population count double word" }, + { "vrepg", OP48(0xe7000000304dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8, "vector replicate double word" }, + { "vftcidb", OP48(0xe7000000304aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 9, 8, "vector fp test data class immediate" }, + { "vgmg", OP48(0xe70000003046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8, "vector generate mask double word" }, + { "vrepig", OP48(0xe70000003045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8, "vector replicate immediate double word" }, + { "vesrag", OP48(0xe7000000303aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right arithmetic mem doubleword" }, + { "vesrlg", OP48(0xe70000003038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right logical mem doubleword" }, + { "verllg", OP48(0xe70000003033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element rotate left logical mem doubleword" }, + { "veslg", OP48(0xe70000003030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift left mem doubleword" }, + { "vlvgg", OP48(0xe70000003022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8, "vector load VR double word element from GR" }, + { "vlgvg", OP48(0xe70000003021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8, "vector load GR from VR double word element" }, + { "vlrepg", OP48(0xe70000003005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load and replicate double word elements" }, + { "vllezg", OP48(0xe70000003004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load logical double word element and zero" }, + { "vmxf", OP48(0xe700000020ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum word" }, + { "vmnf", OP48(0xe700000020feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum word" }, + { "vmxlf", OP48(0xe700000020fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum logical word" }, + { "vmnlf", OP48(0xe700000020fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum logical word" }, + { "vchf", OP48(0xe700000020fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high word" }, + { "vchlf", OP48(0xe700000020f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical word" }, + { "vceqf", OP48(0xe700000020f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal word" }, + { "vsf", OP48(0xe700000020f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract word" }, + { "vscbif", OP48(0xe700000020f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract compute borrow indication word" }, + { "vaf", OP48(0xe700000020f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add word" }, + { "vavgf", OP48(0xe700000020f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average word" }, + { "vaccf", OP48(0xe700000020f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add compute carry word" }, + { "vavglf", OP48(0xe700000020f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average logical word" }, + { "vfmaxsb", OP48(0xe700000020efLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "vector fp maximum short" }, + { "vfminsb", OP48(0xe700000020eeLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 10, 0, "vector fp minimum short" }, + { "vfchsb", OP48(0xe700000020ebLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare high short" }, + { "vfchesb", OP48(0xe700000020eaLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare high or equal short" }, + { "vfcesb", OP48(0xe700000020e8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp compare equal short" }, + { "vfmsb", OP48(0xe700000020e7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp multiply short" }, + { "vfdsb", OP48(0xe700000020e5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp divide short" }, + { "vfasb", OP48(0xe700000020e3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp add short" }, + { "vfssb", OP48(0xe700000020e2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector fp subtract short" }, + { "vlpf", OP48(0xe700000020dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load positive word" }, + { "vlcf", OP48(0xe700000020deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load complement word" }, + { "vecf", OP48(0xe700000020dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare word" }, + { "veclf", OP48(0xe700000020d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare logical word" }, + { "vuphf", OP48(0xe700000020d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack high word" }, + { "vuplf", OP48(0xe700000020d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack low word" }, + { "vuplhf", OP48(0xe700000020d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack logical high word" }, + { "vupllf", OP48(0xe700000020d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack logical low word" }, + { "vfsqsb", OP48(0xe700000020ceLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector fp square root short" }, + { "vfpsosb", OP48(0xe700000020ccLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 10, 0, "vector fp perform sign operation short" }, + { "vflcsb", OP48(0xe700000020ccLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector fp perform sign operation short" }, + { "wfcsb", OP48(0xe700000020cbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp compare scalar short" }, + { "wfksb", OP48(0xe700000020caLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "scalar vector fp compare and signal scalar short" }, + { "vfisb", OP48(0xe700000020c7LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 10, 0, "vector load fp integer short" }, + { "vflls", OP48(0xe700000020c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector fp load lengthened" }, + { "vldeb", OP48(0xe700000020c4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector fp load lengthened short to long" }, + { "vcefb", OP48(0xe700000020c3LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0, "vector fp convert from fixed 32 bit" }, + { "vcfeb", OP48(0xe700000020c2LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0, "vector fp convert to fixed 32 bit" }, + { "vcelfb", OP48(0xe700000020c1LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0, "vector fp convert from logical 32 bit" }, + { "vclfeb", OP48(0xe700000020c0LL), MASK_VRR_VV0UU, INSTR_VRR_VV0UU, 2, 11, 0, "vector fp convert to logical 32 bit" }, + { "vgfmf", OP48(0xe700000020b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector galois field multiply sum word" }, + { "vrf", OP48(0xe700000020b3LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector remainder word" }, + { "vdf", OP48(0xe700000020b2LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector divide word" }, + { "vrlf", OP48(0xe700000020b1LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector remainder logical word" }, + { "vdlf", OP48(0xe700000020b0LL), MASK_VRR_VVV0U02, INSTR_VRR_VVV0U02, 2, 13, 0, "vector divide logical word" }, + { "vmof", OP48(0xe700000020a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply odd word" }, + { "vmef", OP48(0xe700000020a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply even word" }, + { "vmlof", OP48(0xe700000020a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical odd word" }, + { "vmlef", OP48(0xe700000020a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical even word" }, + { "vmhf", OP48(0xe700000020a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply high word" }, + { "vmlf", OP48(0xe700000020a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply low word" }, + { "vmlhf", OP48(0xe700000020a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical high word" }, + { "vpksf", OP48(0xe70000002097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack saturate word" }, + { "vpklsf", OP48(0xe70000002095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack logical saturate word" }, + { "vpkf", OP48(0xe70000002094LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack word" }, + { "vfaef", OP48(0xe70000002082LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find any element equal word" }, + { "vfenef", OP48(0xe70000002081LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find element not equal word" }, + { "vfeef", OP48(0xe70000002080LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find element equal word" }, + { "vesravf", OP48(0xe7000000207aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right arithmetic reg word" }, + { "vesrlvf", OP48(0xe70000002078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right logical reg word" }, + { "verllvf", OP48(0xe70000002073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element rotate left logical reg word" }, + { "verimf", OP48(0xe70000002072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8, "vector element rotate and insert under mask word" }, + { "veslvf", OP48(0xe70000002070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift left reg word" }, + { "vsumqf", OP48(0xe70000002067LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector sum across quadword - word elements" }, + { "vsumgf", OP48(0xe70000002065LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector sum across doubleword - word" }, + { "vmrhf", OP48(0xe70000002061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge high word" }, + { "vmrlf", OP48(0xe70000002060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge low word" }, + { "vsegf", OP48(0xe7000000205fLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector sign extend word to double word" }, + { "vistrf", OP48(0xe7000000205cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 9, "vector isolate string word" }, + { "vgemf", OP48(0xe70000002054LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector generate element masks word" }, + { "vclzf", OP48(0xe70000002053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count leading zeros word" }, + { "vctzf", OP48(0xe70000002052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count trailing zeros word" }, + { "vpopctf", OP48(0xe70000002050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector population count word" }, + { "vrepf", OP48(0xe7000000204dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8, "vector replicate word" }, + { "vftcisb", OP48(0xe7000000204aLL), MASK_VRI_VVU2, INSTR_VRI_VVU2, 2, 10, 0, "vector fp test data class immediate short" }, + { "vgmf", OP48(0xe70000002046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8, "vector generate mask word" }, + { "vrepif", OP48(0xe70000002045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8, "vector replicate immediate word" }, + { "vesraf", OP48(0xe7000000203aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right arithmetic mem word" }, + { "vesrlf", OP48(0xe70000002038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right logical mem word" }, + { "verllf", OP48(0xe70000002033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element rotate left logical mem word" }, + { "veslf", OP48(0xe70000002030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift left mem word" }, + { "vlvgf", OP48(0xe70000002022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8, "vector load VR word element from GR" }, + { "vlgvf", OP48(0xe70000002021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8, "vector load GR from VR word element" }, + { "vlrepf", OP48(0xe70000002005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load and replicate word elements" }, + { "vllezf", OP48(0xe70000002004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load logical word element and zero" }, + { "vmxh", OP48(0xe700000010ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum halfword" }, + { "vmnh", OP48(0xe700000010feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum halfword" }, + { "vmxlh", OP48(0xe700000010fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum logical halfword" }, + { "vmnlh", OP48(0xe700000010fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum logical halfword" }, + { "vchh", OP48(0xe700000010fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high half word" }, + { "vchlh", OP48(0xe700000010f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical half word" }, + { "vceqh", OP48(0xe700000010f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal half word" }, + { "vsh", OP48(0xe700000010f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract halfword" }, + { "vscbih", OP48(0xe700000010f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract compute borrow indication halfword" }, + { "vah", OP48(0xe700000010f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add halfword" }, + { "vavgh", OP48(0xe700000010f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average half word" }, + { "vacch", OP48(0xe700000010f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add compute carry halfword" }, + { "vavglh", OP48(0xe700000010f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average logical half word" }, + { "vlph", OP48(0xe700000010dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load positive halfword" }, + { "vlch", OP48(0xe700000010deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load complement halfword" }, + { "vech", OP48(0xe700000010dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare half word" }, + { "veclh", OP48(0xe700000010d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare logical half word" }, + { "vuphh", OP48(0xe700000010d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack high halfword" }, + { "vuplhw", OP48(0xe700000010d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack low halfword" }, + { "vuplhh", OP48(0xe700000010d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack logical high halfword" }, + { "vupllh", OP48(0xe700000010d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack logical low halfword" }, + { "vgfmh", OP48(0xe700000010b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector galois field multiply sum halfword" }, + { "vmoh", OP48(0xe700000010a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply odd halfword" }, + { "vmeh", OP48(0xe700000010a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply even halfword" }, + { "vmloh", OP48(0xe700000010a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical odd halfword" }, + { "vmleh", OP48(0xe700000010a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical even halfword" }, + { "vmhh", OP48(0xe700000010a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply high halfword" }, + { "vmlhw", OP48(0xe700000010a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply low halfword" }, + { "vmlhh", OP48(0xe700000010a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical high halfword" }, + { "vpksh", OP48(0xe70000001097LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack saturate halfword" }, + { "vpklsh", OP48(0xe70000001095LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack logical saturate halfword" }, + { "vpkh", OP48(0xe70000001094LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector pack halfword" }, + { "vfaeh", OP48(0xe70000001082LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find any element equal halfword" }, + { "vfeneh", OP48(0xe70000001081LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find element not equal halfword" }, + { "vfeeh", OP48(0xe70000001080LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find element equal halfword" }, + { "vesravh", OP48(0xe7000000107aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right arithmetic reg halfword" }, + { "vesrlvh", OP48(0xe70000001078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right logical reg halfword" }, + { "verllvh", OP48(0xe70000001073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element rotate left logical reg halfword" }, + { "verimh", OP48(0xe70000001072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8, "vector element rotate and insert under mask halfword" }, + { "veslvh", OP48(0xe70000001070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift left reg halfword" }, + { "vsumgh", OP48(0xe70000001065LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector sum across doubleword - halfword" }, + { "vsumh", OP48(0xe70000001064LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector sum across word - halfword elements" }, + { "vmrhh", OP48(0xe70000001061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge high halfword" }, + { "vmrlh", OP48(0xe70000001060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge low halfword" }, + { "vsegh", OP48(0xe7000000105fLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector sign extend halfword to double word" }, + { "vistrh", OP48(0xe7000000105cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 9, "vector isolate string halfword" }, + { "vgemh", OP48(0xe70000001054LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector generate element masks halfword" }, + { "vclzh", OP48(0xe70000001053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count leading zeros halfword" }, + { "vctzh", OP48(0xe70000001052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count trailing zeros halfword" }, + { "vpopcth", OP48(0xe70000001050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector population count halfword" }, + { "vreph", OP48(0xe7000000104dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8, "vector replicate halfword" }, + { "vgmh", OP48(0xe70000001046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8, "vector generate mask halfword" }, + { "vrepih", OP48(0xe70000001045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8, "vector replicate immediate halfword" }, + { "vesrah", OP48(0xe7000000103aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right arithmetic mem halfword" }, + { "vesrlh", OP48(0xe70000001038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right logical mem halfword" }, + { "verllh", OP48(0xe70000001033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element rotate left logical mem halfword" }, + { "veslh", OP48(0xe70000001030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift left mem halfword" }, + { "vlvgh", OP48(0xe70000001022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8, "vector load VR halfword element from GR" }, + { "vlgvh", OP48(0xe70000001021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8, "vector load GR from VR halfword element" }, + { "vlreph", OP48(0xe70000001005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load and replicate halfword elements" }, + { "vllezh", OP48(0xe70000001004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load logical halfword element and zero" }, + { "vmx", OP48(0xe700000000ffLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector maximum" }, + { "vmxb", OP48(0xe700000000ffLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum byte" }, + { "vmn", OP48(0xe700000000feLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector minimum" }, + { "vmnb", OP48(0xe700000000feLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum byte" }, + { "vmxl", OP48(0xe700000000fdLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector maximum logical" }, + { "vmxlb", OP48(0xe700000000fdLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector maximum logical byte" }, + { "vmnl", OP48(0xe700000000fcLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector minimum logical" }, + { "vmnlb", OP48(0xe700000000fcLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector minimum logical byte" }, + { "vch", OP48(0xe700000000fbLL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8, "vector compare high" }, + { "vchb", OP48(0xe700000000fbLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high byte" }, + { "vchl", OP48(0xe700000000f9LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8, "vector compare high logical" }, + { "vchlb", OP48(0xe700000000f9LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare high logical byte" }, + { "vceq", OP48(0xe700000000f8LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8, "vector compare equal" }, + { "vceqb", OP48(0xe700000000f8LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector compare equal byte" }, + { "vs", OP48(0xe700000000f7LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector subtract" }, + { "vsb", OP48(0xe700000000f7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract byte" }, + { "vscbi", OP48(0xe700000000f5LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector subtract compute borrow indication" }, + { "vscbib", OP48(0xe700000000f5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector subtract compute borrow indication byte" }, + { "va", OP48(0xe700000000f3LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector add" }, + { "vab", OP48(0xe700000000f3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add byte" }, + { "vavg", OP48(0xe700000000f2LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector average" }, + { "vavgb", OP48(0xe700000000f2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average byte" }, + { "vacc", OP48(0xe700000000f1LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector add compute carry" }, + { "vaccb", OP48(0xe700000000f1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector add compute carry byte" }, + { "vavgl", OP48(0xe700000000f0LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector average logical" }, + { "vavglb", OP48(0xe700000000f0LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector average logical byte" }, + { "vfmax", OP48(0xe700000000efLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 10, 0, "vector fp maximum" }, + { "vfmin", OP48(0xe700000000eeLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 10, 0, "vector fp minimum" }, + { "vfch", OP48(0xe700000000ebLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 9, 8, "vector fp compare high" }, + { "vfche", OP48(0xe700000000eaLL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 9, 8, "vector fp compare high or equal" }, + { "vfce", OP48(0xe700000000e8LL), MASK_VRR_VVV0UUU, INSTR_VRR_VVV0UUU, 2, 9, 8, "vector fp compare equal" }, + { "vfm", OP48(0xe700000000e7LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8, "vector fp multiply" }, + { "vfd", OP48(0xe700000000e5LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8, "vector fp divide" }, + { "vfa", OP48(0xe700000000e3LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8, "vector fp add" }, + { "vfs", OP48(0xe700000000e2LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 9, 8, "vector fp subtract" }, + { "vlp", OP48(0xe700000000dfLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector load positive" }, + { "vlpb", OP48(0xe700000000dfLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load positive byte" }, + { "vlc", OP48(0xe700000000deLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector load complement" }, + { "vlcb", OP48(0xe700000000deLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector load complement byte" }, + { "vec", OP48(0xe700000000dbLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector element compare" }, + { "vecb", OP48(0xe700000000dbLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare byte" }, + { "vecl", OP48(0xe700000000d9LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector element compare logical" }, + { "veclb", OP48(0xe700000000d9LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector element compare logical byte" }, + { "vtm", OP48(0xe700000000d8LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector test under mask" }, + { "vuph", OP48(0xe700000000d7LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector unpack high" }, + { "vuphb", OP48(0xe700000000d7LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack high byte" }, + { "vupl", OP48(0xe700000000d6LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector unpack low" }, + { "vuplb", OP48(0xe700000000d6LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack low byte" }, + { "vuplh", OP48(0xe700000000d5LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector unpack logical high" }, + { "vuplhb", OP48(0xe700000000d5LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack logical high byte" }, + { "vupll", OP48(0xe700000000d4LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector unpack logical low" }, + { "vupllb", OP48(0xe700000000d4LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector unpack logical low byte" }, + { "vfsq", OP48(0xe700000000ceLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8, "vector fp square root" }, + { "vfpso", OP48(0xe700000000ccLL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector fp perform sign operation" }, + { "wfc", OP48(0xe700000000cbLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8, "vector fp compare scalar" }, + { "wfk", OP48(0xe700000000caLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8, "vector fp compare and signal scalar" }, + { "vfi", OP48(0xe700000000c7LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector load fp integer" }, + { "vflr", OP48(0xe700000000c5LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 10, 0, "vector fp load rounded" }, + { "vled", OP48(0xe700000000c5LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector fp load rounded" }, + { "vfll", OP48(0xe700000000c4LL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 10, 0, "vector fp load lengthened" }, + { "vlde", OP48(0xe700000000c4LL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 9, 8, "vector fp load lengthened" }, + { "vcfps", OP48(0xe700000000c3LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0, "vector fp convert from fixed" }, + { "vcdg", OP48(0xe700000000c3LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector fp convert from fixed 64 bit" }, + { "vcsfp", OP48(0xe700000000c2LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0, "vector fp convert to fixed" }, + { "vcgd", OP48(0xe700000000c2LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector fp convert to fixed 64 bit" }, + { "vcfpl", OP48(0xe700000000c1LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0, "vector fp convert from logical" }, + { "vcdlg", OP48(0xe700000000c1LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector fp convert from logical 64 bit" }, + { "vclfp", OP48(0xe700000000c0LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 11, 0, "vector fp convert to logical" }, + { "vclgd", OP48(0xe700000000c0LL), MASK_VRR_VV0UUU, INSTR_VRR_VV0UUU, 2, 9, 8, "vector fp convert to logical 64 bit" }, + { "vsbi", OP48(0xe700000000bfLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector subtract with borrow indication" }, + { "vsbcbi", OP48(0xe700000000bdLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector subtract with borrow compute borrow indication" }, + { "vgfma", OP48(0xe700000000bcLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector galois field multiply sum and accumulate" }, + { "vgfmab", OP48(0xe700000000bcLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector galois field multiply sum and accumulate byte" }, + { "vac", OP48(0xe700000000bbLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector add with carry" }, + { "vaccc", OP48(0xe700000000b9LL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector add with carry compute carry" }, + { "vmsl", OP48(0xe700000000b8LL), MASK_VRR_VVVUU0V, INSTR_VRR_VVVUU0V, 2, 10, 0, "vector multiply sum logical" }, + { "vgfm", OP48(0xe700000000b4LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector galois field multiply sum" }, + { "vgfmb", OP48(0xe700000000b4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector galois field multiply sum byte" }, + { "vr", OP48(0xe700000000b3LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 13, 0, "vector remainder" }, + { "vd", OP48(0xe700000000b2LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 13, 0, "vector divide" }, + { "vrl", OP48(0xe700000000b1LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 13, 0, "vector remainder logical" }, + { "vdl", OP48(0xe700000000b0LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 13, 0, "vector divide logical" }, + { "vmao", OP48(0xe700000000afLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add odd" }, + { "vmaob", OP48(0xe700000000afLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add odd byte" }, + { "vmae", OP48(0xe700000000aeLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add even" }, + { "vmaeb", OP48(0xe700000000aeLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add even byte" }, + { "vmalo", OP48(0xe700000000adLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add logical odd" }, + { "vmalob", OP48(0xe700000000adLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical odd byte" }, + { "vmale", OP48(0xe700000000acLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add logical even" }, + { "vmaleb", OP48(0xe700000000acLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical even byte" }, + { "vmah", OP48(0xe700000000abLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add high" }, + { "vmahb", OP48(0xe700000000abLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add high byte" }, + { "vmal", OP48(0xe700000000aaLL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add low" }, + { "vmalb", OP48(0xe700000000aaLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add low byte" }, + { "vmalh", OP48(0xe700000000a9LL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 9, 8, "vector multiply and add logical high" }, + { "vmalhb", OP48(0xe700000000a9LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector multiply and add logical high byte" }, + { "vmo", OP48(0xe700000000a7LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply odd" }, + { "vmob", OP48(0xe700000000a7LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply odd byte" }, + { "vme", OP48(0xe700000000a6LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply even" }, + { "vmeb", OP48(0xe700000000a6LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply even byte" }, + { "vmlo", OP48(0xe700000000a5LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply logical odd" }, + { "vmlob", OP48(0xe700000000a5LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical odd byte" }, + { "vmle", OP48(0xe700000000a4LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply logical even" }, + { "vmleb", OP48(0xe700000000a4LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical even byte" }, + { "vmh", OP48(0xe700000000a3LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply high" }, + { "vmhb", OP48(0xe700000000a3LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply high byte" }, + { "vml", OP48(0xe700000000a2LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply low" }, + { "vmlb", OP48(0xe700000000a2LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply low byte" }, + { "vmlh", OP48(0xe700000000a1LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector multiply logical high" }, + { "vmlhb", OP48(0xe700000000a1LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector multiply logical high byte" }, + { "vfnma", OP48(0xe7000000009fLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 10, 0, "vector fp negative multiply and add" }, + { "vfnms", OP48(0xe7000000009eLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 10, 0, "vector fp negative multiply and subtract" }, + { "vpks", OP48(0xe70000000097LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8, "vector pack saturate" }, + { "vpkls", OP48(0xe70000000095LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 8, "vector pack logical saturate" }, + { "vpk", OP48(0xe70000000094LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector pack" }, + { "vfma", OP48(0xe7000000008fLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 9, 8, "vector fp multiply and add" }, + { "vfms", OP48(0xe7000000008eLL), MASK_VRR_VVVU0UV, INSTR_VRR_VVVU0UV, 2, 9, 8, "vector fp multiply and subtract" }, + { "vsel", OP48(0xe7000000008dLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector select" }, + { "vperm", OP48(0xe7000000008cLL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 9, 8, "vector permute" }, + { "vstrs", OP48(0xe7000000008bLL), MASK_VRR_VVVUU0V, INSTR_VRR_VVVUU0V, 2, 11, 1, "vector string search" }, + { "vstrsb", OP48(0xe7000000008bLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 11, 1, "vector string search byte" }, + { "vstrc", OP48(0xe7000000008aLL), MASK_VRR_VVVUU0V, INSTR_VRR_VVVUU0V, 2, 9, 9, "vector string range compare" }, + { "vstrcb", OP48(0xe7000000008aLL), MASK_VRR_VVVU0VB, INSTR_VRR_VVVU0VB, 2, 9, 9, "vector string range compare byte" }, + { "vblend", OP48(0xe70000000089LL), MASK_VRR_VVVU0V, INSTR_VRR_VVVU0V, 2, 13, 0, "vector blend" }, + { "vblendb", OP48(0xe70000000089LL), MASK_VRR_VVV0V, INSTR_VRR_VVV0V, 2, 13, 0, "vector blend byte" }, + { "veval", OP48(0xe70000000088LL), MASK_VRI_VVV0UV, INSTR_VRI_VVV0UV, 2, 13, 0, "vector evaluate" }, + { "vsrd", OP48(0xe70000000087LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 11, 0, "vector shift right double by bit" }, + { "vsld", OP48(0xe70000000086LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 11, 0, "vector shift left double by bit" }, + { "vbperm", OP48(0xe70000000085LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector bit permute" }, + { "vpdi", OP48(0xe70000000084LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector permute double word immediate" }, + { "vfae", OP48(0xe70000000082LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 9, "vector find any element equal" }, + { "vfaeb", OP48(0xe70000000082LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find any element equal byte" }, + { "vfene", OP48(0xe70000000081LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 9, "vector find element not equal" }, + { "vfeneb", OP48(0xe70000000081LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find element not equal byte" }, + { "vfee", OP48(0xe70000000080LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 9, 9, "vector find element equal" }, + { "vfeeb", OP48(0xe70000000080LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 9, 9, "vector find element equal byte" }, + { "vsrab", OP48(0xe7000000007fLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector shift right arithmetic by byte" }, + { "vsra", OP48(0xe7000000007eLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector shift right arithmetic" }, + { "vsrlb", OP48(0xe7000000007dLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector shift right logical by byte" }, + { "vsrl", OP48(0xe7000000007cLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector shift right logical" }, + { "vesrav", OP48(0xe7000000007aLL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector element shift right arithmetic reg" }, + { "vesravb", OP48(0xe7000000007aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right arithmetic reg byte" }, + { "vesrlv", OP48(0xe70000000078LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector element shift right logical reg" }, + { "vesrlvb", OP48(0xe70000000078LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift right logical reg byte" }, + { "vsldb", OP48(0xe70000000077LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8, "vector shift left double by byte" }, + { "vslb", OP48(0xe70000000075LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector shift left by byte" }, + { "vsl", OP48(0xe70000000074LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector shift left" }, + { "verllv", OP48(0xe70000000073LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector element rotate left logical reg" }, + { "verllvb", OP48(0xe70000000073LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element rotate left logical reg byte" }, + { "verim", OP48(0xe70000000072LL), MASK_VRI_VVV0UU, INSTR_VRI_VVV0UU, 2, 9, 8, "vector element rotate and insert under mask" }, + { "verimb", OP48(0xe70000000072LL), MASK_VRI_VVV0U, INSTR_VRI_VVV0U, 2, 9, 8, "vector element rotate and insert under mask byte" }, + { "veslv", OP48(0xe70000000070LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector element shift left reg" }, + { "veslvb", OP48(0xe70000000070LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector element shift left reg byte" }, + { "voc", OP48(0xe7000000006fLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector or with complement" }, + { "vnn", OP48(0xe7000000006eLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector nand" }, + { "vx", OP48(0xe7000000006dLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector exclusive or" }, + { "vnx", OP48(0xe7000000006cLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 10, 0, "vector not exclusive or" }, + { "vno", OP48(0xe7000000006bLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector nor" }, + { "vnot", OP48(0xe7000000006bLL), MASK_VRR_VVV2, INSTR_VRR_VVV2, 2, 9, 8, "vector not" }, + { "vo", OP48(0xe7000000006aLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector or" }, + { "vnc", OP48(0xe70000000069LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector and with complement" }, + { "vn", OP48(0xe70000000068LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector and" }, + { "vsumq", OP48(0xe70000000067LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector sum across quadword" }, + { "vcksm", OP48(0xe70000000066LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector checksum" }, + { "vsumg", OP48(0xe70000000065LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector sum across doubleword" }, + { "vsum", OP48(0xe70000000064LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector sum across word" }, + { "vsumb", OP48(0xe70000000064LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector sum across word - byte elements" }, + { "vlvgp", OP48(0xe70000000062LL), MASK_VRR_VRR, INSTR_VRR_VRR, 2, 9, 8, "vector load VR from GRs disjoint" }, + { "vmrh", OP48(0xe70000000061LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector merge high" }, + { "vmrhb", OP48(0xe70000000061LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge high byte" }, + { "vmrl", OP48(0xe70000000060LL), MASK_VRR_VVV0U, INSTR_VRR_VVV0U, 2, 9, 8, "vector merge low" }, + { "vmrlb", OP48(0xe70000000060LL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 9, 8, "vector merge low byte" }, + { "vseg", OP48(0xe7000000005fLL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector sign extend to double word" }, + { "vsegb", OP48(0xe7000000005fLL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector sign extend byte to double word" }, + { "vistr", OP48(0xe7000000005cLL), MASK_VRR_VV0U0U, INSTR_VRR_VV0U0U, 2, 9, 9, "vector isolate string" }, + { "vistrb", OP48(0xe7000000005cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 9, 9, "vector isolate string byte" }, + { "vlr", OP48(0xe70000000056LL), MASK_VRX_VV, INSTR_VRX_VV, 2, 9, 8, "vector register load" }, + { "vgem", OP48(0xe70000000054LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 13, 0, "vector generate element masks" }, + { "vgemb", OP48(0xe70000000054LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 13, 0, "vector generate element masks byte" }, + { "vclz", OP48(0xe70000000053LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector count leading zeros" }, + { "vclzb", OP48(0xe70000000053LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count leading zeros byte" }, + { "vctz", OP48(0xe70000000052LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector count trailing zeros" }, + { "vctzb", OP48(0xe70000000052LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 9, 8, "vector count trailing zeros byte" }, + { "vpopctb", OP48(0xe70000000050LL), MASK_VRR_VV, INSTR_VRR_VV, 2, 10, 0, "vector population count byte" }, + { "vpopct", OP48(0xe70000000050LL), MASK_VRR_VV0U, INSTR_VRR_VV0U, 2, 9, 8, "vector population count" }, + { "vrep", OP48(0xe7000000004dLL), MASK_VRI_VVUU, INSTR_VRI_VVUU, 2, 9, 8, "vector replicate" }, + { "vrepb", OP48(0xe7000000004dLL), MASK_VRI_VVU, INSTR_VRI_VVU, 2, 9, 8, "vector replicate byte" }, + { "vftci", OP48(0xe7000000004aLL), MASK_VRI_VVUUU, INSTR_VRI_VVUUU, 2, 9, 8, "vector fp test data class immediate" }, + { "vgm", OP48(0xe70000000046LL), MASK_VRI_V0UUU, INSTR_VRI_V0UUU, 2, 9, 8, "vector generate mask" }, + { "vgmb", OP48(0xe70000000046LL), MASK_VRI_V0UU, INSTR_VRI_V0UU, 2, 9, 8, "vector generate mask byte" }, + { "vrepi", OP48(0xe70000000045LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8, "vector replicate immediate" }, + { "vrepib", OP48(0xe70000000045LL), MASK_VRI_V0I, INSTR_VRI_V0I, 2, 9, 8, "vector replicate immediate byte" }, + { "vgbm", OP48(0xe70000000044LL), MASK_VRI_V0U, INSTR_VRI_V0U, 2, 9, 8, "vector generate byte mask" }, + { "vzero", OP48(0xe70000000044LL), MASK_VRI_V, INSTR_VRI_V, 2, 9, 8, "vector set to zero" }, + { "vleif", OP48(0xe70000000043LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8, "vector load word element immediate" }, + { "vleig", OP48(0xe70000000042LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8, "vector load double word element immediate" }, + { "vleih", OP48(0xe70000000041LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8, "vector load halfword element immediate" }, + { "vleib", OP48(0xe70000000040LL), MASK_VRI_V0IU, INSTR_VRI_V0IU, 2, 9, 8, "vector load byte element immediate" }, + { "vstl", OP48(0xe7000000003fLL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8, "vector store with length" }, + { "vstm", OP48(0xe7000000003eLL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 9, "vector store multiple" }, + { "vesra", OP48(0xe7000000003aLL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8, "vector element shift right arithmetic mem" }, + { "vesrab", OP48(0xe7000000003aLL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right arithmetic mem byte" }, + { "vesrl", OP48(0xe70000000038LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8, "vector element shift right logical mem" }, + { "vesrlb", OP48(0xe70000000038LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift right logical mem byte" }, + { "vll", OP48(0xe70000000037LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8, "vector load with length" }, + { "vlm", OP48(0xe70000000036LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 9, "vector load multiple" }, + { "verll", OP48(0xe70000000033LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8, "vector element rotate left logical mem" }, + { "verllb", OP48(0xe70000000033LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element rotate left logical mem byte" }, + { "vesl", OP48(0xe70000000030LL), MASK_VRS_VVRDU, INSTR_VRS_VVRDU, 2, 9, 8, "vector element shift left mem" }, + { "veslb", OP48(0xe70000000030LL), MASK_VRS_VVRD, INSTR_VRS_VVRD, 2, 9, 8, "vector element shift left mem byte" }, + { "lcbb", OP48(0xe70000000027LL), MASK_RXE_RRRDU, INSTR_RXE_RRRDU, 2, 9, 8, "load count to block boundary" }, + { "vlvg", OP48(0xe70000000022LL), MASK_VRS_VRRDU, INSTR_VRS_VRRDU, 2, 9, 8, "vector load VR element from GR" }, + { "vlvgb", OP48(0xe70000000022LL), MASK_VRS_VRRD, INSTR_VRS_VRRD, 2, 9, 8, "vector load VR byte element from GR" }, + { "vlgv", OP48(0xe70000000021LL), MASK_VRS_RVRDU, INSTR_VRS_RVRDU, 2, 9, 8, "vector load GR from VR element" }, + { "vlgvb", OP48(0xe70000000021LL), MASK_VRS_RVRD, INSTR_VRS_RVRD, 2, 9, 8, "vector load GR from VR byte element" }, + { "vscef", OP48(0xe7000000001bLL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8, "vector scatter element 4 byte" }, + { "vsceg", OP48(0xe7000000001aLL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8, "vector scatter element 8 byte" }, + { "vgef", OP48(0xe70000000013LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8, "vector gather element 4 byte elements" }, + { "vgeg", OP48(0xe70000000012LL), MASK_VRV_VVXRDU, INSTR_VRV_VVXRDU, 2, 9, 8, "vector gather element 8 byte elements" }, + { "vst", OP48(0xe7000000000eLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 9, "vector store" }, + { "vstef", OP48(0xe7000000000bLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector store word element" }, + { "vsteg", OP48(0xe7000000000aLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector store double word element" }, + { "vsteh", OP48(0xe70000000009LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector store halfword element" }, + { "vsteb", OP48(0xe70000000008LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector store byte element" }, + { "vlbb", OP48(0xe70000000007LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load to block boundary" }, + { "vl", OP48(0xe70000000006LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 9, "vector memory load" }, + { "vlrep", OP48(0xe70000000005LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load and replicate" }, + { "vlrepb", OP48(0xe70000000005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load and replicate byte elements" }, + { "vllez", OP48(0xe70000000004LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load logical element and zero" }, + { "vllezb", OP48(0xe70000000004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 9, 8, "vector load logical byte element and zero" }, + { "vlef", OP48(0xe70000000003LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load word element" }, + { "vleg", OP48(0xe70000000002LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load double word element" }, + { "vleh", OP48(0xe70000000001LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load halfword element" }, + { "vleb", OP48(0xe70000000000LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 9, 8, "vector load byte element" }, + { "lerv", OP48(0xe60000006004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "load byte reversed word" }, + { "vllebrze", OP48(0xe60000006004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed word element left-aligned and zero" }, + { "vschxp", OP48(0xe60000004074LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 12, 0, "decimal scale and convert to extended hfp" }, + { "vstbrq", OP48(0xe6000000400eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store byte reversed quadword elements" }, + { "vlbrq", OP48(0xe60000004006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed quadword elements" }, + { "vschdp", OP48(0xe60000003074LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 12, 0, "decimal scale and convert to long hfp" }, + { "vsterg", OP48(0xe6000000300fLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store doubleword elements reversed" }, + { "vstbrg", OP48(0xe6000000300eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store byte reversed doubleword elements" }, + { "vlerg", OP48(0xe60000003007LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load doubleword elements reversed" }, + { "vlbrg", OP48(0xe60000003006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed doubleword elements" }, + { "vlbrrepg", OP48(0xe60000003005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed doubleword element and replicate" }, + { "ldrv", OP48(0xe60000003004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "load byte reversed doubleword" }, + { "vllebrzg", OP48(0xe60000003004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed doubleword element and zero" }, + { "vschsp", OP48(0xe60000002074LL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 12, 0, "decimal scale and convert to short hfp" }, + { "vsterf", OP48(0xe6000000200fLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store word elements reversed" }, + { "vstbrf", OP48(0xe6000000200eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store byte reversed word elements" }, + { "vlerf", OP48(0xe60000002007LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load word elements reversed" }, + { "vlbrf", OP48(0xe60000002006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed word elements" }, + { "vlbrrepf", OP48(0xe60000002005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed word element and replicate" }, + { "vllebrzf", OP48(0xe60000002004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed word element and zero" }, + { "vsterh", OP48(0xe6000000100fLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store halfword elements reversed" }, + { "vstbrh", OP48(0xe6000000100eLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector store byte reversed halfword elements" }, + { "vlerh", OP48(0xe60000001007LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load halfword elements reversed" }, + { "vlbrh", OP48(0xe60000001006LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed halfword elements" }, + { "vlbrreph", OP48(0xe60000001005LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed halfword element and replicate" }, + { "vllebrzh", OP48(0xe60000001004LL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "vector load byte reversed halfword element and zero" }, + { "vtz", OP48(0xe6000000007fLL), MASK_VRR_0VVU, INSTR_VRR_0VVU, 2, 13, 0, "vector test zoned" }, + { "vsdp", OP48(0xe6000000007eLL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector shift and divide decimal" }, + { "vcsph", OP48(0xe6000000007dLL), MASK_VRR_VVV0U0, INSTR_VRR_VVV0U0, 2, 12, 0, "vector convert hfp to scaled decimal" }, + { "vscshp", OP48(0xe6000000007cLL), MASK_VRR_VVV, INSTR_VRR_VVV, 2, 12, 0, "decimal scale and convert and split to hfp" }, + { "vrp", OP48(0xe6000000007bLL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector remainder decimal" }, + { "vdp", OP48(0xe6000000007aLL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector divide decimal" }, + { "vmsp", OP48(0xe60000000079LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector multiply and shift decimal" }, + { "vmp", OP48(0xe60000000078LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector multiply decimal" }, + { "vcp", OP48(0xe60000000077LL), MASK_VRR_0VV0U, INSTR_VRR_0VV0U, 2, 10, 0, "vector compare decimal" }, + { "vcrnf", OP48(0xe60000000075LL), MASK_VRR_VVV0UU, INSTR_VRR_VVV0UU, 2, 12, 0, "vector fp convert and round to nnp" }, + { "vschp", OP48(0xe60000000074LL), MASK_VRR_VVV0U0U, INSTR_VRR_VVV0U0U, 2, 12, 0, "decimal scale and convert to hfp" }, + { "vsp", OP48(0xe60000000073LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector subtract decimal" }, + { "vsrpr", OP48(0xe60000000072LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 12, 0, "vector shift and round decimal register" }, + { "vap", OP48(0xe60000000071LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 10, 0, "vector add decimal" }, + { "vpkzr", OP48(0xe60000000070LL), MASK_VRI_VVV0UU2, INSTR_VRI_VVV0UU2, 2, 12, 0, "vector pack zoned register" }, + { "vtp", OP48(0xe6000000005fLL), MASK_VRR_0V0U, INSTR_VRR_0V0U, 2, 13, 1, "vector test decimal" }, + { "vtp", OP48(0xe6000000005fLL), MASK_VRR_0V, INSTR_VRR_0V, 2, 10, 0, "vector test decimal" }, + { "vclfnl", OP48(0xe6000000005eLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 12, 0, "vector fp convert and lengthen from nnp low" }, + { "vcfn", OP48(0xe6000000005dLL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 12, 0, "vector fp convert from nnp" }, + { "vupkzl", OP48(0xe6000000005cLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 12, 0, "vector unpack zoned low" }, + { "vpsop", OP48(0xe6000000005bLL), MASK_VRI_VVUUU2, INSTR_VRI_VVUUU2, 2, 10, 0, "vector perform sign operation decimal" }, + { "vcvdg", OP48(0xe6000000005aLL), MASK_VRI_VR0UU, INSTR_VRI_VR0UU, 2, 10, 0, "vector convert to decimal 64 bit" }, + { "vsrp", OP48(0xe60000000059LL), MASK_VRI_VVUUU2, INSTR_VRI_VVUUU2, 2, 10, 0, "vector shift and round decimal" }, + { "vcvd", OP48(0xe60000000058LL), MASK_VRI_VR0UU, INSTR_VRI_VR0UU, 2, 10, 0, "vector convert to decimal 32 bit" }, + { "vclfnh", OP48(0xe60000000056LL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 12, 0, "vector fp convert and lengthen from nnp high" }, + { "vcnf", OP48(0xe60000000055LL), MASK_VRR_VV0UU2, INSTR_VRR_VV0UU2, 2, 12, 0, "vector fp convert to nnp" }, + { "vupkzh", OP48(0xe60000000054LL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 12, 0, "vector unpack zoned high" }, + { "vcvbg", OP48(0xe60000000052LL), MASK_VRR_RV0UU, INSTR_VRR_RV0UU, 2, 11, 1, "vector convert to binary 64 bit" }, + { "vcvbg", OP48(0xe60000000052LL), MASK_VRR_RV0U, INSTR_VRR_RV0U, 2, 10, 0, "vector convert to binary 64 bit" }, + { "vclzdp", OP48(0xe60000000051LL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 12, 0, "vector count leading zero digits" }, + { "vcvb", OP48(0xe60000000050LL), MASK_VRR_RV0UU, INSTR_VRR_RV0UU, 2, 11, 1, "vector convert to binary 32 bit" }, + { "vcvb", OP48(0xe60000000050LL), MASK_VRR_RV0U, INSTR_VRR_RV0U, 2, 10, 0, "vector convert to binary 32 bit" }, + { "vcvbq", OP48(0xe6000000004eLL), MASK_VRR_VV0U2, INSTR_VRR_VV0U2, 2, 13, 0, "vector convert to binary 128 bit" }, + { "vcvdq", OP48(0xe6000000004aLL), MASK_VRI_VV0UU, INSTR_VRI_VV0UU, 2, 13, 0, "vector convert to decimal 128 bit" }, + { "vlip", OP48(0xe60000000049LL), MASK_VRI_V0UU2, INSTR_VRI_V0UU2, 2, 10, 0, "vector load immediate decimal" }, + { "vstrlr", OP48(0xe6000000003fLL), MASK_VRS_RRDV, INSTR_VRS_RRDV, 2, 10, 0, "vector store rightmost with length" }, + { "vstrl", OP48(0xe6000000003dLL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0, "vector store rightmost with immediate length" }, + { "vupkz", OP48(0xe6000000003cLL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0, "vector unpack zoned" }, + { "vlrlr", OP48(0xe60000000037LL), MASK_VRS_RRDV, INSTR_VRS_RRDV, 2, 10, 0, "vector load rightmost with length" }, + { "vlrl", OP48(0xe60000000035LL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0, "vector load rightmost with immediate length" }, + { "vpkz", OP48(0xe60000000034LL), MASK_VSI_URDV, INSTR_VSI_URDV, 2, 10, 0, "vector pack zoned" }, + { "vster", OP48(0xe6000000000fLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector store elements reversed" }, + { "vstbr", OP48(0xe6000000000eLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector store byte reversed elements" }, + { "vstebrf", OP48(0xe6000000000bLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector store byte reversed word element" }, + { "sterv", OP48(0xe6000000000bLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "store byte reversed word" }, + { "vstebrg", OP48(0xe6000000000aLL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector store byte reversed doubleword element" }, + { "stdrv", OP48(0xe6000000000aLL), MASK_VRX_VRRD, INSTR_VRX_VRRD, 2, 11, 0, "store byte reversed doubleword" }, + { "vstebrh", OP48(0xe60000000009LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector store byte reversed halfword element" }, + { "vler", OP48(0xe60000000007LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load elements reversed" }, + { "vlbr", OP48(0xe60000000006LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load byte reversed elements" }, + { "vlbrrep", OP48(0xe60000000005LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load byte reversed element and replicate" }, + { "vllebrz", OP48(0xe60000000004LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load byte reversed element and zero" }, + { "vlebrf", OP48(0xe60000000003LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load byte reversed word element" }, + { "vlebrg", OP48(0xe60000000002LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load byte reversed doubleword element" }, + { "vlebrh", OP48(0xe60000000001LL), MASK_VRX_VRRDU, INSTR_VRX_VRRDU, 2, 11, 0, "vector load byte reversed halfword element" }, + { "tbeginc", OP16(0xe561LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 8, 4, "constrained transaction begin" }, + { "tbegin", OP16(0xe560LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 8, 4, "transaction begin" }, + { "clfhsi", OP16(0xe55dLL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6, 0, "compare logical immediate (32<16)" }, + { "chsi", OP16(0xe55cLL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0, "compare halfword immediate (32<16)" }, + { "clghsi", OP16(0xe559LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6, 0, "compare logical immediate (64<16)" }, + { "cghsi", OP16(0xe558LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0, "compare halfword immediate (64<16)" }, + { "clhhsi", OP16(0xe555LL), MASK_SIL_RDU, INSTR_SIL_RDU, 2, 6, 0, "compare logical immediate (16<16)" }, + { "chhsi", OP16(0xe554LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0, "compare halfword immediate (16<16)" }, + { "mvhi", OP16(0xe54cLL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0, "move (32<16)" }, + { "mvghi", OP16(0xe548LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0, "move (64<16)" }, + { "mvhhi", OP16(0xe544LL), MASK_SIL_RDI, INSTR_SIL_RDI, 2, 6, 0, "move (16<16)" }, + { "mvcdk", OP16(0xe50fLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, "move with destination key" }, + { "mvcsk", OP16(0xe50eLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, "move with source key" }, + { "mvcrl", OP16(0xe50aLL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 11, 0, "move right to left" }, + { "strag", OP16(0xe502LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 2, 2, 0, "store read address" }, + { "tprot", OP16(0xe501LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, "test protection" }, + { "lasp", OP16(0xe500LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0, 0, "load address space parameters" }, + { "bi", OP48(0xe3f000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "unconditional indirect branch" }, + { "bino", OP48(0xe3e000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not overflow / if not ones" }, + { "binh", OP48(0xe3d000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on A not high" }, + { "binp", OP48(0xe3d000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not plus" }, + { "bile", OP48(0xe3c000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on low or equal" }, + { "binl", OP48(0xe3b000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on A not low" }, + { "binm", OP48(0xe3b000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not minus / if not mixed" }, + { "bihe", OP48(0xe3a000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on high or equal" }, + { "binlh", OP48(0xe39000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not low or high" }, + { "bie", OP48(0xe38000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on A equal B" }, + { "biz", OP48(0xe38000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on zero / if zeros" }, + { "bine", OP48(0xe37000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on A not equal B" }, + { "binz", OP48(0xe37000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not zero / if not zeros" }, + { "bilh", OP48(0xe36000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on low or high" }, + { "binhe", OP48(0xe35000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not high or equal" }, + { "bil", OP48(0xe34000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on A low" }, + { "bim", OP48(0xe34000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on minus / if mixed" }, + { "binle", OP48(0xe33000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on not low or equal" }, + { "bih", OP48(0xe32000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on A high" }, + { "bip", OP48(0xe32000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on plus" }, + { "bio", OP48(0xe31000000047LL), MASK_RXY_0RRD, INSTR_RXY_0RRD, 2, 10, 0, "branch indirect on condition on overflow / if ones" }, + { "clhf", OP48(0xe300000000cfLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "compare logical high" }, + { "chf", OP48(0xe300000000cdLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "compare high" }, + { "stfh", OP48(0xe300000000cbLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "store high" }, + { "lfh", OP48(0xe300000000caLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "load high" }, + { "lfhat", OP48(0xe300000000c8LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0, "load high and trap" }, + { "sthh", OP48(0xe300000000c7LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "store halfword high" }, + { "llhh", OP48(0xe300000000c6LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "load logical halfword high" }, + { "lhh", OP48(0xe300000000c4LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "load halfword high" }, + { "stch", OP48(0xe300000000c3LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "store character high" }, + { "llch", OP48(0xe300000000c2LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "load logical character high" }, + { "lbh", OP48(0xe300000000c0LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 7, 0, "load byte high" }, + { "lat", OP48(0xe3000000009fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0, "load and trap 32 bit" }, + { "llgfat", OP48(0xe3000000009dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0, "load logical and trap 32>64" }, + { "llgtat", OP48(0xe3000000009cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0, "load logical thirty one bits and trap 31>64" }, + { "slb", OP48(0xe30000000099LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, "subtract logical with borrow 32" }, + { "slb", OP48(0xe30000000099LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0, "subtract logical with borrow 32" }, + { "alc", OP48(0xe30000000098LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, "add logical with carry 32" }, + { "alc", OP48(0xe30000000098LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0, "add logical with carry 32" }, + { "dl", OP48(0xe30000000097LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 3, 3, 0, "divide logical 32" }, + { "dl", OP48(0xe30000000097LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 3, 2, 0, "divide logical 32" }, + { "ml", OP48(0xe30000000096LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 3, 3, 0, "multiply logical 32" }, + { "ml", OP48(0xe30000000096LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 3, 2, 0, "multiply logical 32" }, + { "llh", OP48(0xe30000000095LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0, "load logical halfword 32" }, + { "llc", OP48(0xe30000000094LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0, "load logical character 32" }, + { "llgh", OP48(0xe30000000091LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load logical halfword" }, + { "llgh", OP48(0xe30000000091LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load logical halfword" }, + { "llgc", OP48(0xe30000000090LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load logical character" }, + { "llgc", OP48(0xe30000000090LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load logical character" }, + { "lpq", OP48(0xe3000000008fLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0, "load pair from quadword" }, + { "lpq", OP48(0xe3000000008fLL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0, "load pair from quadword" }, + { "stpq", OP48(0xe3000000008eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store pair to quadword" }, + { "stpq", OP48(0xe3000000008eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "store pair to quadword" }, + { "slbg", OP48(0xe30000000089LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract logical with borrow 64" }, + { "slbg", OP48(0xe30000000089LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "subtract logical with borrow 64" }, + { "alcg", OP48(0xe30000000088LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add logical with carry 64" }, + { "alcg", OP48(0xe30000000088LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "add logical with carry 64" }, + { "dlg", OP48(0xe30000000087LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0, "divide logical 64" }, + { "dlg", OP48(0xe30000000087LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0, "divide logical 64" }, + { "mlg", OP48(0xe30000000086LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0, "multiply logical 64" }, + { "mlg", OP48(0xe30000000086LL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0, "multiply logical 64" }, + { "lgat", OP48(0xe30000000085LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 0, "load and trap 64 bit" }, + { "mg", OP48(0xe30000000084LL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 10, 0, "multiply 64x64mem -> 128" }, + { "msgc", OP48(0xe30000000083LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "multiply single 64x64mem -> 64" }, + { "xg", OP48(0xe30000000082LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "exclusive or with long offset 64" }, + { "xg", OP48(0xe30000000082LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "exclusive or 64" }, + { "og", OP48(0xe30000000081LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "or with long offset 64" }, + { "og", OP48(0xe30000000081LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "or 64" }, + { "ng", OP48(0xe30000000080LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "and with long offset 64" }, + { "ng", OP48(0xe30000000080LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "and 64" }, + { "mhy", OP48(0xe3000000007cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0, "multiply halfword" }, + { "shy", OP48(0xe3000000007bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract halfword with long offset" }, + { "ahy", OP48(0xe3000000007aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add halfword with long offset" }, + { "chy", OP48(0xe30000000079LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare halfword with long offset" }, + { "lhy", OP48(0xe30000000078LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load halfword with long offset" }, + { "lgb", OP48(0xe30000000077LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load byte with long offset 64" }, + { "lb", OP48(0xe30000000076LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load byte with long offset" }, + { "laey", OP48(0xe30000000075LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0, "load address extended" }, + { "icy", OP48(0xe30000000073LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "insert character with long offset" }, + { "stcy", OP48(0xe30000000072LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store character with long offset" }, + { "lay", OP48(0xe30000000071LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load address with long offset" }, + { "sthy", OP48(0xe30000000070LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store halfword with long offset" }, + { "llxaq", OP48(0xe30000000069LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load logical indexed address (shift left 4)" }, + { "lxaq", OP48(0xe30000000068LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load indexed address (shift left 4)" }, + { "llxag", OP48(0xe30000000067LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load logical indexed address (shift left 3)" }, + { "lxag", OP48(0xe30000000066LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load indexed address (shift left 3)" }, + { "llxaf", OP48(0xe30000000065LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load logical indexed address (shift left 2)" }, + { "lxaf", OP48(0xe30000000064LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load indexed address (shift left 2)" }, + { "llxah", OP48(0xe30000000063LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load logical indexed address (shift left 1)" }, + { "lxah", OP48(0xe30000000062LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load indexed address (shift left 1)" }, + { "llxab", OP48(0xe30000000061LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load logical indexed address (shift left 0)" }, + { "lxab", OP48(0xe30000000060LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 13, 0, "load indexed address (shift left 0)" }, + { "sly", OP48(0xe3000000005fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract logical with long offset" }, + { "aly", OP48(0xe3000000005eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add logical with long offset" }, + { "mfy", OP48(0xe3000000005cLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 6, 0, "multiply" }, + { "sy", OP48(0xe3000000005bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract with long offset" }, + { "ay", OP48(0xe3000000005aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add with long offset" }, + { "cy", OP48(0xe30000000059LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare with long offset" }, + { "ly", OP48(0xe30000000058LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load with long offset" }, + { "xy", OP48(0xe30000000057LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "exclusive or with long offset" }, + { "oy", OP48(0xe30000000056LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "or with long offset" }, + { "cly", OP48(0xe30000000055LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare logical with long offset" }, + { "ny", OP48(0xe30000000054LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "and with long offset" }, + { "msc", OP48(0xe30000000053LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "multiply single 32x32mem -> 32" }, + { "msy", OP48(0xe30000000051LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "multiply single with long offset" }, + { "sty", OP48(0xe30000000050LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store with long offset" }, + { "lgsc", OP48(0xe3000000004dLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "load guarded storage controls" }, + { "lgg", OP48(0xe3000000004cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "load guarded 64 bit" }, + { "stgsc", OP48(0xe30000000049LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "store guarded storage controls" }, + { "llgfsg", OP48(0xe30000000048LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "load logical and shift guarded 64 bit" }, + { "bic", OP48(0xe30000000047LL), MASK_RXY_URRD, INSTR_RXY_URRD, 2, 10, 0, "branch indirect on condition" }, + { "bctg", OP48(0xe30000000046LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "branch on count 64" }, + { "bctg", OP48(0xe30000000046LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "branch on count 64" }, + { "strvh", OP48(0xe3000000003fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store reversed 64" }, + { "strvh", OP48(0xe3000000003fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0, "store reversed 64" }, + { "strv", OP48(0xe3000000003eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, "store reversed 32" }, + { "strv", OP48(0xe3000000003eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0, "store reversed 32" }, + { "mgh", OP48(0xe3000000003cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "multiply halfword 64x16mem -> 64" }, + { "lzrf", OP48(0xe3000000003bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 9, 0, "load and zero rightmost byte 32->32" }, + { "llzrgf", OP48(0xe3000000003aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 9, 0, "load logical and zero rightmost bytes 32->64" }, + { "sgh", OP48(0xe30000000039LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "subtract halfword from 64 bit value" }, + { "agh", OP48(0xe30000000038LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 10, 0, "add halfword to 64 bit value" }, + { "pfd", OP48(0xe30000000036LL), MASK_RXY_URRD, INSTR_RXY_URRD, 2, 6, 0, "prefetch data" }, + { "cgh", OP48(0xe30000000034LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0, "compare halfword (64<16)" }, + { "ltgf", OP48(0xe30000000032LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 6, 0, "load and test (64<32)" }, + { "clgf", OP48(0xe30000000031LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare logical with long offset 64<32" }, + { "clgf", OP48(0xe30000000031LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "compare logical 64<32" }, + { "cgf", OP48(0xe30000000030LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare with long offset 64<32" }, + { "cgf", OP48(0xe30000000030LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "compare 64<32" }, + { "strvg", OP48(0xe3000000002fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store reversed 64" }, + { "strvg", OP48(0xe3000000002fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "store reversed 64" }, + { "cvdg", OP48(0xe3000000002eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "convert to decimal with long offset 64" }, + { "cvdg", OP48(0xe3000000002eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "convert to decimal 64" }, + { "lzrg", OP48(0xe3000000002aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 9, 0, "load and zero rightmost byte 64->64" }, + { "cvdy", OP48(0xe30000000026LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "convert to decimal with long offset" }, + { "ntstg", OP48(0xe30000000025LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 8, 4, "nontransactional store" }, + { "stg", OP48(0xe30000000024LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "store with long offset 64" }, + { "stg", OP48(0xe30000000024LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "store 64" }, + { "clg", OP48(0xe30000000021LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare logical with long offset 64" }, + { "clg", OP48(0xe30000000021LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "compare logical 64" }, + { "cg", OP48(0xe30000000020LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "compare with long offset 64" }, + { "cg", OP48(0xe30000000020LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "compare 64" }, + { "lrvh", OP48(0xe3000000001fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, "load reversed 16" }, + { "lrvh", OP48(0xe3000000001fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0, "load reversed 16" }, + { "lrv", OP48(0xe3000000001eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3, 0, "load reversed 32" }, + { "lrv", OP48(0xe3000000001eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 2, 0, "load reversed 32" }, + { "dsgf", OP48(0xe3000000001dLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0, "divide single 64<32" }, + { "dsgf", OP48(0xe3000000001dLL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0, "divide single 64<32" }, + { "msgf", OP48(0xe3000000001cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "multiply single with long offset 64<32" }, + { "msgf", OP48(0xe3000000001cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "multiply single 64<32" }, + { "slgf", OP48(0xe3000000001bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract logical with long offset 64<32" }, + { "slgf", OP48(0xe3000000001bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "subtract logical 64<32" }, + { "algf", OP48(0xe3000000001aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add logical with long offset 64<32" }, + { "algf", OP48(0xe3000000001aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "add logical 64<32" }, + { "sgf", OP48(0xe30000000019LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract with long offset 64<32" }, + { "sgf", OP48(0xe30000000019LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "subtract 64<32" }, + { "agf", OP48(0xe30000000018LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add with long offset 64<32" }, + { "agf", OP48(0xe30000000018LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "add 64<32" }, + { "llgt", OP48(0xe30000000017LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load logical thirty one bits" }, + { "llgt", OP48(0xe30000000017LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load logical thirty one bits" }, + { "llgf", OP48(0xe30000000016LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load logical 64<32" }, + { "llgf", OP48(0xe30000000016LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load logical 64<32" }, + { "lgh", OP48(0xe30000000015LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load halfword 64" }, + { "lgh", OP48(0xe30000000015LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load halfword 64" }, + { "lgf", OP48(0xe30000000014LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load 64<32" }, + { "lgf", OP48(0xe30000000014LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load 64<32" }, + { "lray", OP48(0xe30000000013LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load real address with long offset" }, + { "lt", OP48(0xe30000000012LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0, "load and test 32" }, + { "lrvg", OP48(0xe3000000000fLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load reversed 64" }, + { "lrvg", OP48(0xe3000000000fLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load reversed 64" }, + { "cvbg", OP48(0xe3000000000eLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "convert to binary with long offset 64" }, + { "cvbg", OP48(0xe3000000000eLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "convert to binary 64" }, + { "dsg", OP48(0xe3000000000dLL), MASK_RXY_RERRD, INSTR_RXY_RERRD, 2, 3, 0, "divide single 64" }, + { "dsg", OP48(0xe3000000000dLL), MASK_RXE_RERRD, INSTR_RXE_RERRD, 2, 2, 0, "divide single 64" }, + { "msg", OP48(0xe3000000000cLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "multiply single with long offset 64" }, + { "msg", OP48(0xe3000000000cLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "multiply single 64" }, + { "slg", OP48(0xe3000000000bLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract logical with long offset 64" }, + { "slg", OP48(0xe3000000000bLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "subtract logical 64" }, + { "alg", OP48(0xe3000000000aLL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add logical with long offset 64" }, + { "alg", OP48(0xe3000000000aLL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "add logical 64" }, + { "sg", OP48(0xe30000000009LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "subtract with long offset 64" }, + { "sg", OP48(0xe30000000009LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "subtract 64" }, + { "ag", OP48(0xe30000000008LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "add with long offset 64" }, + { "ag", OP48(0xe30000000008LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "add 64" }, + { "cvby", OP48(0xe30000000006LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "convert to binary with long offset" }, + { "lg", OP48(0xe30000000004LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load 64" }, + { "lg", OP48(0xe30000000004LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load 64" }, + { "lrag", OP48(0xe30000000003LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 3, 0, "load real address with long offset 64" }, + { "lrag", OP48(0xe30000000003LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 2, 2, 0, "load real address 64" }, + { "ltg", OP48(0xe30000000002LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 2, 4, 0, "load and test 64" }, + { "unpku", OP8(0xe2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "unpack unicode" }, + { "pku", OP8(0xe1LL), MASK_SS_L2RDRD, INSTR_SS_L2RDRD, 3, 0, 0, "pack unicode" }, + { "edmk", OP8(0xdfLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "edit and mark" }, + { "ed", OP8(0xdeLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "edit" }, + { "trt", OP8(0xddLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "translate and test" }, + { "tr", OP8(0xdcLL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "translate" }, + { "mvcs", OP8(0xdbLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, "move to secondary" }, + { "mvcp", OP8(0xdaLL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, "move to primary" }, + { "mvck", OP8(0xd9LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD, 3, 0, 0, "move with key" }, + { "xc", OP8(0xd7LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "exclusive or" }, + { "oc", OP8(0xd6LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "or" }, + { "clc", OP8(0xd5LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "compare logical" }, + { "nc", OP8(0xd4LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "and" }, + { "mvz", OP8(0xd3LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "move zones" }, + { "mvc", OP8(0xd2LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "move" }, + { "mvn", OP8(0xd1LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 3, 0, 0, "move numerics" }, + { "trtr", OP8(0xd0LL), MASK_SS_L0RDRD, INSTR_SS_L0RDRD, 2, 4, 0, "tranlate and test reverse" }, + { "clih", OP16(0xcc0fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 7, 0, "compare logical immediate" }, + { "cih", OP16(0xcc0dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0, "compare immediate high" }, + { "alsihn", OP16(0xcc0bLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0, "add logical with signed immediate high no cc" }, + { "alsih", OP16(0xcc0aLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0, "add logical with signed immediate high with cc" }, + { "aih", OP16(0xcc08LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 7, 0, "add immediate high" }, + { "brcth", OP16(0xcc06LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 7, 112, "branch relative on count high" }, + { "jcth", OP16(0xcc06LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 7, 112, "jump on count high" }, + { "calgf", OP16(0xc80fLL), MASK_SSF_RRDRD2, INSTR_SSF_RRDRD2, 2, 13, 0, "compare and load 64<32" }, + { "calg", OP16(0xc807LL), MASK_SSF_RRDRD2, INSTR_SSF_RRDRD2, 2, 13, 0, "compare and load 64" }, + { "cal", OP16(0xc806LL), MASK_SSF_RRDRD2, INSTR_SSF_RRDRD2, 2, 13, 0, "compare and load 32" }, + { "lpdg", OP16(0xc805LL), MASK_SSF_RERDRD2, INSTR_SSF_RERDRD2, 2, 7, 0, "load pair disjoint 64 bit" }, + { "lpd", OP16(0xc804LL), MASK_SSF_RERDRD2, INSTR_SSF_RERDRD2, 2, 7, 0, "load pair disjoint 32 bit" }, + { "csst", OP16(0xc802LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5, 0, "compare and swap and store" }, + { "ectg", OP16(0xc801LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 5, 0, "extract cpu time" }, + { "mvcos", OP16(0xc800LL), MASK_SSF_RRDRD, INSTR_SSF_RRDRD, 2, 4, 0, "move with optional specifications" }, + { "bpp", OP8(0xc7LL), MASK_SMI_U0RDP, INSTR_SMI_U0RDP, 2, 8, 0, "branch prediction preload" }, + { "clrl", OP16(0xc60fLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare logical relative long (32)" }, + { "clgfrl", OP16(0xc60eLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare logical relative long (64<32)" }, + { "crl", OP16(0xc60dLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare relative long (32)" }, + { "cgfrl", OP16(0xc60cLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare relative long (64<32)" }, + { "clgrl", OP16(0xc60aLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare logical relative long (64)" }, + { "cgrl", OP16(0xc608LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare relative long (64)" }, + { "clhrl", OP16(0xc607LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare logical relative long (32<16)" }, + { "clghrl", OP16(0xc606LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare logical relative long (64<16)" }, + { "chrl", OP16(0xc605LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare halfword relative long (32<8)" }, + { "cghrl", OP16(0xc604LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "compare halfword relative long (64<8)" }, + { "pfdrl", OP16(0xc602LL), MASK_RIL_UP, INSTR_RIL_UP, 2, 6, 0, "prefetch data relative long" }, + { "exrl", OP16(0xc600LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "execute relative long" }, + { "bprp", OP8(0xc5LL), MASK_MII_UPP, INSTR_MII_UPP, 2, 8, 0, "branch prediction relative preload" }, + { "strl", OP16(0xc40fLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "store relative long (32)" }, + { "llgfrl", OP16(0xc40eLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load logical relative long (64<32)" }, + { "lrl", OP16(0xc40dLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load relative long (32)" }, + { "lgfrl", OP16(0xc40cLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load relative long (64<32)" }, + { "stgrl", OP16(0xc40bLL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "store relative long (64)" }, + { "lgrl", OP16(0xc408LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load relative long (64)" }, + { "sthrl", OP16(0xc407LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "store halfword relative long" }, + { "llghrl", OP16(0xc406LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load logical halfword relative long (64<16)" }, + { "lhrl", OP16(0xc405LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load halfword relative long (32<16)" }, + { "lghrl", OP16(0xc404LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load halfword relative long (64<16)" }, + { "llhrl", OP16(0xc402LL), MASK_RIL_RP, INSTR_RIL_RP, 2, 6, 0, "load logical halfword relative long (32<16)" }, + { "clfi", OP16(0xc20fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "compare logical immediate 32" }, + { "clgfi", OP16(0xc20eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "compare logical immediate 64<32" }, + { "cfi", OP16(0xc20dLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0, "compare immediate 32" }, + { "cgfi", OP16(0xc20cLL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0, "compare immediate 64<32" }, + { "alfi", OP16(0xc20bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "add logical immediate 32" }, + { "algfi", OP16(0xc20aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "add logical immediate 64<32" }, + { "afi", OP16(0xc209LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0, "add immediate 32" }, + { "agfi", OP16(0xc208LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0, "add immediate 64<32" }, + { "slfi", OP16(0xc205LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "subtract logical immediate 32" }, + { "slgfi", OP16(0xc204LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "subtract logical immediate 64<32" }, + { "msfi", OP16(0xc201LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 6, 0, "multiply single immediate (32)" }, + { "msgfi", OP16(0xc200LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 6, 0, "multiply single immediate (64)" }, + { "jg", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 48, "unconditional jump long" }, + { "brul", OP16(0xc0f4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 48, "unconditional jump long" }, + { "jgno", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not overflow / if not ones" }, + { "brnol", OP16(0xc0e4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not overflow / if not ones" }, + { "jgnh", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A not high" }, + { "jgnp", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not plus" }, + { "brnhl", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A not high" }, + { "brnpl", OP16(0xc0d4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not plus" }, + { "jgle", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on low or equal" }, + { "brlel", OP16(0xc0c4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on low or equal" }, + { "jgnl", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A not low" }, + { "jgnm", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not minus / if not mixed" }, + { "brnll", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A not low" }, + { "brnml", OP16(0xc0b4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not minus / if not mixed" }, + { "jghe", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on high or equal" }, + { "brhel", OP16(0xc0a4LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on high or equal" }, + { "jgnlh", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not low or high" }, + { "brnlhl", OP16(0xc094LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not low or high" }, + { "jge", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A equal B" }, + { "jgz", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on zero / if zeros" }, + { "brel", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A equal B" }, + { "brzl", OP16(0xc084LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on zero / if zeros" }, + { "jgne", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A not equal B" }, + { "jgnz", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not zero / if not zeros" }, + { "brnel", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A not equal B" }, + { "brnzl", OP16(0xc074LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not zero / if not zeros" }, + { "jglh", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on low or high" }, + { "brlhl", OP16(0xc064LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on low or high" }, + { "jgnhe", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not high or equal" }, + { "brnhel", OP16(0xc054LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not high or equal" }, + { "jgl", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A low" }, + { "jgm", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on minus / if mixed" }, + { "brll", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A low" }, + { "brml", OP16(0xc044LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on minus / if mixed" }, + { "jgnle", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not low or equal" }, + { "brnlel", OP16(0xc034LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on not low or equal" }, + { "jgh", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A high" }, + { "jgp", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on plus" }, + { "brhl", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on A high" }, + { "brpl", OP16(0xc024LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on plus" }, + { "jgo", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on overflow / if ones" }, + { "brol", OP16(0xc014LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 112, "conditional jump long on overflow / if ones" }, + { "llilf", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "load logical immediate low" }, + { "llgfi", OP16(0xc00fLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "load logical immediate" }, + { "llihf", OP16(0xc00eLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "load logical immediate high" }, + { "oilf", OP16(0xc00dLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "or immediate low" }, + { "oihf", OP16(0xc00cLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "or immediate high" }, + { "nilf", OP16(0xc00bLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "and immediate low" }, + { "nihf", OP16(0xc00aLL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "and immediate high" }, + { "iilf", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "insert immediate low" }, + { "lfi", OP16(0xc009LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "insert immediate 32" }, + { "iihf", OP16(0xc008LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "insert immediate high" }, + { "xilf", OP16(0xc007LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "exclusive or immediate low" }, + { "xihf", OP16(0xc006LL), MASK_RIL_RU, INSTR_RIL_RU, 2, 4, 0, "exclusive or immediate high" }, + { "brasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2, 176, "branch relative and save long" }, + { "jasl", OP16(0xc005LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2, 176, "branch relative and save long" }, + { "brcl", OP16(0xc004LL), MASK_RIL_UP, INSTR_RIL_UP, 3, 2, 112, "branch relative on condition long" }, + { "jgnop", OP16(0xc004LL), MASK_RIL_0P, INSTR_RIL_0P, 3, 2, 0, "nop jump long" }, + { "lgfi", OP16(0xc001LL), MASK_RIL_RI, INSTR_RIL_RI, 2, 4, 0, "load immediate 64<32" }, + { "larl", OP16(0xc000LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 2, 0, "load address relative long" }, + { "icm", OP8(0xbfLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0, 0, "insert characters under mask" }, + { "stcm", OP8(0xbeLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0, 0, "store characters under mask" }, + { "clm", OP8(0xbdLL), MASK_RS_RURD, INSTR_RS_RURD, 3, 0, 0, "compare logical characters under mask" }, + { "cds", OP8(0xbbLL), MASK_RS_RERERD, INSTR_RS_RERERD, 3, 0, 0, "compare double and swap" }, + { "cs", OP8(0xbaLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "compare and swap" }, + { "msrkc", OP16(0xb9fdLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 10, 0, "multiply single 32x32 -> 32" }, + { "slrk", OP16(0xb9fbLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract logical 3 operands 32 bit" }, + { "alrk", OP16(0xb9faLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add logical 3 operands 32 bit" }, + { "srk", OP16(0xb9f9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract 3 operands 32 bit" }, + { "ark", OP16(0xb9f8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add 3 operands 32 bit" }, + { "xrk", OP16(0xb9f7LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "xor 3 operands 32 bit" }, + { "ork", OP16(0xb9f6LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "or 3 operands 32 bit" }, + { "ncrk", OP16(0xb9f5LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "and with complement 32 bit" }, + { "nrk", OP16(0xb9f4LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "and 3 operands 32 bit" }, + { "locrno", OP32(0xb9f2e000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not overflow / if not ones" }, + { "locrnh", OP32(0xb9f2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on A not high" }, + { "locrnp", OP32(0xb9f2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not plus" }, + { "locrle", OP32(0xb9f2c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on low or equal" }, + { "locrnl", OP32(0xb9f2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on A not low" }, + { "locrnm", OP32(0xb9f2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not minus / if not mixed" }, + { "locrhe", OP32(0xb9f2a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on high or equal" }, + { "locrnlh", OP32(0xb9f29000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not low or high" }, + { "locre", OP32(0xb9f28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on A equal B" }, + { "locrz", OP32(0xb9f28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on zero / if zeros" }, + { "locrne", OP32(0xb9f27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on A not equal B" }, + { "locrnz", OP32(0xb9f27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not zero / if not zeros" }, + { "locrlh", OP32(0xb9f26000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on low or high" }, + { "locrnhe", OP32(0xb9f25000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not high or equal" }, + { "locrl", OP32(0xb9f24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on A low" }, + { "locrm", OP32(0xb9f24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on minus / if mixed" }, + { "locrnle", OP32(0xb9f23000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on not low or equal" }, + { "locrh", OP32(0xb9f22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on A high" }, + { "locrp", OP32(0xb9f22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on plus" }, + { "locro", OP32(0xb9f21000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 32 bit on overflow / if ones" }, + { "locr", OP16(0xb9f2LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 7, 0, "load on condition 32 bit" }, + { "selrno", OP32(0xb9f00e00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not overflow / if not ones" }, + { "selrnh", OP32(0xb9f00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on A not high" }, + { "selrnp", OP32(0xb9f00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not plus" }, + { "selrle", OP32(0xb9f00c00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on low or equal" }, + { "selrnl", OP32(0xb9f00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on A not low" }, + { "selrnm", OP32(0xb9f00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not minus / if not mixed" }, + { "selrhe", OP32(0xb9f00a00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on high or equal" }, + { "selrnlh", OP32(0xb9f00900LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not low or high" }, + { "selre", OP32(0xb9f00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on A equal B" }, + { "selrz", OP32(0xb9f00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on zero / if zeros" }, + { "selrne", OP32(0xb9f00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on A not equal B" }, + { "selrnz", OP32(0xb9f00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not zero / if not zeros" }, + { "selrlh", OP32(0xb9f00600LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on low or high" }, + { "selrnhe", OP32(0xb9f00500LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not high or equal" }, + { "selrl", OP32(0xb9f00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on A low" }, + { "selrm", OP32(0xb9f00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on minus / if mixed" }, + { "selrnle", OP32(0xb9f00300LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on not low or equal" }, + { "selrh", OP32(0xb9f00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on A high" }, + { "selrp", OP32(0xb9f00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on plus" }, + { "selro", OP32(0xb9f00100LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 32 bit on overflow / if ones" }, + { "selr", OP16(0xb9f0LL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 11, 0, "select 32 bit" }, + { "msgrkc", OP16(0xb9edLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 10, 0, "multiply single 64x64 -> 64" }, + { "mgrk", OP16(0xb9ecLL), MASK_RRF_R0RER, INSTR_RRF_R0RER, 2, 10, 0, "multiply 64x64reg -> 128" }, + { "slgrk", OP16(0xb9ebLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract logical 3 operands 64 bit" }, + { "algrk", OP16(0xb9eaLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add logical 3 operands 64 bit" }, + { "sgrk", OP16(0xb9e9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract 3 operands 64 bit" }, + { "agrk", OP16(0xb9e8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add 3 operands 64 bit" }, + { "xgrk", OP16(0xb9e7LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "xor 3 operands 64 bit" }, + { "ogrk", OP16(0xb9e6LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "or 3 operands 64 bit" }, + { "ncgrk", OP16(0xb9e5LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "and with complement 64 bit" }, + { "ngrk", OP16(0xb9e4LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "and 3 operands 64 bit" }, + { "selgrno", OP32(0xb9e30e00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not overflow / if not ones" }, + { "selgrnh", OP32(0xb9e30d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on A not high" }, + { "selgrnp", OP32(0xb9e30d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not plus" }, + { "selgrle", OP32(0xb9e30c00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on low or equal" }, + { "selgrnl", OP32(0xb9e30b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on A not low" }, + { "selgrnm", OP32(0xb9e30b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not minus / if not mixed" }, + { "selgrhe", OP32(0xb9e30a00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on high or equal" }, + { "selgrnlh", OP32(0xb9e30900LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not low or high" }, + { "selgre", OP32(0xb9e30800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on A equal B" }, + { "selgrz", OP32(0xb9e30800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on zero / if zeros" }, + { "selgrne", OP32(0xb9e30700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on A not equal B" }, + { "selgrnz", OP32(0xb9e30700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not zero / if not zeros" }, + { "selgrlh", OP32(0xb9e30600LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on low or high" }, + { "selgrnhe", OP32(0xb9e30500LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not high or equal" }, + { "selgrl", OP32(0xb9e30400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on A low" }, + { "selgrm", OP32(0xb9e30400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on minus / if mixed" }, + { "selgrnle", OP32(0xb9e30300LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on not low or equal" }, + { "selgrh", OP32(0xb9e30200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on A high" }, + { "selgrp", OP32(0xb9e30200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on plus" }, + { "selgro", OP32(0xb9e30100LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select 64 bit on overflow / if ones" }, + { "selgr", OP16(0xb9e3LL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 11, 0, "select 64 bit" }, + { "locgrno", OP32(0xb9e2e000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not overflow / if not ones" }, + { "locgrnh", OP32(0xb9e2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on A not high" }, + { "locgrnp", OP32(0xb9e2d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not plus" }, + { "locgrle", OP32(0xb9e2c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on low or equal" }, + { "locgrnl", OP32(0xb9e2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on A not low" }, + { "locgrnm", OP32(0xb9e2b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not minus / if not mixed" }, + { "locgrhe", OP32(0xb9e2a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on high or equal" }, + { "locgrnlh", OP32(0xb9e29000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not low or high" }, + { "locgre", OP32(0xb9e28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on A equal B" }, + { "locgrz", OP32(0xb9e28000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on zero / if zeros" }, + { "locgrne", OP32(0xb9e27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on A not equal B" }, + { "locgrnz", OP32(0xb9e27000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not zero / if not zeros" }, + { "locgrlh", OP32(0xb9e26000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on low or high" }, + { "locgrnhe", OP32(0xb9e25000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not high or equal" }, + { "locgrl", OP32(0xb9e24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on A low" }, + { "locgrm", OP32(0xb9e24000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on minus / if mixed" }, + { "locgrnle", OP32(0xb9e23000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on not low or equal" }, + { "locgrh", OP32(0xb9e22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on A high" }, + { "locgrp", OP32(0xb9e22000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on plus" }, + { "locgro", OP32(0xb9e21000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 7, 0, "load on condition 64 bit on overflow / if ones" }, + { "locgr", OP16(0xb9e2LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 7, 0, "load on condition 64 bit" }, + { "popcnt", OP16(0xb9e1LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 11, 1, "population count arch13" }, + { "popcnt", OP16(0xb9e1LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "population count" }, + { "locfhrno", OP32(0xb9e0e000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not overflow / if not ones" }, + { "locfhrnh", OP32(0xb9e0d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on A not high" }, + { "locfhrnp", OP32(0xb9e0d000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not plus" }, + { "locfhrle", OP32(0xb9e0c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on low or equal" }, + { "locfhrnl", OP32(0xb9e0b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on A not low" }, + { "locfhrnm", OP32(0xb9e0b000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not minus / if not mixed" }, + { "locfhrhe", OP32(0xb9e0a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on high or equal" }, + { "locfhrnlh", OP32(0xb9e09000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not low or high" }, + { "locfhre", OP32(0xb9e08000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on A equal B" }, + { "locfhrz", OP32(0xb9e08000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on zero / if zeros" }, + { "locfhrne", OP32(0xb9e07000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on A not equal B" }, + { "locfhrnz", OP32(0xb9e07000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not zero / if not zeros" }, + { "locfhrlh", OP32(0xb9e06000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on low or high" }, + { "locfhrnhe", OP32(0xb9e05000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not high or equal" }, + { "locfhrl", OP32(0xb9e04000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on A low" }, + { "locfhrm", OP32(0xb9e04000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on minus / if mixed" }, + { "locfhrnle", OP32(0xb9e03000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on not low or equal" }, + { "locfhrh", OP32(0xb9e02000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on A high" }, + { "locfhrp", OP32(0xb9e02000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on plus" }, + { "locfhro", OP32(0xb9e01000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 9, 0, "load high on condition from gpr on overflow / if ones" }, + { "locfhr", OP16(0xb9e0LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 9, 0, "load high on condition from gpr" }, + { "clhlr", OP16(0xb9dfLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "compare logical high low" }, + { "chlr", OP16(0xb9ddLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "compare high low" }, + { "slhhlr", OP16(0xb9dbLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract logical high low" }, + { "alhhlr", OP16(0xb9daLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add logical high low" }, + { "shhlr", OP16(0xb9d9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract high low" }, + { "ahhlr", OP16(0xb9d8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add high low" }, + { "clhhr", OP16(0xb9cfLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "compare logical high high" }, + { "chhr", OP16(0xb9cdLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "compare high high" }, + { "slhhhr", OP16(0xb9cbLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract logical high high" }, + { "alhhhr", OP16(0xb9caLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add logical high high" }, + { "shhhr", OP16(0xb9c9LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "subtract high high" }, + { "ahhhr", OP16(0xb9c8LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 7, 0, "add high high" }, + { "selfhrno", OP32(0xb9c00e00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not overflow / if not ones" }, + { "selfhrnh", OP32(0xb9c00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on A not high" }, + { "selfhrnp", OP32(0xb9c00d00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not plus" }, + { "selfhrle", OP32(0xb9c00c00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on low or equal" }, + { "selfhrnl", OP32(0xb9c00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on A not low" }, + { "selfhrnm", OP32(0xb9c00b00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not minus / if not mixed" }, + { "selfhrhe", OP32(0xb9c00a00LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on high or equal" }, + { "selfhrnlh", OP32(0xb9c00900LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not low or high" }, + { "selfhre", OP32(0xb9c00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on A equal B" }, + { "selfhrz", OP32(0xb9c00800LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on zero / if zeros" }, + { "selfhrne", OP32(0xb9c00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on A not equal B" }, + { "selfhrnz", OP32(0xb9c00700LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not zero / if not zeros" }, + { "selfhrlh", OP32(0xb9c00600LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on low or high" }, + { "selfhrnhe", OP32(0xb9c00500LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not high or equal" }, + { "selfhrl", OP32(0xb9c00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on A low" }, + { "selfhrm", OP32(0xb9c00400LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on minus / if mixed" }, + { "selfhrnle", OP32(0xb9c00300LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on not low or equal" }, + { "selfhrh", OP32(0xb9c00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on A high" }, + { "selfhrp", OP32(0xb9c00200LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on plus" }, + { "selfhro", OP32(0xb9c00100LL), MASK_RRF_R0RR3, INSTR_RRF_R0RR3, 2, 11, 0, "select high on overflow / if ones" }, + { "selfhr", OP16(0xb9c0LL), MASK_RRF_RURR, INSTR_RRF_RURR, 2, 11, 0, "select high" }, + { "trte", OP16(0xb9bfLL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 2, 6, 1, "translate and test extended" }, + { "srstu", OP16(0xb9beLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "search string unicode" }, + { "trtre", OP16(0xb9bdLL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 2, 6, 1, "translate and test reverse extended" }, + { "cu42", OP16(0xb9b3LL), MASK_RRE_RERE, INSTR_RRE_RERE, 2, 4, 0, "convert utf-32 to utf-16" }, + { "cu41", OP16(0xb9b2LL), MASK_RRE_RERE, INSTR_RRE_RERE, 2, 4, 0, "convert utf-32 to utf-8" }, + { "cu24", OP16(0xb9b1LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1, "convert utf-16 to utf-32" }, + { "cu14", OP16(0xb9b0LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1, "convert utf-8 to utf-32" }, + { "pfmf", OP16(0xb9afLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0, "perform frame management function" }, + { "rrbm", OP16(0xb9aeLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "reset reference bits multiple" }, + { "irbm", OP16(0xb9acLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 10, 0, "insert reference bits multiple" }, + { "lptea", OP16(0xb9aaLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 4, 0, "load page-table-entry address" }, + { "ptf", OP16(0xb9a2LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 6, 0, "perform topology function" }, + { "tpei", OP16(0xb9a1LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 10, 0, "test pending external interruption" }, + { "ssair", OP16(0xb99fLL), MASK_RRE_R0, INSTR_RRE_R0, 3, 3, 0, "set secondary ASN with instance" }, + { "pti", OP16(0xb99eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0, "program transfer with instance" }, + { "esea", OP16(0xb99dLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 2, 0, "extract and set extended authority" }, + { "esair", OP16(0xb99bLL), MASK_RRE_R0, INSTR_RRE_R0, 3, 3, 0, "extract secondary ASN and instance" }, + { "epair", OP16(0xb99aLL), MASK_RRE_R0, INSTR_RRE_R0, 3, 3, 0, "extract primary ASN and instance" }, + { "slbr", OP16(0xb999LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0, "subtract logical with borrow 32" }, + { "alcr", OP16(0xb998LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0, "add logical with carry 32" }, + { "dlr", OP16(0xb997LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 2, 0, "divide logical 32" }, + { "mlr", OP16(0xb996LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 2, 0, "multiply logical 32" }, + { "llhr", OP16(0xb995LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load logical halfword 32" }, + { "llcr", OP16(0xb994LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load logical character 32" }, + { "troo", OP16(0xb993LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1, "translate one to one" }, + { "troo", OP16(0xb993LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0, "translate one to one" }, + { "trot", OP16(0xb992LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1, "translate one to two" }, + { "trot", OP16(0xb992LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0, "translate one to two" }, + { "trto", OP16(0xb991LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1, "translate two to one" }, + { "trto", OP16(0xb991LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0, "translate two to one" }, + { "trtt", OP16(0xb990LL), MASK_RRF_U0RER, INSTR_RRF_U0RER, 3, 4, 1, "translate two to two" }, + { "trtt", OP16(0xb990LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0, "translate two to two" }, + { "crdte", OP16(0xb98fLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 8, 1, "compare and replace DAT table entry" }, + { "idte", OP16(0xb98eLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 3, 1, "invalidate dat table entry" }, + { "epsw", OP16(0xb98dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0, "extract psw" }, + { "rdp", OP16(0xb98bLL), MASK_RRF_RURR2, INSTR_RRF_RURR2, 2, 12, 1, "reset dat protection" }, + { "cspg", OP16(0xb98aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 3, 0, "compare and swap and purge" }, + { "slbgr", OP16(0xb989LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "subtract logical with borrow 64" }, + { "alcgr", OP16(0xb988LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "add logical with carry 64" }, + { "dlgr", OP16(0xb987LL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0, "divide logical 64" }, + { "mlgr", OP16(0xb986LL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0, "multiply logical 64" }, + { "llghr", OP16(0xb985LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load logical halfword 64" }, + { "llgcr", OP16(0xb984LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load logical character 64" }, + { "flogr", OP16(0xb983LL), MASK_RRE_RER, INSTR_RRE_RER, 2, 4, 0, "find leftmost one" }, + { "xgr", OP16(0xb982LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "exclusive or 64" }, + { "ogr", OP16(0xb981LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "or 64" }, + { "ngr", OP16(0xb980LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "and 64" }, + { "nxrk", OP16(0xb977LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "not exclusive or 32 bit" }, + { "nork", OP16(0xb976LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "nor 32 bit" }, + { "notr", OP16(0xb976LL), MASK_RRF_R0RR4, INSTR_RRF_R0RR4, 2, 11, 0, "not 32 bit" }, + { "ocrk", OP16(0xb975LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "or with complement 32 bit" }, + { "nnrk", OP16(0xb974LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "nand 32 bit" }, + { "clrtnh", OP32(0xb973c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on A not high" }, + { "clrtle", OP32(0xb973c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on low or equal" }, + { "clrtnl", OP32(0xb973a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on A not low" }, + { "clrthe", OP32(0xb973a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on high or equal" }, + { "clrte", OP32(0xb9738000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on A equal B" }, + { "clrtnlh", OP32(0xb9738000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on not low or high" }, + { "clrtne", OP32(0xb9736000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on A not equal B" }, + { "clrtlh", OP32(0xb9736000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on low or high" }, + { "clrtl", OP32(0xb9734000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on A low" }, + { "clrtnhe", OP32(0xb9734000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on not high or equal" }, + { "clrth", OP32(0xb9732000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on A high" }, + { "clrtnle", OP32(0xb9732000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (32) on not low or equal" }, + { "clrt", OP16(0xb973LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0, "compare logical and trap (32)" }, + { "crtnh", OP32(0xb972c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on A not high" }, + { "crtle", OP32(0xb972c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on low or equal" }, + { "crtnl", OP32(0xb972a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on A not low" }, + { "crthe", OP32(0xb972a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on high or equal" }, + { "crte", OP32(0xb9728000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on A equal B" }, + { "crtnlh", OP32(0xb9728000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on not low or high" }, + { "crtne", OP32(0xb9726000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on A not equal B" }, + { "crtlh", OP32(0xb9726000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on low or high" }, + { "crtl", OP32(0xb9724000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on A low" }, + { "crtnhe", OP32(0xb9724000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on not high or equal" }, + { "crth", OP32(0xb9722000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on A high" }, + { "crtnle", OP32(0xb9722000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap on not low or equal" }, + { "crt", OP16(0xb972LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0, "compare and trap" }, + { "bdepg", OP16(0xb96dLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 13, 0, "bit deposit" }, + { "bextg", OP16(0xb96cLL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 13, 0, "bit extract" }, + { "ctzg", OP16(0xb969LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 13, 0, "count trailing zeros" }, + { "clzg", OP16(0xb968LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 13, 0, "count leading zeros" }, + { "nxgrk", OP16(0xb967LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "not exclusive or 64 bit" }, + { "nogrk", OP16(0xb966LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "nor 64 bit" }, + { "notgr", OP16(0xb966LL), MASK_RRF_R0RR4, INSTR_RRF_R0RR4, 2, 11, 0, "not 64 bit" }, + { "ocgrk", OP16(0xb965LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "or with complement 64 bit" }, + { "nngrk", OP16(0xb964LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "nand 64 bit" }, + { "clgrtnh", OP32(0xb961c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on A not high" }, + { "clgrtle", OP32(0xb961c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on low or equal" }, + { "clgrtnl", OP32(0xb961a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on A not low" }, + { "clgrthe", OP32(0xb961a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on high or equal" }, + { "clgrte", OP32(0xb9618000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on A equal B" }, + { "clgrtnlh", OP32(0xb9618000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on not low or high" }, + { "clgrtne", OP32(0xb9616000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on A not equal B" }, + { "clgrtlh", OP32(0xb9616000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on low or high" }, + { "clgrtl", OP32(0xb9614000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on A low" }, + { "clgrtnhe", OP32(0xb9614000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on not high or equal" }, + { "clgrth", OP32(0xb9612000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on A high" }, + { "clgrtnle", OP32(0xb9612000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare logical and trap (64) on not low or equal" }, + { "clgrt", OP16(0xb961LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0, "compare logical and trap (64)" }, + { "cgrtnh", OP32(0xb960c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on A not high" }, + { "cgrtle", OP32(0xb960c000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on low or equal" }, + { "cgrtnl", OP32(0xb960a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on A not low" }, + { "cgrthe", OP32(0xb960a000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on high or equal" }, + { "cgrte", OP32(0xb9608000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on A equal B" }, + { "cgrtnlh", OP32(0xb9608000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on not low or high" }, + { "cgrtne", OP32(0xb9606000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on A not equal B" }, + { "cgrtlh", OP32(0xb9606000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on low or high" }, + { "cgrtl", OP32(0xb9604000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on A low" }, + { "cgrtnhe", OP32(0xb9604000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on not high or equal" }, + { "cgrth", OP32(0xb9602000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on A high" }, + { "cgrtnle", OP32(0xb9602000LL), MASK_RRF_00RR, INSTR_RRF_00RR, 2, 6, 0, "compare and trap 64 on not low or equal" }, + { "cgrt", OP16(0xb960LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 6, 0, "compare and trap 64" }, + { "cxlftr", OP16(0xb95bLL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit fixed logical to extended dfp with rounding mode" }, + { "cxlgtr", OP16(0xb95aLL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from 64 bit fixed logical to extended dfp with rounding mode" }, + { "cxftr", OP16(0xb959LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from 32 bit fixed to extended dfp with rounding mode" }, + { "cdlftr", OP16(0xb953LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit fixed logical to long dfp with rounding mode" }, + { "cdlgtr", OP16(0xb952LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 64 bit fixed logical to long dfp with rounding mode" }, + { "cdftr", OP16(0xb951LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit fixed to long dfp with rounding mode" }, + { "clfxtr", OP16(0xb94bLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 32 bit fixed logical from extended dfp with rounding mode" }, + { "clgxtr", OP16(0xb94aLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 64 bit fixed logical from extended dfp with rounding mode" }, + { "cfxtr", OP16(0xb949LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed from extended dfp source with rounding mode" }, + { "bctgr", OP16(0xb946LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "branch on count 64" }, + { "clfdtr", OP16(0xb943LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed logical from long dfp with rounding mode" }, + { "clgdtr", OP16(0xb942LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 64 bit fixed logical from long dfp with rounding mode" }, + { "cfdtr", OP16(0xb941LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed from long dfp source with rounding mode" }, + { "klmd", OP16(0xb93fLL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 13, 1, "compute last message digest" }, + { "klmd", OP16(0xb93fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0, "compute last message digest" }, + { "kimd", OP16(0xb93eLL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 13, 1, "compute intermediate message digest" }, + { "kimd", OP16(0xb93eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0, "compute intermediate message digest" }, + { "prno", OP16(0xb93cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 10, 0, "perform random number operation" }, + { "ppno", OP16(0xb93cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 9, 0, "perform pseudorandom number operation" }, + { "nnpa", OP16(0xb93bLL), MASK_RRE_00, INSTR_RRE_00, 2, 12, 0, "neural network processing assist" }, + { "kdsa", OP16(0xb93aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 11, 0, "compute digital signature authentication" }, + { "dfltcc", OP16(0xb939LL), MASK_RRF_R0RR2, INSTR_RRF_R0RR2, 2, 11, 0, "deflate conversion call" }, + { "sortl", OP16(0xb938LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 11, 0, "sort lists" }, + { "clgfr", OP16(0xb931LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "compare logical 64<32" }, + { "cgfr", OP16(0xb930LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "compare 64<32" }, + { "kmc", OP16(0xb92fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0, "cipher message with chaining" }, + { "km", OP16(0xb92eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0, "cipher message" }, + { "kmctr", OP16(0xb92dLL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 7, 0, "cipher message with counter" }, + { "pcc", OP16(0xb92cLL), MASK_RRE_00, INSTR_RRE_00, 2, 7, 0, "perform cryptographic computation" }, + { "kmo", OP16(0xb92bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "cipher message with OFB" }, + { "kmf", OP16(0xb92aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 7, 0, "cipher message with CFB" }, + { "kma", OP16(0xb929LL), MASK_RRF_R0RR, INSTR_RRF_R0RR, 2, 10, 0, "cipher message with galois counter mode" }, + { "pckmo", OP16(0xb928LL), MASK_RRE_00, INSTR_RRE_00, 2, 7, 0, "perform cryptographic key management operation" }, + { "lhr", OP16(0xb927LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load halfword 32" }, + { "lbr", OP16(0xb926LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load byte 32" }, + { "sturg", OP16(0xb925LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "store using real address 64" }, + { "clgr", OP16(0xb921LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "compare logical 64" }, + { "cgr", OP16(0xb920LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "compare 64" }, + { "lrvr", OP16(0xb91fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 2, 0, "load reversed 32" }, + { "kmac", OP16(0xb91eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 3, 0, "compute message authentication code" }, + { "dsgfr", OP16(0xb91dLL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0, "divide single 64<32" }, + { "msgfr", OP16(0xb91cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "multiply single 64<32" }, + { "slgfr", OP16(0xb91bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "subtract logical 64<32" }, + { "algfr", OP16(0xb91aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "add logical 64<32" }, + { "sgfr", OP16(0xb919LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "subtract 64<32" }, + { "agfr", OP16(0xb918LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "add 64<32" }, + { "llgtr", OP16(0xb917LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load logical thirty one bits" }, + { "llgfr", OP16(0xb916LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load logical 64<32" }, + { "lgfr", OP16(0xb914LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load 64<32" }, + { "lcgfr", OP16(0xb913LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load complement 64<32" }, + { "ltgfr", OP16(0xb912LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load and test 64<32" }, + { "lngfr", OP16(0xb911LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load negative 64<32" }, + { "lpgfr", OP16(0xb910LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load positive 64<32" }, + { "lrvgr", OP16(0xb90fLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load reversed 64" }, + { "eregg", OP16(0xb90eLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "extract stacked registers 64" }, + { "dsgr", OP16(0xb90dLL), MASK_RRE_RER, INSTR_RRE_RER, 2, 2, 0, "divide single 64" }, + { "msgr", OP16(0xb90cLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "multiply single 64" }, + { "slgr", OP16(0xb90bLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "subtract logical 64" }, + { "algr", OP16(0xb90aLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "add logical 64" }, + { "sgr", OP16(0xb909LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "subtract 64" }, + { "agr", OP16(0xb908LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "add 64" }, + { "lghr", OP16(0xb907LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load halfword 64" }, + { "lgbr", OP16(0xb906LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 4, 0, "load byte 64" }, + { "lurag", OP16(0xb905LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load using real address 64" }, + { "lgr", OP16(0xb904LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load 64" }, + { "lcgr", OP16(0xb903LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load complement 64" }, + { "ltgr", OP16(0xb902LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load and test 64" }, + { "lngr", OP16(0xb901LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load negative 64" }, + { "lpgr", OP16(0xb900LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 2, 0, "load positive 64" }, + { "lctl", OP8(0xb7LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0, 0, "load control" }, + { "stctl", OP8(0xb6LL), MASK_RS_CCRD, INSTR_RS_CCRD, 3, 0, 0, "store control" }, + { "rrxtr", OP16(0xb3ffLL), MASK_RRF_FEFERU, INSTR_RRF_FEFERU, 2, 5, 0, "Reround extended dfp" }, + { "iextr", OP16(0xb3feLL), MASK_RRF_FE0FER, INSTR_RRF_FE0FER, 2, 5, 0, "insert biased exponent extended dfp" }, + { "qaxtr", OP16(0xb3fdLL), MASK_RRF_FEUFEFE, INSTR_RRF_FEUFEFE, 2, 5, 0, "Quantize extended dfp" }, + { "cextr", OP16(0xb3fcLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 2, 5, 0, "compare exponent extended dfp" }, + { "cxstr", OP16(0xb3fbLL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0, "convert from signed bcd extended dfp" }, + { "cxutr", OP16(0xb3faLL), MASK_RRE_FER, INSTR_RRE_FER, 2, 5, 0, "convert from unsigned bcd to extended dfp" }, + { "cxgtra", OP16(0xb3f9LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from fixed extended dfp with rounding mode" }, + { "cxgtr", OP16(0xb3f9LL), MASK_RRE_FER, INSTR_RRE_FER, 2, 5, 0, "convert from fixed extended dfp" }, + { "rrdtr", OP16(0xb3f7LL), MASK_RRF_FFRU, INSTR_RRF_FFRU, 2, 5, 0, "Reround long dfp" }, + { "iedtr", OP16(0xb3f6LL), MASK_RRF_F0FR, INSTR_RRF_F0FR, 2, 5, 0, "insert biased exponent long dfp" }, + { "qadtr", OP16(0xb3f5LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 2, 5, 0, "Quantize long dfp" }, + { "cedtr", OP16(0xb3f4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "compare exponent long dfp" }, + { "cdstr", OP16(0xb3f3LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0, "convert from signed bcd long dfp" }, + { "cdutr", OP16(0xb3f2LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0, "convert from unsigned bcd to long dfp" }, + { "cdgtra", OP16(0xb3f1LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from fixed long dfp with rounding mode" }, + { "cdgtr", OP16(0xb3f1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0, "convert from fixed long dfp" }, + { "esxtr", OP16(0xb3efLL), MASK_RRE_RFE, INSTR_RRE_RFE, 2, 5, 0, "extract significance from extended dfp" }, + { "eextr", OP16(0xb3edLL), MASK_RRE_RFE, INSTR_RRE_RFE, 2, 5, 0, "extract biased exponent from extended dfp" }, + { "cxtr", OP16(0xb3ecLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 2, 5, 0, "compare extended dfp" }, + { "csxtr", OP16(0xb3ebLL), MASK_RRF_0UREFE, INSTR_RRF_0UREFE, 2, 5, 0, "convert from extended dfp to signed bcd" }, + { "cuxtr", OP16(0xb3eaLL), MASK_RRE_RFE, INSTR_RRE_RFE, 2, 5, 0, "convert from extended dfp to unsigned bcd" }, + { "cgxtra", OP16(0xb3e9LL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 64 bit fixed from extended dfp with rounding mode" }, + { "cgxtr", OP16(0xb3e9LL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 2, 5, 0, "convert from extended dfp to fixed" }, + { "kxtr", OP16(0xb3e8LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "compare and signal extended dfp" }, + { "esdtr", OP16(0xb3e7LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0, "extract significance from long dfp" }, + { "eedtr", OP16(0xb3e5LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0, "extract biased exponent from long dfp" }, + { "cdtr", OP16(0xb3e4LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "compare long dfp" }, + { "csdtr", OP16(0xb3e3LL), MASK_RRF_0URF, INSTR_RRF_0URF, 2, 5, 0, "convert from long dfp to signed bcd" }, + { "cudtr", OP16(0xb3e2LL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0, "convert from long dfp to unsigned bcd" }, + { "cgdtra", OP16(0xb3e1LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 64 bit fixed from long dfp with rounding mode" }, + { "cgdtr", OP16(0xb3e1LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 5, 0, "convert from long dfp to fixed" }, + { "kdtr", OP16(0xb3e0LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "compare and signal long dfp" }, + { "fixtr", OP16(0xb3dfLL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 5, 0, "load fp integer extended dfp" }, + { "ltxtr", OP16(0xb3deLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 2, 5, 0, "load and test extended dfp" }, + { "ldxtr", OP16(0xb3ddLL), MASK_RRF_UUFFE, INSTR_RRF_UUFFE, 2, 5, 0, "load rounded extended dfp" }, + { "lxdtr", OP16(0xb3dcLL), MASK_RRF_0UFEF, INSTR_RRF_0UFEF, 2, 5, 0, "load lengthened extended dfp" }, + { "sxtra", OP16(0xb3dbLL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0, "subtract extended dfp with rounding mode" }, + { "sxtr", OP16(0xb3dbLL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0, "subtract extended dfp" }, + { "axtra", OP16(0xb3daLL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0, "add extended dfp with rounding mode" }, + { "axtr", OP16(0xb3daLL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0, "add extended dfp" }, + { "dxtra", OP16(0xb3d9LL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0, "divide extended dfp with rounding mode" }, + { "dxtr", OP16(0xb3d9LL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0, "divide extended dfp" }, + { "mxtra", OP16(0xb3d8LL), MASK_RRF_FEUFEFE2, INSTR_RRF_FEUFEFE2, 2, 7, 0, "multiply extended dfp with rounding mode" }, + { "mxtr", OP16(0xb3d8LL), MASK_RRR_FE0FEFE, INSTR_RRR_FE0FEFE, 2, 5, 0, "multiply extended dfp" }, + { "fidtr", OP16(0xb3d7LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5, 0, "load fp integer long dfp" }, + { "ltdtr", OP16(0xb3d6LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "load and test long dfp" }, + { "ledtr", OP16(0xb3d5LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 5, 0, "load rounded long dfp" }, + { "ldetr", OP16(0xb3d4LL), MASK_RRF_0UFF, INSTR_RRF_0UFF, 2, 5, 0, "load lengthened long dfp" }, + { "sdtra", OP16(0xb3d3LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0, "subtract long dfp with rounding mode" }, + { "sdtr", OP16(0xb3d3LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0, "subtract long dfp" }, + { "adtra", OP16(0xb3d2LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0, "add long dfp with rounding mode" }, + { "adtr", OP16(0xb3d2LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0, "add long dfp" }, + { "ddtra", OP16(0xb3d1LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0, "divide long dfp with rounding mode" }, + { "ddtr", OP16(0xb3d1LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0, "divide long dfp" }, + { "mdtra", OP16(0xb3d0LL), MASK_RRF_FUFF2, INSTR_RRF_FUFF2, 2, 7, 0, "multiply long dfp with rounding mode" }, + { "mdtr", OP16(0xb3d0LL), MASK_RRR_F0FF, INSTR_RRR_F0FF, 2, 5, 0, "multiply long dfp" }, + { "lgdr", OP16(0xb3cdLL), MASK_RRE_RF, INSTR_RRE_RF, 2, 5, 0, "load GR from FPR" }, + { "cgxr", OP16(0xb3caLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 2, 2, 0, "convert to fixed extended hfp to 64" }, + { "cgdr", OP16(0xb3c9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0, "convert to fixed long hfp to 64" }, + { "cger", OP16(0xb3c8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0, "convert to fixed short hfp to 64" }, + { "cxgr", OP16(0xb3c6LL), MASK_RRE_FER, INSTR_RRE_FER, 2, 2, 0, "convert from fixed 64 to extended hfp" }, + { "cdgr", OP16(0xb3c5LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0, "convert from fixed 64 to long hfp" }, + { "cegr", OP16(0xb3c4LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0, "convert from fixed 64 to short hfp" }, + { "ldgr", OP16(0xb3c1LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 5, 0, "load FPR from GR" }, + { "cfxr", OP16(0xb3baLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 3, 0, 0, "convert to fixed extended hfp to 32" }, + { "cfdr", OP16(0xb3b9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0, "convert to fixed long hfp to 32" }, + { "cfer", OP16(0xb3b8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0, "convert to fixed short hfp to 32" }, + { "cxfr", OP16(0xb3b6LL), MASK_RRE_FER, INSTR_RRE_FER, 3, 0, 0, "convert from fixed 32 to extended hfp" }, + { "cdfr", OP16(0xb3b5LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0, "convert from fixed 32 to long hfp" }, + { "cefr", OP16(0xb3b4LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0, "convert from fixed 32 to short hfp" }, + { "clgxbr", OP16(0xb3aeLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 64 bit fixed logical from extended bfp with rounding mode" }, + { "clgdbr", OP16(0xb3adLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 64 bit fixed logical from long bfp with rounding mode" }, + { "clgebr", OP16(0xb3acLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 64 bit fixed logical from short bfp with rounding mode" }, + { "cgxbra", OP16(0xb3aaLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 64 bit fixed from extended bfp with rounding mode" }, + { "cgxbr", OP16(0xb3aaLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 2, 2, 0, "convert to fixed extended bfp to 64" }, + { "cgdbra", OP16(0xb3a9LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 64 bit fixed from long bfp with rounding mode" }, + { "cgdbr", OP16(0xb3a9LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0, "convert to fixed long bfp to 64" }, + { "cgebra", OP16(0xb3a8LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 64 bit fixed from short bfp with rounding mode" }, + { "cgebr", OP16(0xb3a8LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 2, 2, 0, "convert to fixed short bfd to 64" }, + { "cxgbra", OP16(0xb3a6LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from 64 bit fixed to extended bfp with rounding mode" }, + { "cxgbr", OP16(0xb3a6LL), MASK_RRE_FER, INSTR_RRE_FER, 2, 2, 0, "convert from fixed 64 to extended bfp" }, + { "cdgbra", OP16(0xb3a5LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 64 bit fixed to long bfp with rounding mode" }, + { "cdgbr", OP16(0xb3a5LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0, "convert from fixed 64 to long bfp" }, + { "cegbra", OP16(0xb3a4LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 64 bit fixed to short bfp with rounding mode" }, + { "cegbr", OP16(0xb3a4LL), MASK_RRE_FR, INSTR_RRE_FR, 2, 2, 0, "convert from fixed 64 to short bfp" }, + { "cxlgbr", OP16(0xb3a2LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from 64 bit logical fixed to extended bfp with rounding mode" }, + { "cdlgbr", OP16(0xb3a1LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 64 bit logical fixed to long bfp with rounding mode" }, + { "celgbr", OP16(0xb3a0LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 64 bit logical fixed to short bfp with rounding mode" }, + { "clfxbr", OP16(0xb39eLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 32 bit fixed logical from extended bfp with rounding mode" }, + { "clfdbr", OP16(0xb39dLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed logical from long bfp with rounding mode" }, + { "clfebr", OP16(0xb39cLL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed logical from short bfp with rounding mode" }, + { "cfxbra", OP16(0xb39aLL), MASK_RRF_UURFE, INSTR_RRF_UURFE, 2, 7, 0, "convert to 32 bit fixed from extended bfp with rounding mode" }, + { "cfxbr", OP16(0xb39aLL), MASK_RRF_U0RFE, INSTR_RRF_U0RFE, 3, 0, 0, "convert to fixed extended bfp to 32" }, + { "cfdbra", OP16(0xb399LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed from long bfp with rounding mode" }, + { "cfdbr", OP16(0xb399LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0, "convert to fixed long bfp to 32" }, + { "cfebra", OP16(0xb398LL), MASK_RRF_UURF, INSTR_RRF_UURF, 2, 7, 0, "convert to 32 bit fixed from short bfp with rounding mode" }, + { "cfebr", OP16(0xb398LL), MASK_RRF_U0RF, INSTR_RRF_U0RF, 3, 0, 0, "convert to fixed short bfp to 32" }, + { "cxfbra", OP16(0xb396LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from 32 bit fixed to extended bfp with rounding mode" }, + { "cxfbr", OP16(0xb396LL), MASK_RRE_FER, INSTR_RRE_FER, 3, 0, 0, "convert from fixed 32 to extended bfp" }, + { "cdfbra", OP16(0xb395LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit fixed to long bfp with rounding mode" }, + { "cdfbr", OP16(0xb395LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0, "convert from fixed 32 to long bfp" }, + { "cefbra", OP16(0xb394LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit fixed to short bfp with rounding mode" }, + { "cefbr", OP16(0xb394LL), MASK_RRE_FR, INSTR_RRE_FR, 3, 0, 0, "convert from fixed 32 to short bfp" }, + { "cxlfbr", OP16(0xb392LL), MASK_RRF_UUFER, INSTR_RRF_UUFER, 2, 7, 0, "convert from 32 bit logical fixed to extended bfp with rounding mode" }, + { "cdlfbr", OP16(0xb391LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit logical fixed to long bfp with rounding mode" }, + { "celfbr", OP16(0xb390LL), MASK_RRF_UUFR, INSTR_RRF_UUFR, 2, 7, 0, "convert from 32 bit logical fixed to short bfp with rounding mode" }, + { "efpc", OP16(0xb38cLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 1, "extract fpc" }, + { "sfasr", OP16(0xb385LL), MASK_RRE_R0, INSTR_RRE_R0, 2, 5, 0, "set fpc and signal" }, + { "sfpc", OP16(0xb384LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 1, "set fpc" }, + { "fidr", OP16(0xb37fLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load fp integer long hfp" }, + { "fier", OP16(0xb377LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load fp integer short hfp" }, + { "lzxr", OP16(0xb376LL), MASK_RRE_FE0, INSTR_RRE_FE0, 3, 0, 0, "load extended zero" }, + { "lzdr", OP16(0xb375LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0, 0, "load long zero" }, + { "lzer", OP16(0xb374LL), MASK_RRE_F0, INSTR_RRE_F0, 3, 0, 0, "load short zero" }, + { "lcdfr", OP16(0xb373LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "load complement no cc" }, + { "cpsdr", OP16(0xb372LL), MASK_RRF_F0FF2, INSTR_RRF_F0FF2, 2, 5, 0, "copy sign" }, + { "lndfr", OP16(0xb371LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "load negative no cc" }, + { "lpdfr", OP16(0xb370LL), MASK_RRE_FF, INSTR_RRE_FF, 2, 5, 0, "load positive no cc" }, + { "cxr", OP16(0xb369LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "compare extended hfp" }, + { "fixr", OP16(0xb367LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load fp integer extended hfp" }, + { "lexr", OP16(0xb366LL), MASK_RRE_FFE, INSTR_RRE_FFE, 3, 0, 0, "load rounded extended to short hfp" }, + { "lxr", OP16(0xb365LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load extended fp" }, + { "lcxr", OP16(0xb363LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load complement extended hfp" }, + { "ltxr", OP16(0xb362LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load and test extended hfp" }, + { "lnxr", OP16(0xb361LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load negative extended hfp" }, + { "lpxr", OP16(0xb360LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load positive extended hfp" }, + { "fidbra", OP16(0xb35fLL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 7, 0, "load fp integer long bfp with inexact suppression" }, + { "fidbr", OP16(0xb35fLL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0, "load fp integer long bfp" }, + { "didbr", OP16(0xb35bLL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0, 0, "divide to integer long bfp" }, + { "thdr", OP16(0xb359LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "convert long bfp to long hfp" }, + { "thder", OP16(0xb358LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "convert short bfp to long hfp" }, + { "fiebra", OP16(0xb357LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 7, 0, "load fp integer short bfp with inexact suppression" }, + { "fiebr", OP16(0xb357LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0, "load fp integer short bfp" }, + { "diebr", OP16(0xb353LL), MASK_RRF_FUFF, INSTR_RRF_FUFF, 3, 0, 0, "divide to integer short bfp" }, + { "tbdr", OP16(0xb351LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0, "convert long hfp to long bfp" }, + { "tbedr", OP16(0xb350LL), MASK_RRF_U0FF, INSTR_RRF_U0FF, 3, 0, 0, "convert long hfp to short bfp" }, + { "dxbr", OP16(0xb34dLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "divide extended bfp" }, + { "mxbr", OP16(0xb34cLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "multiply extended bfp" }, + { "sxbr", OP16(0xb34bLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "subtract extended bfp" }, + { "axbr", OP16(0xb34aLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "add extended bfp" }, + { "cxbr", OP16(0xb349LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "compare extended bfp" }, + { "kxbr", OP16(0xb348LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "compare and signal extended bfp" }, + { "fixbra", OP16(0xb347LL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 7, 0, "load fp integer extended bfp with inexact suppression" }, + { "fixbr", OP16(0xb347LL), MASK_RRF_U0FEFE, INSTR_RRF_U0FEFE, 3, 0, 0, "load fp integer extended bfp" }, + { "lexbra", OP16(0xb346LL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 7, 0, "load rounded short/extended bfp to short/extended bfp with rounding mode" }, + { "lexbr", OP16(0xb346LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load rounded extended to short bfp" }, + { "ldxbra", OP16(0xb345LL), MASK_RRF_UUFEFE, INSTR_RRF_UUFEFE, 2, 7, 0, "load rounded long/extended bfp to long/extended bfp with rounding mode" }, + { "ldxbr", OP16(0xb345LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load rounded extended to long bfp" }, + { "ledbra", OP16(0xb344LL), MASK_RRF_UUFF, INSTR_RRF_UUFF, 2, 7, 0, "load rounded short/long bfp to short/long bfp with rounding mode" }, + { "ledbr", OP16(0xb344LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load rounded long to short bfp" }, + { "lcxbr", OP16(0xb343LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load complement extended bfp" }, + { "ltxbr", OP16(0xb342LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load and test extended bfp" }, + { "lnxbr", OP16(0xb341LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load negative extended bfp" }, + { "lpxbr", OP16(0xb340LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "load positive extended bfp" }, + { "msdr", OP16(0xb33fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0, "multiply and subtract long hfp" }, + { "madr", OP16(0xb33eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0, "multiply and add long hfp" }, + { "myhr", OP16(0xb33dLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0, "multiply unnormalized long hfp high" }, + { "mayhr", OP16(0xb33cLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0, "multiply and add unnormalized long hfp high" }, + { "myr", OP16(0xb33bLL), MASK_RRF_FE0FF, INSTR_RRF_FE0FF, 2, 4, 0, "multiply unnormalized long hfp" }, + { "mayr", OP16(0xb33aLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0, "multiply and add unnormalized long hfp" }, + { "mylr", OP16(0xb339LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0, "multiply unnormalized long hfp low" }, + { "maylr", OP16(0xb338LL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 2, 4, 0, "multiply and add unnormalized long hfp low" }, + { "meer", OP16(0xb337LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "multiply short hfp" }, + { "sqxr", OP16(0xb336LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "square root extended hfp" }, + { "mser", OP16(0xb32fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0, "mutliply and subtract short hfp" }, + { "maer", OP16(0xb32eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 3, 0, "multiply and add short hfp" }, + { "lxer", OP16(0xb326LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0, "load lengthened short to extended hfp" }, + { "lxdr", OP16(0xb325LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0, "load lengthened long to extended hfp" }, + { "lder", OP16(0xb324LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load lengthened short to long hfp" }, + { "msdbr", OP16(0xb31fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0, "multiply and subtract long bfp" }, + { "madbr", OP16(0xb31eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0, "multiply and add long bfp" }, + { "ddbr", OP16(0xb31dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "divide long bfp" }, + { "mdbr", OP16(0xb31cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "multiply long bfp" }, + { "sdbr", OP16(0xb31bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "subtract long bfp" }, + { "adbr", OP16(0xb31aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "add long bfp" }, + { "cdbr", OP16(0xb319LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "compare long bfp" }, + { "kdbr", OP16(0xb318LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "compare and signal long bfp" }, + { "meebr", OP16(0xb317LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "multiply short bfp" }, + { "sqxbr", OP16(0xb316LL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "square root extended bfp" }, + { "sqdbr", OP16(0xb315LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "square root long bfp" }, + { "sqebr", OP16(0xb314LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "square root short bfp" }, + { "lcdbr", OP16(0xb313LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load complement long bfp" }, + { "ltdbr", OP16(0xb312LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load and test long bfp" }, + { "lndbr", OP16(0xb311LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load negative long bfp" }, + { "lpdbr", OP16(0xb310LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load positive long bfp" }, + { "msebr", OP16(0xb30fLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0, "multiply and subtract short bfp" }, + { "maebr", OP16(0xb30eLL), MASK_RRF_F0FF, INSTR_RRF_F0FF, 3, 0, 0, "multiply and add short bfp" }, + { "debr", OP16(0xb30dLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "divide short bfp" }, + { "mdebr", OP16(0xb30cLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "multiply short to long bfp" }, + { "sebr", OP16(0xb30bLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "subtract short bfp" }, + { "aebr", OP16(0xb30aLL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "add short bfp" }, + { "cebr", OP16(0xb309LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "compare short bfp" }, + { "kebr", OP16(0xb308LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "compare and signal short bfp" }, + { "mxdbr", OP16(0xb307LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0, "multiply long to extended bfp" }, + { "lxebr", OP16(0xb306LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0, "load lengthened short to extended bfp" }, + { "lxdbr", OP16(0xb305LL), MASK_RRE_FEF, INSTR_RRE_FEF, 3, 0, 0, "load lengthened long to extended bfp" }, + { "ldebr", OP16(0xb304LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load lengthened short to long bfp" }, + { "lcebr", OP16(0xb303LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load complement short bfp" }, + { "ltebr", OP16(0xb302LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load and test short bfp" }, + { "lnebr", OP16(0xb301LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load negative short bfp" }, + { "lpebr", OP16(0xb300LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "load positive short bfp" }, + { "trap4", OP16(0xb2ffLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "trap4" }, + { "tabort", OP16(0xb2fcLL), MASK_S_RD, INSTR_S_RD, 2, 8, 4, "transaction abort" }, + { "niai", OP16(0xb2faLL), MASK_IE_UU, INSTR_IE_UU, 2, 8, 0, "next instruction access intent" }, + { "tend", OP16(0xb2f8LL), MASK_S_00, INSTR_S_00, 2, 8, 4, "transaction end" }, + { "ecpga", OP16(0xb2edLL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0, "extract coprocessor-group address" }, + { "etnd", OP16(0xb2ecLL), MASK_RRE_R0, INSTR_RRE_R0, 2, 8, 4, "extract transaction nesting depth" }, + { "ppa", OP16(0xb2e8LL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 8, 4, "perform processor assist" }, + { "epctr", OP16(0xb2e5LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0, "extract peripheral counter" }, + { "ecctr", OP16(0xb2e4LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0, "extract cpu counter" }, + { "spctr", OP16(0xb2e1LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0, "set peripheral counter" }, + { "scctr", OP16(0xb2e0LL), MASK_RRE_RR, INSTR_RRE_RR, 2, 6, 0, "set cpu counter" }, + { "lfas", OP16(0xb2bdLL), MASK_S_RD, INSTR_S_RD, 2, 5, 0, "load fpd and signal" }, + { "srnmt", OP16(0xb2b9LL), MASK_S_RD, INSTR_S_RD, 2, 5, 0, "set rounding mode dfp" }, + { "srnmb", OP16(0xb2b8LL), MASK_S_RD, INSTR_S_RD, 2, 7, 0, "set 3 bit bfp rounding mode" }, + { "lpswe", OP16(0xb2b2LL), MASK_S_RD, INSTR_S_RD, 2, 2, 0, "load psw extended" }, + { "stfl", OP16(0xb2b1LL), MASK_S_RD, INSTR_S_RD, 3, 2, 0, "store facility list" }, + { "stfle", OP16(0xb2b0LL), MASK_S_RD, INSTR_S_RD, 2, 4, 0, "store facility list extended" }, + { "cu12", OP16(0xb2a7LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1, "convert utf-8 to utf-16" }, + { "cutfu", OP16(0xb2a7LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1, "convert utf-8 to unicode" }, + { "cutfu", OP16(0xb2a7LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "convert utf-8 to unicode" }, + { "cu21", OP16(0xb2a6LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1, "convert utf-16 to utf-8" }, + { "cuutf", OP16(0xb2a6LL), MASK_RRF_U0RERE, INSTR_RRF_U0RERE, 2, 4, 1, "convert unicode to utf-8" }, + { "cuutf", OP16(0xb2a6LL), MASK_RRE_RERE, INSTR_RRE_RERE, 3, 0, 0, "convert unicode to utf-8" }, + { "tre", OP16(0xb2a5LL), MASK_RRE_RER, INSTR_RRE_RER, 3, 0, 0, "translate extended" }, + { "lfpc", OP16(0xb29dLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "load fpc" }, + { "stfpc", OP16(0xb29cLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store fpc" }, + { "srnm", OP16(0xb299LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set rounding mode" }, + { "qpaci", OP16(0xb28fLL), MASK_S_RD, INSTR_S_RD, 2, 12, 0, "query processor activity counter information" }, + { "qctri", OP16(0xb28eLL), MASK_S_RD, INSTR_S_RD, 2, 6, 0, "query counter information" }, + { "lsctl", OP16(0xb287LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0, "load sampling controls" }, + { "qsi", OP16(0xb286LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0, "query sampling information" }, + { "lpctl", OP16(0xb285LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0, "load peripheral-counter-set controls" }, + { "lcctl", OP16(0xb284LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0, "load cpu-counter-set controls" }, + { "lpp", OP16(0xb280LL), MASK_S_RD, INSTR_S_RD, 2, 6, 0, "load program parameter" }, + { "stsi", OP16(0xb27dLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store system information" }, + { "stckf", OP16(0xb27cLL), MASK_S_RD, INSTR_S_RD, 2, 4, 0, "store clock fast" }, + { "sacf", OP16(0xb279LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set address space control fast" }, + { "stcke", OP16(0xb278LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store clock extended" }, + { "rp", OP16(0xb277LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "resume program" }, + { "xsch", OP16(0xb276LL), MASK_S_00, INSTR_S_00, 3, 0, 0, "cancel subchannel" }, + { "siga", OP16(0xb274LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "signal adapter" }, + { "cmpsc", OP16(0xb263LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "compression call" }, + { "srst", OP16(0xb25eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "search string" }, + { "clst", OP16(0xb25dLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "compare logical string" }, + { "bsa", OP16(0xb25aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "branch and set authority" }, + { "bsg", OP16(0xb258LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "branch in subspace group" }, + { "cuse", OP16(0xb257LL), MASK_RRE_RERE, INSTR_RRE_RERE, 3, 0, 0, "compare until substring equal" }, + { "mvst", OP16(0xb255LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "move string" }, + { "mvpg", OP16(0xb254LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "move page" }, + { "msr", OP16(0xb252LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "multiply single" }, + { "csp", OP16(0xb250LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "compare and swap and purge" }, + { "ear", OP16(0xb24fLL), MASK_RRE_RA, INSTR_RRE_RA, 3, 0, 0, "extract access" }, + { "sar", OP16(0xb24eLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0, 0, "set access" }, + { "cpya", OP16(0xb24dLL), MASK_RRE_AA, INSTR_RRE_AA, 3, 0, 0, "copy access" }, + { "tar", OP16(0xb24cLL), MASK_RRE_AR, INSTR_RRE_AR, 3, 0, 0, "test access" }, + { "lura", OP16(0xb24bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "load using real address" }, + { "esta", OP16(0xb24aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "extract stacked state" }, + { "ereg", OP16(0xb249LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "extract stacked registers" }, + { "palb", OP16(0xb248LL), MASK_RRE_00, INSTR_RRE_00, 3, 0, 0, "purge ALB" }, + { "msta", OP16(0xb247LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0, "modify stacked state" }, + { "stura", OP16(0xb246LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "store using real address" }, + { "sqer", OP16(0xb245LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "square root (short)" }, + { "sqdr", OP16(0xb244LL), MASK_RRE_FF, INSTR_RRE_FF, 3, 0, 0, "square root (long)" }, + { "cksm", OP16(0xb241LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "checksum" }, + { "bakr", OP16(0xb240LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "branch and stack" }, + { "schm", OP16(0xb23cLL), MASK_S_00, INSTR_S_00, 3, 0, 0, "set channel monitor" }, + { "rchp", OP16(0xb23bLL), MASK_S_00, INSTR_S_00, 3, 0, 0, "reset channel path" }, + { "stcps", OP16(0xb23aLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store channel path status" }, + { "stcrw", OP16(0xb239LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store channel report word" }, + { "rsch", OP16(0xb238LL), MASK_S_00, INSTR_S_00, 3, 0, 0, "resume subchannel" }, + { "sal", OP16(0xb237LL), MASK_S_00, INSTR_S_00, 3, 0, 0, "set address limit" }, + { "tpi", OP16(0xb236LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "test pending interruption" }, + { "tsch", OP16(0xb235LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "test subchannel" }, + { "stsch", OP16(0xb234LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store subchannel" }, + { "ssch", OP16(0xb233LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "start subchannel" }, + { "msch", OP16(0xb232LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "modify subchannel" }, + { "hsch", OP16(0xb231LL), MASK_S_00, INSTR_S_00, 3, 0, 0, "halt subchannel" }, + { "csch", OP16(0xb230LL), MASK_S_00, INSTR_S_00, 3, 0, 0, "clear subchannel" }, + { "pgout", OP16(0xb22fLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "page out" }, + { "pgin", OP16(0xb22eLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "page in" }, + { "dxr", OP16(0xb22dLL), MASK_RRE_FEFE, INSTR_RRE_FEFE, 3, 0, 0, "divide (ext.)" }, + { "tb", OP16(0xb22cLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "test block" }, + { "sske", OP16(0xb22bLL), MASK_RRF_U0RR, INSTR_RRF_U0RR, 2, 4, 1, "set storage key extended" }, + { "sske", OP16(0xb22bLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "set storage key extended" }, + { "rrbe", OP16(0xb22aLL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "reset reference bit extended" }, + { "iske", OP16(0xb229LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "insert storage key extended" }, + { "pt", OP16(0xb228LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "program transfer" }, + { "esar", OP16(0xb227LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0, "extract secondary ASN" }, + { "epar", OP16(0xb226LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0, "extract primary ASN" }, + { "ssar", OP16(0xb225LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0, "set secondary ASN" }, + { "iac", OP16(0xb224LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0, "insert address space control" }, + { "ivsk", OP16(0xb223LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0, 0, "insert virtual storage key" }, + { "ipm", OP16(0xb222LL), MASK_RRE_R0, INSTR_RRE_R0, 3, 0, 0, "insert program mask" }, + { "ipte", OP16(0xb221LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0, 2, "invalidate page table entry" }, + { "cfc", OP16(0xb21aLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "compare and form codeword" }, + { "sac", OP16(0xb219LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set address space control" }, + { "pc", OP16(0xb218LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "program call" }, + { "sie", OP16(0xb214LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "start interpretive execution" }, + { "stap", OP16(0xb212LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store CPU address" }, + { "stpx", OP16(0xb211LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store prefix" }, + { "spx", OP16(0xb210LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set prefix" }, + { "ptlb", OP16(0xb20dLL), MASK_S_00, INSTR_S_00, 3, 0, 0, "purge TLB" }, + { "ipk", OP16(0xb20bLL), MASK_S_00, INSTR_S_00, 3, 0, 0, "insert PSW key" }, + { "spka", OP16(0xb20aLL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set PSW key from address" }, + { "stpt", OP16(0xb209LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store CPU timer" }, + { "spt", OP16(0xb208LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set CPU timer" }, + { "stckc", OP16(0xb207LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store clock comparator" }, + { "sckc", OP16(0xb206LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set clock comparator" }, + { "stck", OP16(0xb205LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store clock" }, + { "sck", OP16(0xb204LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "set clock" }, + { "stidp", OP16(0xb202LL), MASK_S_RD, INSTR_S_RD, 3, 0, 0, "store CPU id" }, + { "stbear", OP16(0xb201LL), MASK_S_RD, INSTR_S_RD, 2, 12, 0, "store bear" }, + { "lbear", OP16(0xb200LL), MASK_S_RD, INSTR_S_RD, 2, 12, 0, "load bear" }, + { "lra", OP8(0xb1LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "load real address" }, + { "mc", OP16(0xaf00LL), MASK_SI_URD, INSTR_SI_URD, 2, 6, 0, "monitor call" }, + { "mc", OP8(0xafLL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "monitor call" }, + { "sigp", OP8(0xaeLL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "signal processor" }, + { "stosm", OP8(0xadLL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "store then or system mask" }, + { "stnsm", OP8(0xacLL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "store then and system mask" }, + { "clcle", OP8(0xa9LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "compare logical long extended" }, + { "mvcle", OP8(0xa8LL), MASK_RS_RERERD, INSTR_RS_RERERD, 3, 0, 0, "move long extended" }, + { "j", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 48, "unconditional jump" }, + { "bru", OP16(0xa7f4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 48, "unconditional jump" }, + { "jno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not overflow / if not ones" }, + { "brno", OP16(0xa7e4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not overflow / if not ones" }, + { "jnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A not high" }, + { "jnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not plus" }, + { "brnh", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A not high" }, + { "brnp", OP16(0xa7d4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not plus" }, + { "jle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on low or equal" }, + { "brle", OP16(0xa7c4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on low or equal" }, + { "jnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A not low" }, + { "jnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not minus / if not mixed" }, + { "brnl", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A not low" }, + { "brnm", OP16(0xa7b4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not minus / if not mixed" }, + { "jhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on high or equal" }, + { "brhe", OP16(0xa7a4LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on high or equal" }, + { "jnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not low or high" }, + { "brnlh", OP16(0xa794LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not low or high" }, + { "je", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A equal B" }, + { "jz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on zero / if zeros" }, + { "bre", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A equal B" }, + { "brz", OP16(0xa784LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on zero / if zeros" }, + { "jne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A not equal B" }, + { "jnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not zero / if not zeros" }, + { "brne", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A not equal B" }, + { "brnz", OP16(0xa774LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not zero / if not zeros" }, + { "jlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on low or high" }, + { "brlh", OP16(0xa764LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on low or high" }, + { "jnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not high or equal" }, + { "brnhe", OP16(0xa754LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not high or equal" }, + { "jl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A low" }, + { "jm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on minus / if mixed" }, + { "brl", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A low" }, + { "brm", OP16(0xa744LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on minus / if mixed" }, + { "jnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not low or equal" }, + { "brnle", OP16(0xa734LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on not low or equal" }, + { "jh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A high" }, + { "jp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on plus" }, + { "brh", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on A high" }, + { "brp", OP16(0xa724LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on plus" }, + { "jo", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on overflow / if ones" }, + { "bro", OP16(0xa714LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 112, "conditional jump on overflow / if ones" }, + { "cghi", OP16(0xa70fLL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0, "compare halfword immediate 64" }, + { "chi", OP16(0xa70eLL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, "compare halfword immediate" }, + { "mghi", OP16(0xa70dLL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0, "multiply halfword immediate 64" }, + { "mhi", OP16(0xa70cLL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, "multiply halfword immediate" }, + { "aghi", OP16(0xa70bLL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0, "add halfword immediate 64" }, + { "ahi", OP16(0xa70aLL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, "add halfword immediate" }, + { "lghi", OP16(0xa709LL), MASK_RI_RI, INSTR_RI_RI, 2, 2, 0, "load halfword immediate 64" }, + { "lhi", OP16(0xa708LL), MASK_RI_RI, INSTR_RI_RI, 3, 0, 0, "load halfword immediate" }, + { "brctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2, 112, "branch relative on count 64" }, + { "jctg", OP16(0xa707LL), MASK_RI_RP, INSTR_RI_RP, 2, 2, 112, "branch relative on count 64" }, + { "brct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 112, "branch relative on count" }, + { "jct", OP16(0xa706LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 112, "branch relative on count" }, + { "bras", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 176, "branch relative and save" }, + { "jas", OP16(0xa705LL), MASK_RI_RP, INSTR_RI_RP, 3, 0, 176, "branch relative and save" }, + { "brc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0, 112, "branch relative on condition" }, + { "jc", OP16(0xa704LL), MASK_RI_UP, INSTR_RI_UP, 3, 0, 112, "conditional jump" }, + { "jnop", OP16(0xa704LL), MASK_RI_0P, INSTR_RI_0P, 3, 0, 0, "nop jump" }, + { "tmhl", OP16(0xa703LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "test under mask high low" }, + { "tmhh", OP16(0xa702LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "test under mask high high" }, + { "tmll", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0, "test under mask low low" }, + { "tml", OP16(0xa701LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0, "test under mask low" }, + { "tmlh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0, "test under mask low high" }, + { "tmh", OP16(0xa700LL), MASK_RI_RU, INSTR_RI_RU, 3, 0, 0, "test under mask high" }, + { "llill", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "load logical immediate low low" }, + { "llghi", OP16(0xa50fLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "load logical immediate" }, + { "llilh", OP16(0xa50eLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "load logical immediate low high" }, + { "llihl", OP16(0xa50dLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "load logical immediate high low" }, + { "llihh", OP16(0xa50cLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "load logical immediate high high" }, + { "oill", OP16(0xa50bLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "or immediate low low" }, + { "oilh", OP16(0xa50aLL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "or immediate low high" }, + { "oihl", OP16(0xa509LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "or immediate high low" }, + { "oihh", OP16(0xa508LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "or immediate high high" }, + { "nill", OP16(0xa507LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "and immediate low low" }, + { "nilh", OP16(0xa506LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "and immediate low high" }, + { "nihl", OP16(0xa505LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "and immediate high low" }, + { "nihh", OP16(0xa504LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "and immediate high high" }, + { "iill", OP16(0xa503LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "insert immediate low low" }, + { "iilh", OP16(0xa502LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "insert immediate low high" }, + { "iihl", OP16(0xa501LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "insert immediate high low" }, + { "iihh", OP16(0xa500LL), MASK_RI_RU, INSTR_RI_RU, 2, 2, 0, "insert immediate high high" }, + { "stam", OP8(0x9bLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0, 0, "store access multiple" }, + { "lam", OP8(0x9aLL), MASK_RS_AARD, INSTR_RS_AARD, 3, 0, 0, "load access multiple" }, + { "trace", OP8(0x99LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "trace" }, + { "lm", OP8(0x98LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "load multiple" }, + { "xi", OP8(0x97LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "exclusive or" }, + { "oi", OP8(0x96LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "or" }, + { "cli", OP8(0x95LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "compare logical" }, + { "ni", OP8(0x94LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "and" }, + { "ts", OP8(0x93LL), MASK_SI_RD, INSTR_SI_RD, 3, 0, 0, "test and set" }, + { "mvi", OP8(0x92LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "move" }, + { "tm", OP8(0x91LL), MASK_SI_URD, INSTR_SI_URD, 3, 0, 0, "test under mask" }, + { "stm", OP8(0x90LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "store multiple" }, + { "slda", OP8(0x8fLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0, "shift left double (long)" }, + { "srda", OP8(0x8eLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0, "shift right double (long)" }, + { "sldl", OP8(0x8dLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0, "shift left double logical (long)" }, + { "srdl", OP8(0x8cLL), MASK_RS_RE0RD, INSTR_RS_RE0RD, 3, 0, 0, "shift right double logical (long)" }, + { "sla", OP8(0x8bLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0, "shift left single" }, + { "sra", OP8(0x8aLL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0, "shift right single" }, + { "sll", OP8(0x89LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0, "shift left single logical" }, + { "srl", OP8(0x88LL), MASK_RS_R0RD, INSTR_RS_R0RD, 3, 0, 0, "shift right single logical" }, + { "bxle", OP8(0x87LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "branch on index low or equal" }, + { "bxh", OP8(0x86LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "branch on index high" }, + { "brxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 112, "branch relative on index low or equal" }, + { "jxle", OP8(0x85LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 112, "branch relative on index low or equal" }, + { "brxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 112, "branch relative on index high" }, + { "jxh", OP8(0x84LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0, 112, "branch relative on index high" }, + { "diag", OP8(0x83LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0, 0, "diagnose" }, + { "lpsw", OP8(0x82LL), MASK_SI_RD, INSTR_SI_RD, 3, 0, 0, "load PSW" }, + { "ssm", OP8(0x80LL), MASK_SI_RD, INSTR_SI_RD, 3, 0, 0, "set system mask" }, + { "su", OP8(0x7fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "subtract unnormalized (short)" }, + { "au", OP8(0x7eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "add unnormalized (short)" }, + { "de", OP8(0x7dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "divide (short)" }, + { "mde", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "multiply (short to long)" }, + { "me", OP8(0x7cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "multiply (short to long)" }, + { "se", OP8(0x7bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "subtract normalized (short)" }, + { "ae", OP8(0x7aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "add normalized (short)" }, + { "ce", OP8(0x79LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "compare (short)" }, + { "le", OP8(0x78LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "load (short)" }, + { "ms", OP8(0x71LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "multiply single" }, + { "ste", OP8(0x70LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "store (short)" }, + { "sw", OP8(0x6fLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "subtract unnormalized (long)" }, + { "aw", OP8(0x6eLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "add unnormalized (long)" }, + { "dd", OP8(0x6dLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "divide (long)" }, + { "md", OP8(0x6cLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "multiply (long)" }, + { "sd", OP8(0x6bLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "subtract normalized (long)" }, + { "ad", OP8(0x6aLL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "add normalized (long)" }, + { "cd", OP8(0x69LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "compare (long)" }, + { "ld", OP8(0x68LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "load (long)" }, + { "mxd", OP8(0x67LL), MASK_RX_FERRD, INSTR_RX_FERRD, 3, 0, 0, "multiply (long to ext.)" }, + { "std", OP8(0x60LL), MASK_RX_FRRD, INSTR_RX_FRRD, 3, 0, 0, "store (long)" }, + { "sl", OP8(0x5fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "subtract logical" }, + { "al", OP8(0x5eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "add logical" }, + { "d", OP8(0x5dLL), MASK_RX_RERRD, INSTR_RX_RERRD, 3, 0, 0, "divide" }, + { "m", OP8(0x5cLL), MASK_RX_RERRD, INSTR_RX_RERRD, 3, 0, 0, "multiply" }, + { "s", OP8(0x5bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "subtract" }, + { "a", OP8(0x5aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "add" }, + { "c", OP8(0x59LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "compare" }, + { "l", OP8(0x58LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "load" }, + { "x", OP8(0x57LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "exclusive or" }, + { "o", OP8(0x56LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "or" }, + { "cl", OP8(0x55LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "compare logical" }, + { "n", OP8(0x54LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "and" }, + { "lae", OP8(0x51LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "load address extended" }, + { "st", OP8(0x50LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "store" }, + { "cvb", OP8(0x4fLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "convert to binary" }, + { "cvd", OP8(0x4eLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "convert to decimal" }, + { "bas", OP8(0x4dLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "branch and save" }, + { "mh", OP8(0x4cLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "multiply halfword" }, + { "sh", OP8(0x4bLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "subtract halfword" }, + { "ah", OP8(0x4aLL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "add halfword" }, + { "ch", OP8(0x49LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "compare halfword" }, + { "lh", OP8(0x48LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "load halfword" }, + { "b", OP16(0x47f0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "unconditional branch" }, + { "bno", OP16(0x47e0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not overflow / if not ones" }, + { "bnh", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on A not high" }, + { "bnp", OP16(0x47d0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not plus" }, + { "ble", OP16(0x47c0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on low or equal" }, + { "bnl", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on A not low" }, + { "bnm", OP16(0x47b0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not minus / if not mixed" }, + { "bhe", OP16(0x47a0LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on high or equal" }, + { "bnlh", OP16(0x4790LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not low or high" }, + { "be", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on A equal B" }, + { "bz", OP16(0x4780LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on zero / if zeros" }, + { "bne", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on A not equal B" }, + { "bnz", OP16(0x4770LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not zero / if not zeros" }, + { "blh", OP16(0x4760LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on low or high" }, + { "bnhe", OP16(0x4750LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not high or equal" }, + { "bl", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on A low" }, + { "bm", OP16(0x4740LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on minus / if mixed" }, + { "bnle", OP16(0x4730LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on not low or equal" }, + { "bh", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on A high" }, + { "bp", OP16(0x4720LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on plus" }, + { "bo", OP16(0x4710LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 0, "conditional branch on overflow / if ones" }, + { "bc", OP8(0x47LL), MASK_RX_URRD, INSTR_RX_URRD, 3, 0, 0, "branch on condition" }, + { "nop", OP16(0x4700LL), MASK_RX_0RRD, INSTR_RX_0RRD, 3, 0, 1, "no operation" }, + { "bct", OP8(0x46LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "branch on count" }, + { "bal", OP8(0x45LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "branch and link" }, + { "ex", OP8(0x44LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "execute" }, + { "ic", OP8(0x43LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "insert character" }, + { "stc", OP8(0x42LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "store character" }, + { "la", OP8(0x41LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "load address" }, + { "sth", OP8(0x40LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0, 0, "store halfword" }, + { "sur", OP8(0x3fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "subtract unnormalized (short)" }, + { "aur", OP8(0x3eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "add unnormalized (short)" }, + { "der", OP8(0x3dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "divide (short)" }, + { "mder", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "multiply short to long hfp" }, + { "mer", OP8(0x3cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "multiply (short to long)" }, + { "ser", OP8(0x3bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "subtract normalized (short)" }, + { "aer", OP8(0x3aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "add normalized (short)" }, + { "cer", OP8(0x39LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "compare (short)" }, + { "ler", OP8(0x38LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load (short)" }, + { "sxr", OP8(0x37LL), MASK_RR_FEFE, INSTR_RR_FEFE, 3, 0, 0, "subtract normalized (ext.)" }, + { "axr", OP8(0x36LL), MASK_RR_FEFE, INSTR_RR_FEFE, 3, 0, 0, "add normalized" }, + { "ledr", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load rounded (long to short)" }, + { "lrer", OP8(0x35LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load rounded (long to short)" }, + { "her", OP8(0x34LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "halve (short)" }, + { "lcer", OP8(0x33LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load complement (short)" }, + { "lter", OP8(0x32LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load and test (short)" }, + { "lner", OP8(0x31LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load negative (short)" }, + { "lper", OP8(0x30LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load positive (short)" }, + { "swr", OP8(0x2fLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "subtract unnormalized (long)" }, + { "awr", OP8(0x2eLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "add unnormalized (long)" }, + { "ddr", OP8(0x2dLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "divide (long)" }, + { "mdr", OP8(0x2cLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "multiply (long)" }, + { "sdr", OP8(0x2bLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "subtract normalized (long)" }, + { "adr", OP8(0x2aLL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "add normalized (long)" }, + { "cdr", OP8(0x29LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "compare (long)" }, + { "ldr", OP8(0x28LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load (long)" }, + { "mxdr", OP8(0x27LL), MASK_RR_FEF, INSTR_RR_FEF, 3, 0, 0, "multiply (long to ext.)" }, + { "mxr", OP8(0x26LL), MASK_RR_FEFE, INSTR_RR_FEFE, 3, 0, 0, "multiply (ext.)" }, + { "ldxr", OP8(0x25LL), MASK_RR_FFE, INSTR_RR_FFE, 3, 0, 0, "load rounded (ext. to long)" }, + { "lrdr", OP8(0x25LL), MASK_RR_FFE, INSTR_RR_FFE, 3, 0, 0, "load rounded (ext. to long)" }, + { "hdr", OP8(0x24LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "halve (long)" }, + { "lcdr", OP8(0x23LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load complement (long)" }, + { "ltdr", OP8(0x22LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load and test (long)" }, + { "lndr", OP8(0x21LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load negative (long)" }, + { "lpdr", OP8(0x20LL), MASK_RR_FF, INSTR_RR_FF, 3, 0, 0, "load positive (long)" }, + { "slr", OP8(0x1fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "subtract logical" }, + { "alr", OP8(0x1eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "add logical" }, + { "dr", OP8(0x1dLL), MASK_RR_RER, INSTR_RR_RER, 3, 0, 0, "divide" }, + { "mr", OP8(0x1cLL), MASK_RR_RER, INSTR_RR_RER, 3, 0, 0, "multiply" }, + { "sr", OP8(0x1bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "subtract" }, + { "ar", OP8(0x1aLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "add" }, + { "cr", OP8(0x19LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "compare" }, + { "lr", OP8(0x18LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "load" }, + { "xr", OP8(0x17LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "exclusive or" }, + { "or", OP8(0x16LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "or" }, + { "clr", OP8(0x15LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "compare logical" }, + { "nr", OP8(0x14LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "and" }, + { "lcr", OP8(0x13LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "load complement" }, + { "ltr", OP8(0x12LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "load and test" }, + { "lnr", OP8(0x11LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "load negative" }, + { "lpr", OP8(0x10LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "load positive" }, + { "clcl", OP8(0x0fLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "compare logical long" }, + { "mvcl", OP8(0x0eLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "move long" }, + { "basr", OP8(0x0dLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "branch and save" }, + { "bassm", OP8(0x0cLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "branch and save and set mode" }, + { "bsm", OP8(0x0bLL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "branch and set mode" }, + { "svc", OP8(0x0aLL), MASK_RR_U0, INSTR_RR_U0, 3, 0, 0, "supervisor call" }, + { "br", OP16(0x07f0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "unconditional branch" }, + { "bnor", OP16(0x07e0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not overflow / if not ones" }, + { "bnhr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on A not high" }, + { "bnpr", OP16(0x07d0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not plus" }, + { "bler", OP16(0x07c0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on low or equal" }, + { "bnlr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on A not low" }, + { "bnmr", OP16(0x07b0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not minus / if not mixed" }, + { "bher", OP16(0x07a0LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on high or equal" }, + { "bnlhr", OP16(0x0790LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not low or high" }, + { "ber", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on A equal B" }, + { "bzr", OP16(0x0780LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on zero / if zeros" }, + { "bner", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on A not equal B" }, + { "bnzr", OP16(0x0770LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not zero / if not zeros" }, + { "blhr", OP16(0x0760LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on low or high" }, + { "bnher", OP16(0x0750LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not high or equal" }, + { "blr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on A low" }, + { "bmr", OP16(0x0740LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on minus / if mixed" }, + { "bnler", OP16(0x0730LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on not low or equal" }, + { "bhr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on A high" }, + { "bpr", OP16(0x0720LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on plus" }, + { "bor", OP16(0x0710LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 0, "conditional branch on overflow / if ones" }, + { "bcr", OP8(0x07LL), MASK_RR_UR, INSTR_RR_UR, 3, 0, 0, "branch on condition" }, + { "nopr", OP16(0x0700LL), MASK_RR_0R, INSTR_RR_0R, 3, 0, 1, "no operation" }, + { "bctr", OP8(0x06LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "branch on count" }, + { "balr", OP8(0x05LL), MASK_RR_RR, INSTR_RR_RR, 3, 0, 0, "branch and link" }, + { "spm", OP8(0x04LL), MASK_RR_R0, INSTR_RR_R0, 3, 0, 0, "set program mask" }, + { "trap2", OP16(0x01ffLL), MASK_E, INSTR_E, 3, 0, 0, "trap" }, + { "sam64", OP16(0x010eLL), MASK_E, INSTR_E, 2, 2, 0, "set addressing mode 64" }, + { "sam31", OP16(0x010dLL), MASK_E, INSTR_E, 3, 2, 0, "set addressing mode 31" }, + { "sam24", OP16(0x010cLL), MASK_E, INSTR_E, 3, 2, 0, "set addressing mode 24" }, + { "tam", OP16(0x010bLL), MASK_E, INSTR_E, 3, 2, 0, "test addressing mode" }, + { "pfpo", OP16(0x010aLL), MASK_E, INSTR_E, 2, 5, 0, "perform floating point operation" }, + { "sckpf", OP16(0x0107LL), MASK_E, INSTR_E, 3, 0, 0, "set clock programmable field" }, + { "ptff", OP16(0x0104LL), MASK_E, INSTR_E, 2, 4, 0, "perform timing facility function" }, + { "upt", OP16(0x0102LL), MASK_E, INSTR_E, 3, 0, 0, "update tree" }, + { "pr", OP16(0x0101LL), MASK_E, INSTR_E, 3, 0, 0, "program return" } +}; + +const int s390_num_opcodes = + sizeof (s390_opcodes) / sizeof (s390_opcodes[0]); diff --git a/VEX/priv/objdump/s390.h b/VEX/priv/objdump/s390.h new file mode 100644 index 000000000..c0a396fc9 --- /dev/null +++ b/VEX/priv/objdump/s390.h @@ -0,0 +1,197 @@ +/* s390.h -- Header file for S390 opcode table + Copyright (C) 2000-2025 Free Software Foundation, Inc. + Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef S390_H +#define S390_H + +/* List of instruction sets variations. */ + +enum s390_opcode_mode_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ZARCH + }; + +enum s390_opcode_cpu_val + { + S390_OPCODE_G5 = 0, + S390_OPCODE_G6, + S390_OPCODE_Z900, + S390_OPCODE_Z990, + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC, + S390_OPCODE_Z10, + S390_OPCODE_Z196, + S390_OPCODE_ZEC12, + S390_OPCODE_Z13, + S390_OPCODE_ARCH12, + S390_OPCODE_ARCH13, + S390_OPCODE_ARCH14, + S390_OPCODE_ARCH15, + S390_OPCODE_MAXCPU + }; + +/* Values defined for the flags field of a struct s390_opcode. */ + +/* Last one or two instruction operands are optional. */ +#define S390_INSTR_FLAG_OPTPARM 0x1 +#define S390_INSTR_FLAG_OPTPARM2 0x2 + +/* Instruction requires a specific facility. */ +#define S390_INSTR_FLAG_HTM 0x4 +#define S390_INSTR_FLAG_VX 0x8 +#define S390_INSTR_FLAG_FACILITY_MASK 0xc + +/* Instruction annotations for jump visualization. */ +#define S390_INSTR_FLAG_CLASS_BRANCH 0x10 +#define S390_INSTR_FLAG_CLASS_RELATIVE 0x20 +#define S390_INSTR_FLAG_CLASS_CONDITIONAL 0x40 +#define S390_INSTR_FLAG_CLASS_SUBROUTINE 0x80 +#define S390_INSTR_FLAG_CLASS_MASK 0xf0 + +#define S390_INSTR_FLAGS_CLASS_JUMP \ + (S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE) + +#define S390_INSTR_FLAGS_CLASS_CONDJUMP \ + (S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE \ + | S390_INSTR_FLAG_CLASS_CONDITIONAL) + +#define S390_INSTR_FLAGS_CLASS_JUMPSR \ + (S390_INSTR_FLAG_CLASS_BRANCH | S390_INSTR_FLAG_CLASS_RELATIVE \ + | S390_INSTR_FLAG_CLASS_SUBROUTINE) + +/* Instruction is an .insn pseudo-mnemonic. */ +#define S390_INSTR_FLAG_PSEUDO_MNEMONIC 0x100 + +/* The opcode table is an array of struct s390_opcode. */ + +struct s390_opcode + { + /* The opcode name (mnemonic). */ + const char * name; + + /* The opcode itself. Those bits which will be filled in with + operands are zeroes. */ + unsigned char opcode[6]; + + /* The opcode mask. This is used by the disassembler. This is a + mask containing ones indicating those bits which must match the + opcode field, and zeroes indicating those bits which need not + match (and are presumably filled in by operands). */ + unsigned char mask[6]; + + /* The opcode length in bytes. */ + int oplen; + + /* An array of operand codes. Each code is an index into the + operand table. They appear in the order which the operands must + appear in assembly code, and are terminated by a zero. */ + unsigned char operands[6]; + + /* Bitmask of execution modes this opcode is available for. */ + unsigned int modes; + + /* First cpu this opcode is available for. */ + enum s390_opcode_cpu_val min_cpu; + + /* Instruction specific flags. */ + unsigned int flags; + + /* Instruction description. */ + const char * description; + }; + +/* The table itself is sorted by major opcode number, and is otherwise + in the order in which the disassembler should consider + instructions. */ +extern const struct s390_opcode s390_opcodes[]; +extern const int s390_num_opcodes; + +/* A opcode format table for the .insn pseudo mnemonic. */ +extern const struct s390_opcode s390_opformats[]; +extern const int s390_num_opformats; + +/* The operands table is an array of struct s390_operand. */ + +struct s390_operand + { + /* The number of bits in the operand. */ + int bits; + + /* How far the operand is left shifted in the instruction. */ + int shift; + + /* One bit syntax flags. */ + unsigned long flags; + }; + +/* Elements in the table are retrieved by indexing with values from + the operands field of the s390_opcodes table. */ + +extern const struct s390_operand s390_operands[]; + +/* Values defined for the flags field of a struct s390_operand. */ + +/* This operand names a register. The disassembler uses this to print + register names with a leading 'r'. */ +#define S390_OPERAND_GPR 0x1 + +/* This operand names a floating point register. The disassembler + prints these with a leading 'f'. */ +#define S390_OPERAND_FPR 0x2 + +/* This operand names an access register. The disassembler + prints these with a leading 'a'. */ +#define S390_OPERAND_AR 0x4 + +/* This operand names a control register. The disassembler + prints these with a leading 'c'. */ +#define S390_OPERAND_CR 0x8 + +/* This operand is a displacement. */ +#define S390_OPERAND_DISP 0x10 + +/* This operand names a base register. */ +#define S390_OPERAND_BASE 0x20 + +/* This operand names an index register, it can be skipped. */ +#define S390_OPERAND_INDEX 0x40 + +/* This operand is a relative branch displacement. The disassembler + prints these symbolically if possible. */ +#define S390_OPERAND_PCREL 0x80 + +/* This operand takes signed values. */ +#define S390_OPERAND_SIGNED 0x100 + +/* This operand is a length. */ +#define S390_OPERAND_LENGTH 0x200 + +/* The operand needs to be a valid GP or FP register pair. */ +#define S390_OPERAND_REG_PAIR 0x400 + +/* This operand names a vector register. The disassembler uses this + to print register names with a leading 'v'. */ +#define S390_OPERAND_VR 0x800 + +#define S390_OPERAND_CP16 0x1000 + +#endif /* S390_H */ diff --git a/VEX/priv/objdump/stubs.h b/VEX/priv/objdump/stubs.h new file mode 100644 index 000000000..0b71c6908 --- /dev/null +++ b/VEX/priv/objdump/stubs.h @@ -0,0 +1,49 @@ +/* + This file is part of Valgrind, a dynamic binary instrumentation + framework. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 3 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, see . + + The GNU General Public License is contained in the file COPYING. +*/ + +#ifndef __VEX_STUBS_H +#define __VEX_STUBS_H + +/* This file contains things that need to be defined to get the + objdump stuff compiled and to avoid pulling in more header files. */ + +#define bool _Bool +#define true 1 +#define false 0 + +typedef unsigned char bfd_byte; // uint8_t originally +typedef unsigned long long bfd_vma; // uint64_t originally +typedef unsigned long size_t; + +#define ATTRIBUTE_FPTR_PRINTF_2 \ + __attribute__ ((__format__ (__printf__, 2, 3))) \ + __attribute__ ((__nonnull__ (2))); +#define ATTRIBUTE_FPTR_PRINTF_3 \ + __attribute__ ((__format__ (__printf__, 3, 4))) \ + __attribute__ ((__nonnull__ (3))) +#define ATTRIBUTE_UNUSED __attribute__ ((unused)) + +/* This is defined in VEX, too. But we want to avoid mixing VEX + and binutils headers. */ +#ifndef NULL +#define NULL ((void *)0) +#endif + +#endif // __VEX_STUBS_H diff --git a/VEX/priv/s390_disasm.c b/VEX/priv/s390_disasm.c deleted file mode 100644 index d2325e7ca..000000000 --- a/VEX/priv/s390_disasm.c +++ /dev/null @@ -1,1267 +0,0 @@ -/* -*- mode: C; c-basic-offset: 3; -*- */ - -/*---------------------------------------------------------------*/ -/*--- begin s390_disasm.c ---*/ -/*---------------------------------------------------------------*/ - -/* - This file is part of Valgrind, a dynamic binary instrumentation - framework. - - Copyright IBM Corp. 2010-2017 - - This program is free software; you can redistribute it and/or - modify it under the terms of the GNU General Public License as - published by the Free Software Foundation; either version 3 of the - License, or (at your option) any later version. - - This program is distributed in the hope that it will be useful, but - WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, see . - - The GNU General Public License is contained in the file COPYING. -*/ - -/* Contributed by Florian Krohm */ - -#include "libvex_basictypes.h" -#include "main_util.h" // vassert -#include "main_globals.h" // vex_traceflags -#include "s390_defs.h" // S390_MAX_MNEMONIC_LEN -#include "s390_disasm.h" - -static HChar *s390_disasm_aux(const s390_opnd *, const HChar *, HChar *, - Int (*)(UInt, UInt, UInt *)); - -/* Return the mnemonic padded with blanks to its right */ -static const HChar * -padmnm(const HChar *mnm) -{ - vassert(vex_strlen(mnm) <= S390_MAX_MNEMONIC_LEN); - - static HChar buf[S390_MAX_MNEMONIC_LEN + 1]; - - vex_sprintf(buf, "%-*s", S390_MAX_MNEMONIC_LEN, mnm); - - return buf; -} - - -/* Return the name of a general purpose register for dis-assembly purposes. */ -static const HChar * -gpr_operand(UInt archreg) -{ - static const HChar names[16][5] = { - "%r0", "%r1", "%r2", "%r3", - "%r4", "%r5", "%r6", "%r7", - "%r8", "%r9", "%r10", "%r11", - "%r12", "%r13", "%r14", "%r15", - }; - - vassert(archreg < 16); - - return names[archreg]; -} - - -/* Return the name of a floating point register for dis-assembly purposes. */ -static const HChar * -fpr_operand(UInt archreg) -{ - static const HChar names[16][5] = { - "%f0", "%f1", "%f2", "%f3", - "%f4", "%f5", "%f6", "%f7", - "%f8", "%f9", "%f10", "%f11", - "%f12", "%f13", "%f14", "%f15", - }; - - vassert(archreg < 16); - - return names[archreg]; -} - - -/* Return the name of an access register for dis-assembly purposes. */ -static const HChar * -ar_operand(UInt archreg) -{ - static const HChar names[16][5] = { - "%a0", "%a1", "%a2", "%a3", - "%a4", "%a5", "%a6", "%a7", - "%a8", "%a9", "%a10", "%a11", - "%a12", "%a13", "%a14", "%a15", - }; - - vassert(archreg < 16); - - return names[archreg]; -} - - -/* Return the name of a vector register for dis-assembly purposes. */ -static const HChar * -vr_operand(UInt archreg) -{ - static const HChar names[32][5] = { - "%v0", "%v1", "%v2", "%v3", - "%v4", "%v5", "%v6", "%v7", - "%v8", "%v9", "%v10", "%v11", - "%v12", "%v13", "%v14", "%v15", - "%v16", "%v17", "%v18", "%v19", - "%v20", "%v21", "%v22", "%v23", - "%v24", "%v25", "%v26", "%v27", - "%v28", "%v29", "%v30", "%v31", - }; - - vassert(archreg < 32); - - return names[archreg]; -} - - -/* Common function used to construct a mnemonic based on a condition code - mask. */ -static const HChar * -construct_mnemonic(const HChar *prefix, const HChar *suffix, UInt mask) -{ - static HChar buf[S390_MAX_MNEMONIC_LEN + 1]; - - static HChar mask_id[16][4] = { - "", /* 0 -> unused */ - "o", "h", "nle", "l", "nhe", "lh", "ne", - "e", "nlh", "he", "nl", "le", "nh", "no", - "" /* 15 -> unused */ - }; - - /* Guard against buffer overflow */ - vassert(vex_strlen(prefix) + vex_strlen(suffix) + - sizeof mask_id[0] <= sizeof buf); - - HChar *p = buf; - - p += vex_sprintf(p, "%s%s%s", prefix, mask_id[mask], suffix); - *p = '\0'; - - return buf; -} - - -/* An operand with a base register, an index register, and a displacement. - If the displacement is signed, the rightmost 20 bit of D need to be - sign extended */ -static HChar * -dxb_operand(HChar *p, UInt d, UInt x, UInt b, Bool displacement_is_signed) -{ - if (displacement_is_signed) { - Int displ = (Int)(d << 12) >> 12; /* sign extend */ - - p += vex_sprintf(p, "%d", displ); - } else { - p += vex_sprintf(p, "%u", d); - } - if (x != 0) { - p += vex_sprintf(p, "(%s,%s)", gpr_operand(x), - b != 0 ? gpr_operand(b) : "0"); - } else { - if (b != 0) { - p += vex_sprintf(p, "(%s)", gpr_operand(b)); - } - } - - return p; -} - - -/* An operand with base register, unsigned length, and a 12-bit - unsigned displacement */ -static HChar * -udlb_operand(HChar *p, UInt d, UInt length, UInt b) -{ - p += vex_sprintf(p, "%u", d); - p += vex_sprintf(p, "(%u", length + 1); // actual length is +1 - p += vex_sprintf(p, ",%s", b != 0 ? gpr_operand(b) : "0"); - p += vex_sprintf(p, ")"); - - return p; -} - - -/* An operand with a base register, an vector register, and a displacement. - If the displacement is signed, the rightmost 20 bit of D need to be - sign extended */ -static HChar * -dvb_operand(HChar *p, UInt d, UInt v, UInt b, Bool displacement_is_signed) -{ - if (displacement_is_signed) { - Int displ = (Int)(d << 12) >> 12; /* sign extend */ - - p += vex_sprintf(p, "%d", displ); - } else { - p += vex_sprintf(p, "%u", d); - } - p += vex_sprintf(p, "(%s", vr_operand(v)); - p += vex_sprintf(p, ",%s", b != 0 ? gpr_operand(b) : "0"); - p += vex_sprintf(p, ")"); - - return p; -} - - -/* Return the number of MASK operands */ -static UInt -mask_count(const s390_opnd *opnds) -{ - UInt num_masks = 0; - - for (UInt ix = 0; opnds[ix].kind != S390_OPND_DONE; ++ix) { - if (opnds[ix].kind == S390_OPND_MASK) { - ++num_masks; - } - } - return num_masks; -} - - -/* Given the mask number return its index in the operands array. - Mask numbers begin at 1. */ -static UInt -get_mask_index(const s390_opnd *opnds, UInt mask_no) -{ - vassert(mask_no <= mask_count(opnds)); - - UInt count = 0; - - for (UInt ix = 0; opnds[ix].kind != S390_OPND_DONE; ++ix) { - if (opnds[ix].kind == S390_OPND_MASK) { - ++count; - if (count == mask_no) - return ix; - } - } - /* not reachable */ - return 0; -} - - -/* It is expected that OPNDS contains exactly one MASK operand. Return - its index. Assert, if there is no mask or multiple mask fields. */ -static UInt -unique_mask_index(const s390_opnd *opnds) -{ - vassert(mask_count(opnds) == 1); - - return get_mask_index(opnds, 1); -} - - -/* Special handling for the BCR opcode */ -HChar * -bcr_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *xmnm; - UInt mask = opnds[1].mask; - - if (mask == 0) - xmnm = "nopr"; - else if (mask == 15) - xmnm = "br"; - else - xmnm = construct_mnemonic("b", "r", mask); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -/* Special handling for the BC opcode */ -HChar * -bc_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *xmnm; - UInt mask = opnds[1].mask; - - if (mask == 0) { - xmnm = "nop"; - if (opnds[2].d == 0 && opnds[2].b == 0 && opnds[2].x == 0) - return p += vex_sprintf(p, "nop"); - } else if (mask == 15) - xmnm = "b"; - else - xmnm = construct_mnemonic("b", "", mask); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -/* Special handling for the BRC opcode */ -HChar * -brc_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *xmnm; - UInt mask = opnds[1].mask; - - if (mask == 0) - xmnm = "jnop"; - else if (mask == 15) - xmnm = "j"; - else - xmnm = construct_mnemonic("j", "", mask); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -/* Special handling for the BRCL opcode */ -HChar * -brcl_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *xmnm; - UInt mask = opnds[1].mask; - - if (mask == 0) - xmnm = "jgnop"; - else if (mask == 15) - xmnm = "jg"; - else - xmnm = construct_mnemonic("jg", "", mask); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -/* Return 1, if mask should be printed. In *VALUE return the mask value - that should be printed. */ -static Int -cabt_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value) -{ - *value = mask; - return (mask & 1) || mask == 0 || mask == 14; -} - - -/* Special handling for the various compare and branch / trap opcodes: - CLFIT, CLGIT, C[G]IT, C[L][G]RJ, C[L][G]IJ, C[L][G]IB, C[L][G]RB, - CL[G]T, C[L][G]RT -*/ -HChar * -cabt_disasm(const s390_opnd *opnds, HChar *p) -{ - static HChar xmnm[S390_MAX_MNEMONIC_LEN + 1]; - - static const HChar suffix[8][3] = { - "", "h", "l", "ne", "e", "nl", "nh", "" - }; - - const HChar *base = opnds[0].xmnm.base; - - /* Guard against buffer overflow */ - vassert(vex_strlen(base) + sizeof suffix[0] <= sizeof xmnm); - - HChar *x = xmnm; - UInt mask = opnds[unique_mask_index(opnds)].mask; - - x += vex_sprintf(x, "%s", base); - if (! (mask & 0x1)) { - x += vex_sprintf(x, "%s", suffix[mask >> 1]); - } - *x = '\0'; - - return s390_disasm_aux(opnds, xmnm, p, cabt_mh); -} - - -static Int -cls_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value) -{ - *value = mask; - return mask == 0 || mask == 15; -} - - -/* Special handling for the various conditional load / store opcodes: - LOC[G]R, LOCFHR, LOC[G]HI, LOCHHI, LOC[G], LOCFH, STOC[G], STOFH - Also used for SEL[G]R and SELFHR -*/ -HChar * -cls_disasm(const s390_opnd *opnds, HChar *p) -{ - UInt mask = opnds[unique_mask_index(opnds)].mask; - const HChar *base = opnds[0].xmnm.base; - const HChar *xmnm = construct_mnemonic(base, "", mask); - - return s390_disasm_aux(opnds, xmnm, p, cls_mh); -} - - -static Int -bic_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value) -{ - *value = mask; - return mask == 0; -} - - -/* Special handling for the BIC opcode */ -HChar * -bic_disasm(const s390_opnd *opnds, HChar *p) -{ - UInt mask = opnds[1].mask; - const HChar *xmnm; - - if (mask == 0) { - /* There is no special opcode when mask == 0. */ - xmnm = opnds[0].xmnm.base; - } else { - xmnm = construct_mnemonic("bi", "", mask); - } - - return s390_disasm_aux(opnds, xmnm, p, bic_mh); -} - - -/* Special handling for the VGBM opcode */ -HChar * -vgbm_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *xmnm; - const HChar *v1 = vr_operand(opnds[1].regno); - UInt i2 = opnds[2].u; - - if (i2 == 0) { - xmnm = padmnm("vzero"); - p += vex_sprintf(p, "%s %s", xmnm, v1); - } else if (i2 == 0xffff) { - xmnm = padmnm("vone"); - p += vex_sprintf(p, "%s %s", xmnm, v1); - } else { - xmnm = padmnm(opnds[0].xmnm.base); - p += vex_sprintf(p, "%s %s,%u", xmnm, v1, i2); - } - return p; -} - - -static Int -mask0_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value) -{ - *value = mask; - return mask != 0; -} - - -/* Write out the operands, except if the unique mask is 0 do not write it */ -HChar * -mask0_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 1); - - const HChar *mnm = opnds[0].xmnm.base; - - if (vex_streq(mnm, "cu12") && opnds[unique_mask_index(opnds)].mask == 0) - mnm = "cutfu"; - if (vex_streq(mnm, "cu21") && opnds[unique_mask_index(opnds)].mask == 0) - mnm = "cuutf"; - - return s390_disasm_aux(opnds, mnm, p, mask0_mh); -} - - -/* Opcode is expected to have a single MASK operand. Use its value - to determine a single-character suffix to be appended to the base - mnemonic. The mask itself is not printed. */ -HChar * -va_like_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar suffix[] = { 'b', 'h', 'f', 'g', 'q' }; - const HChar *base = opnds[0].xmnm.base; - UInt mask = opnds[unique_mask_index(opnds)].mask; - HChar xmnm[vex_strlen(base) + 2 + 1]; - HChar extra = '\0'; - - vassert(mask < sizeof suffix); - - if (mask == 1 && - (vex_streq(base, "vupl") || vex_streq(base, "vmal") || - vex_streq(base, "vml"))) { - extra = 'w'; - } - vex_sprintf(xmnm, "%s%c%c", base, suffix[mask], extra); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -/* Opcode is expected to have two MASK operands. Use their values - to determine a suffix to be appended to the base mnemonic. The - masks themselves are not printed. */ -HChar * -vch_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix1[] = { 'b', 'h', 'f', 'g' }; - const HChar suffix2[] = { '\0', 's' }; - const HChar *base = opnds[0].xmnm.base; - UInt m4 = opnds[get_mask_index(opnds, 1)].mask; - UInt m5 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + 2 + 1]; - - vassert(m4 < sizeof suffix1); - vassert(m5 < sizeof suffix2); - - vex_sprintf(xmnm, "%s%c%c", base, suffix1[m4], suffix2[m5]); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -static Int -always_mh(UInt ix __attribute__((unused)), - UInt mask, UInt *value) -{ - *value = mask; - return 1; -} - - -static Int -never_mh(UInt ix __attribute__((unused)), - UInt mask, UInt *value) -{ - *value = mask; - return 0; -} - - -HChar * -vfce_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 3); - - const HChar suffix1[][3] = { "sb", "db", "xb" }; - const HChar suffix2[] = { '\0', 's' }; - const HChar *base = opnds[0].xmnm.base; - UInt m4 = opnds[get_mask_index(opnds, 1)].mask; - UInt m5 = opnds[get_mask_index(opnds, 2)].mask; - UInt m6 = opnds[get_mask_index(opnds, 3)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix1 - 1) + 1 + 1]; - - if (m4 == 4 && (m5 == 0 || m5 == 4)) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m4 - 2 < sizeof suffix1 / sizeof *suffix1); - vassert(m6 < sizeof suffix2); - - vex_sprintf(xmnm, "%s%s%c", base, suffix1[m4 - 2], suffix2[m6]); - - if (m5 & 0x8) xmnm[0] = 'w'; - if (m5 & 0x4) xmnm[2] = 'k'; - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -HChar * -vfmix_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[][3] = { "sb", "db", "xb" }; - const HChar *base = opnds[0].xmnm.base; - UInt m4 = opnds[get_mask_index(opnds, 1)].mask; - UInt m5 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix - 1) + 1]; - - if (m4 == 4 && m5 == 0) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m4 - 2 < sizeof suffix / sizeof *suffix); - - vex_sprintf(xmnm, "%s%s", base, suffix[m4 - 2]); - - if (m5 & 0x8) xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -HChar * -vfa_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[][3] = { "sb", "db", "xb" }; - const HChar *base = opnds[0].xmnm.base; - UInt m4 = opnds[get_mask_index(opnds, 1)].mask; - UInt m5 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix - 1) + 1]; - - if (m4 == 4 && m5 == 0) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m4 - 2 < sizeof suffix / sizeof *suffix); - - vex_sprintf(xmnm, "%s%s", base, suffix[m4 - 2]); - - if (m5 & 0x8) xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -/* Also used for VFEE, VFENE, and VSTRS. But for those opcodes m5 < 8. - Hence, the return value is 0 and no mask will be written for - those opcodes. */ -static Int -vfae_mh(UInt ix, UInt mask, UInt *value) -{ - *value = mask & 0xC; - return (ix == 5) && (mask & 0xC); -} - - -HChar * -vfae_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[] = { 'b', 'h', 'f' }; - const HChar *base = opnds[0].xmnm.base; - - UInt m4 = opnds[get_mask_index(opnds, 1)].mask; - UInt m5 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + 3 + 1]; - - HChar s = (m5 & 0x1) ? 's' : '\0'; - HChar z = (m5 & 0x2) ? 'z' : '\0'; - - vex_sprintf(xmnm, "%s%c%c%c", base, z, suffix[m4], s); - - return s390_disasm_aux(opnds, xmnm, p, vfae_mh); -} - - -HChar * -vfms_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[][3] = { "sb", "db", "xb" }; - const HChar *base = opnds[0].xmnm.base; - UInt m5 = opnds[get_mask_index(opnds, 1)].mask; - UInt m6 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix - 1) + 1]; - - if (m6 == 4 && m5 == 0) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m6 - 2 < sizeof suffix / sizeof *suffix); - - vex_sprintf(xmnm, "%s%s", base, suffix[m6 - 2]); - - if (m5 & 0x8) xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -static Int -vmsl_mh(UInt ix, UInt mask, UInt *value) -{ - *value = mask; - return ix == 6; -} - - -HChar * -vmsl_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[] = { 'g' }; - const HChar *base = opnds[0].xmnm.base; - UInt m5 = opnds[get_mask_index(opnds, 1)].mask; - /* m6 does not influence the extended mnemonic */ - HChar xmnm[vex_strlen(base) + 1 + 1]; - - vassert(m5 - 3 < sizeof suffix); - - vex_sprintf(xmnm, "%s%c", base, suffix[m5 - 3]); - - return s390_disasm_aux(opnds, xmnm, p, vmsl_mh); -} - - -static Int -vstrc_mh(UInt ix, UInt mask, UInt *value) -{ - *value = mask & 0xC; - return (ix == 6) && (mask & 0xC); -} - - -HChar * -vstrc_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[] = { 'b', 'h', 'f' }; - const HChar *base = opnds[0].xmnm.base; - - UInt m5 = opnds[get_mask_index(opnds, 1)].mask; - UInt m6 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + 3 + 1]; - - HChar s = (m6 & 0x1) ? 's' : '\0'; - HChar z = (m6 & 0x2) ? 'z' : '\0'; - - vex_sprintf(xmnm, "%s%c%c%c", base, z, suffix[m5], s); - - return s390_disasm_aux(opnds, xmnm, p, vstrc_mh); -} - - -HChar * -vllebrz_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 1); - - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - const HChar *xmnm; - - switch (m3) { - case 1: xmnm = "vllebrzh"; break; - case 2: xmnm = "vllebrzf"; break; - case 3: xmnm = "ldrv"; break; - case 6: xmnm = "lerv"; break; - default: vassert(0); - } - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -HChar * -vstebrf_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 1); - - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - const HChar *xmnm; - - if (m3 == 0) - xmnm = "sterv"; - else - xmnm = opnds[0].xmnm.base; - - return s390_disasm_aux(opnds, xmnm, p, mask0_mh); -} - - -HChar * -vstebrg_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 1); - - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - const HChar *xmnm; - - if (m3 == 0) - xmnm = "stdrv"; - else - xmnm = opnds[0].xmnm.base; - - return s390_disasm_aux(opnds, xmnm, p, mask0_mh); -} - - -HChar * -vllez_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 1); - - const HChar suffix[][3] = { "b", "h", "f", "g", "", "", "lf" }; - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix - 1) + 1]; - - vassert(m3 < sizeof suffix / sizeof *suffix); - vex_sprintf(xmnm, "%s%s", base, suffix[m3]); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -HChar * -wfc_like_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[][3] = { "sb", "db", "xb" }; - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix - 1) + 1]; - - vassert(m3 - 2 < sizeof suffix / sizeof *suffix); - - vex_sprintf(xmnm, "%s%s", base, suffix[m3 - 2]); - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -HChar * -vfll_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[] = { 's', 'd' }; - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + 1 + 1]; - - if (m3 == 3 && m4 == 0) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m3 - 2 < sizeof suffix); - vex_sprintf(xmnm, "%s%c", base, suffix[m3 - 2]); - - if (m4 == 8) - xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -static Int -always_m4(UInt ix, UInt mask, UInt *value) -{ - *value = mask & 0x4; - return ix == 4; -} - - -HChar * -vflr_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[] = { 'd', 'x' }; - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + 1 + 1]; - - if (m3 == 4 && m4 < 8) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m3 - 3 < sizeof suffix); - vex_sprintf(xmnm, "%s%c", base, suffix[m3 - 3]); - - if (m4 & 0x8) - xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, always_m4); -} - - -HChar * -vfi_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar suffix[][3] = { "sb", "db", "xb" }; - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(base) + (sizeof *suffix - 1) + 1]; - - if (m3 == 4 && m4 < 8) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(m3 - 2 < sizeof suffix / sizeof *suffix); - vex_sprintf(xmnm, "%s%s", base, suffix[m3 - 2]); - - if (m4 & 0x8) - xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, always_m4); -} - - -HChar * -vfpso_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 3); - - const HChar suffix1[] = { 'c', 'n', 'p' }; - const HChar suffix2[][3] = { "sb", "db", "xb" }; - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - UInt m5 = opnds[get_mask_index(opnds, 3)].mask; - HChar xmnm[vex_strlen(base) + 1 + (sizeof *suffix2 - 1) + 1]; - - if (m3 == 4 && m4 == 0) - return s390_disasm_aux(opnds, base, p, always_mh); - - vassert(vex_strlen("vfl") <= vex_strlen(base)); - vassert(m5 < sizeof suffix1); - vassert(m3 - 2 < sizeof suffix2 / sizeof *suffix2); - vex_sprintf(xmnm, "%s%c%s", "vfl", suffix1[m5], suffix2[m3 - 2]); - - if (m4 & 0x8) - xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, NULL); -} - - -static Int -vcgd_mh(UInt ix, UInt mask, UInt *value) -{ - *value = mask; - if (ix == 5) - return 1; - if (ix == 4) { - if (mask >= 8) - *value = mask - 8; - return 1; - } - return 0; -} - - -static HChar * -vcgd_like_disasm(const s390_opnd *opnds, const HChar *mnm[2], HChar *p) -{ - vassert(mask_count(opnds) == 3); - vassert(vex_strlen(mnm[0]) == vex_strlen(mnm[1])); - - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - HChar xmnm[vex_strlen(mnm[0]) + 1]; - - vex_sprintf(xmnm, "%s", mnm[m3 - 2]); - if (m4 & 0x8) - xmnm[0] = 'w'; - - return s390_disasm_aux(opnds, xmnm, p, vcgd_mh); -} - - -HChar * -vcgd_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *mnm[2] = { "vcfeb", "vcgdb" }; - - return vcgd_like_disasm(opnds, mnm, p); -} - - -HChar * -vcdg_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *mnm[2] = { "vcefb", "vcdgb" }; - - return vcgd_like_disasm(opnds, mnm, p); -} - - -HChar * -vclgd_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *mnm[2] = { "vclfeb", "vclgdb" }; - - return vcgd_like_disasm(opnds, mnm, p); -} - - -HChar * -vcgld_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *mnm[2] = { "vcelfb", "vcdlgb" }; - - return vcgd_like_disasm(opnds, mnm, p); -} - - -/* Used by BFP / DFP convert from fixed / logical opcodes - - 1) Mnemonics ending in 'A', e.g. CEFBRA - a) m3 == m4 == 0 --> CEFBR and no mask values written - b) otherwise --> CEFBRA and both mask values written - - 2) Mnemonics for "logical" opcodes, e.g. CELFBR - These do not end in 'A' - --> mnemonic unchanged, both mask values written - - 3) Neither #1 nor #2, e.g. CDFTR - --> mnemonic unchanged, both mask values written -*/ -HChar * -fp_convf_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar *base = opnds[0].xmnm.base; - UInt m3 = opnds[get_mask_index(opnds, 1)].mask; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - UInt len = vex_strlen(base); - - HChar xmnm[len + 1]; - - vex_sprintf(xmnm, "%s", base); - - if (xmnm[len - 1] == 'a' && m3 + m4 == 0) { - xmnm[len - 1] = '\0'; - return s390_disasm_aux(opnds, xmnm, p, never_mh); - } - return s390_disasm_aux(opnds, xmnm, p, always_mh); -} - - -/* Return 1, if mask should be printed. In *VALUE return the mask value - that should be printed. */ -static Int -fp_convt_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value) -{ - *value = mask; - return (ix == 2 || mask != 0) ? 1 : 0; -} - - -/* Used by BFP / DFP convert to fixed / logical opcodes - - 1) Mnemonics ending in 'A', e.g. CFEBRA - a) m4 == 0 --> CFEBR and no mask values written - b) otherwise --> CFEBRA and both mask values written - - 2) Mnemonics for "logical" opcodes, e.g. CLFEBR - These do not end in 'A' - --> mnemonic unchanged, both mask values written - - 3) Neither #1 nor #2, e.g. CFDTR - --> mnemonic unchanged, both mask values written -*/ -HChar * -fp_convt_disasm(const s390_opnd *opnds, HChar *p) -{ - vassert(mask_count(opnds) == 2); - - const HChar *base = opnds[0].xmnm.base; - UInt m4 = opnds[get_mask_index(opnds, 2)].mask; - UInt len = vex_strlen(base); - - HChar xmnm[len + 1]; - - vex_sprintf(xmnm, "%s", base); - - if (xmnm[len - 1] == 'a' && m4 == 0) { - xmnm[len - 1] = '\0'; - return s390_disasm_aux(opnds, xmnm, p, fp_convt_mh); - } - return s390_disasm_aux(opnds, xmnm, p, always_mh); -} - - -HChar * -adtra_like_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *base = opnds[0].xmnm.base; - UInt m4 = opnds[get_mask_index(opnds, 1)].mask; - UInt len = vex_strlen(base); - - HChar xmnm[len + 1]; - - vex_sprintf(xmnm, "%s", base); - - if (xmnm[len - 1] == 'a' && m4 == 0) { - xmnm[len - 1] = '\0'; - } - return s390_disasm_aux(opnds, xmnm, p, mask0_mh); -} - - -static Int -rotate_mh(UInt ix __attribute__((unused)), UInt mask, UInt *value) -{ - *value = mask; - if (ix == 5 && mask == 0) return 0; - if (ix == 3) // rosbg, etc - *value = mask & ~0x80; - if (ix == 4) // risbg - *value = mask & ~0x80; - return 1; -} - - -HChar * -rotate_disasm(const s390_opnd *opnds, HChar *p) -{ - const HChar *base = opnds[0].xmnm.base; - UInt len = vex_strlen(base); - HChar xmnm[len + 1]; - - if (opnds[0].xmnm.base[1] == 'i') - vex_sprintf(xmnm, "%s%c", base, (opnds[4].u & 0x80) ? 'z' : '\0'); - else - vex_sprintf(xmnm, "%s%c", base, (opnds[3].u & 0x80) ? 't' : '\0'); - - return s390_disasm_aux(opnds, xmnm, p, rotate_mh); -} - - -/* Write out OPNDS. MH is a mask handler. It decides whether or not a - MASK operand is written and if so, massages the mask value as needed. */ -static HChar * -s390_disasm_aux(const s390_opnd *opnds, const HChar *xmnm, HChar *p, - Int (*mh)(UInt, UInt, UInt *)) -{ - vassert(opnds[0].kind == S390_OPND_MNM || - opnds[0].kind == S390_OPND_XMNM); - - Int write_separator = 0; // no separator after mnemonic - - for (UInt ix = 0; opnds[ix].kind != S390_OPND_DONE; ++ix) { - const s390_opnd *opnd = opnds + ix; - - switch (opnd->kind) { - case S390_OPND_MNM: - p += vex_sprintf(p, "%s", padmnm(opnd->mnm)); - *p++ = ' '; - break; - - case S390_OPND_XMNM: - p += vex_sprintf(p, "%s", padmnm(xmnm)); - *p++ = ' '; - break; - - case S390_OPND_GPR: - p += vex_sprintf(p, "%s", gpr_operand(opnd->regno)); - break; - - case S390_OPND_FPR: - p += vex_sprintf(p, "%s", fpr_operand(opnd->regno)); - break; - - case S390_OPND_AR: - p += vex_sprintf(p, "%s", ar_operand(opnd->regno)); - break; - - case S390_OPND_VR: - p += vex_sprintf(p, "%s", vr_operand(opnd->regno)); - break; - - case S390_OPND_MASK: { - UInt value; - if (mh && mh(ix, opnd->mask, &value)) - p += vex_sprintf(p, "%u", value); - else - write_separator = 0; - break; - } - - case S390_OPND_UINT: - p += vex_sprintf(p, "%u", opnd->u); - break; - - case S390_OPND_INT: - p += vex_sprintf(p, "%d", opnd->i); - break; - - case S390_OPND_PCREL: { - Long offset = opnd->pcrel; - - /* Convert # halfwords to # bytes */ - offset <<= 1; - - if (offset < 0) { - p += vex_sprintf(p, ".%lld", offset); - } else { - p += vex_sprintf(p, ".+%lld", offset); - } - break; - } - - case S390_OPND_SDXB: { - UInt d = opnd->d; - UInt x = opnd->x; - UInt b = opnd->b; - - p = dxb_operand(p, d, x, b, 1 /* signed_displacement */); - break; - } - - case S390_OPND_UDXB: { - UInt d = opnd->d; - UInt x = opnd->x; - UInt b = opnd->b; - - p = dxb_operand(p, d, x, b, 0 /* signed_displacement */); - break; - } - - case S390_OPND_UDLB: { - UInt d = opnd->d; - UInt l = opnd->l; - UInt b = opnd->b; - - p = udlb_operand(p, d, l, b); - break; - } - - case S390_OPND_UDVB: { - UInt d = opnd->d; - UInt v = opnd->v; - UInt b = opnd->b; - - p = dvb_operand(p, d, v, b, 0 /* signed_displacement */); - break; - } - - case S390_OPND_DONE: // silence GCC - vassert(0); - break; - } - - if (write_separator) - *p++ = ','; - write_separator = 1; - } - - if (p[-1] == ',') // remove trailing separator, if any - *--p = '\0'; - - return p; -} - - -void -s390_disasm(const s390_opnd *opnds) -{ - HChar buf[128]; /* holds the disassembled insn */ - HChar *p = buf; - - if (opnds[0].kind == S390_OPND_MNM) { - p = s390_disasm_aux(opnds, NULL, p, NULL); - } else if (opnds[0].kind == S390_OPND_XMNM) { - p = opnds[0].xmnm.handler(opnds, p); - } else { - vassert(0); - } - *p = '\0'; - - vassert(p < buf + sizeof buf); /* detect buffer overwrite */ - - /* Finally, write out the disassembled insn */ - vex_printf("%s\n", buf); -} - -/*---------------------------------------------------------------*/ -/*--- end s390_disasm.c ---*/ -/*---------------------------------------------------------------*/ diff --git a/VEX/priv/s390_disasm.h b/VEX/priv/s390_disasm.h index d3096fd47..eec3dbca1 100644 --- a/VEX/priv/s390_disasm.h +++ b/VEX/priv/s390_disasm.h @@ -31,114 +31,7 @@ #include "libvex_basictypes.h" -/* The different kinds of operands in an asm insn */ -typedef enum { - S390_OPND_DONE, - S390_OPND_GPR, - S390_OPND_FPR, - S390_OPND_AR, - S390_OPND_VR, - S390_OPND_INT, - S390_OPND_UINT, - S390_OPND_PCREL, - S390_OPND_SDXB, - S390_OPND_UDXB, - S390_OPND_UDLB, - S390_OPND_UDVB, - S390_OPND_MNM, - S390_OPND_XMNM, - S390_OPND_MASK, // used for operands that modify the mnemonic -} opnd_t; - -typedef struct s390_opnd s390_opnd; - -struct s390_opnd { - opnd_t kind; // S390_OPND_.... - union { - const HChar *mnm; // MNM - UInt regno; // GPR, AR, FPR, VR - UInt mask; // MASK - Int pcrel; // PCREL - UInt u; // UINT - Int i; // INT - struct { // UDXB, SDXB, UDLB, UDVB - UInt d : 20; - union { - UInt x : 4; - UInt l : 8; - UInt v : 5; - }; - UInt b : 4; - }; - struct { - const HChar *base; - HChar *(*handler)(const s390_opnd *, HChar *); - } xmnm; - }; -}; - -/* Convenience macro to piece together a 20-bit displacement value. */ -#define D20(dh,dl) (((dh) << 12) | (dl)) - -/* Macros for operand construction */ -#define MNM(x) { S390_OPND_MNM, .mnm = (x) } -#define GPR(x) { S390_OPND_GPR, .regno = (x) } -#define FPR(x) { S390_OPND_FPR, .regno = (x) } -#define AR(x) { S390_OPND_AR, .regno = (x) } -#define VR(x) { S390_OPND_VR, .regno = (x) } -#define MASK(x) { S390_OPND_MASK, .mask = (x) } -#define UINT(x) { S390_OPND_UINT, .u = (x) } -#define INT(x) { S390_OPND_INT, .i = (x) } -#define PCREL(x) { S390_OPND_PCREL, .pcrel = (x) } -#define UDXB(_d,_x,_b) { S390_OPND_UDXB, .d = (_d), .x = (_x), .b = (_b) } -#define UDVB(_d,_v,_b) { S390_OPND_UDVB, .d = (_d), .v = (_v), .b = (_b) } -#define UDLB(_d,_l,_b) { S390_OPND_UDLB, .d = (_d), .l = (_l), .b = (_b) } -#define SDXB(dh,dl,_x,_b) \ - { S390_OPND_SDXB, .d = D20((dh), (dl)), .x = (_x), .b = (_b) } -#define XMNM(mnm,h) \ - { S390_OPND_XMNM, .xmnm.base = (mnm), .xmnm.handler = (h) } - -#define S390_DISASM(...) \ - s390_disasm((s390_opnd []){ __VA_ARGS__, { S390_OPND_DONE } }) - -void s390_disasm(const s390_opnd *); - -/* Handlers for extended mnemonics */ -HChar *bc_disasm(const s390_opnd *, HChar *); -HChar *bcr_disasm(const s390_opnd *, HChar *); -HChar *brc_disasm(const s390_opnd *, HChar *); -HChar *bic_disasm(const s390_opnd *, HChar *); -HChar *cls_disasm(const s390_opnd *, HChar *); -HChar *brcl_disasm(const s390_opnd *, HChar *); -HChar *cabt_disasm(const s390_opnd *, HChar *); -HChar *mask0_disasm(const s390_opnd *, HChar *); -HChar *vcdg_disasm(const s390_opnd *, HChar *); -HChar *vcgd_disasm(const s390_opnd *, HChar *); -HChar *vcgld_disasm(const s390_opnd *, HChar *); -HChar *vclgd_disasm(const s390_opnd *, HChar *); -HChar *vfi_disasm(const s390_opnd *, HChar *); -HChar *vfll_disasm(const s390_opnd *, HChar *); -HChar *vflr_disasm(const s390_opnd *, HChar *); -HChar *vfms_like_disasm(const s390_opnd *, HChar *); -HChar *vfpso_disasm(const s390_opnd *, HChar *); -HChar *vgbm_disasm(const s390_opnd *, HChar *); -HChar *vllez_disasm(const s390_opnd *, HChar *); -HChar *vllebrz_disasm(const s390_opnd *, HChar *); -HChar *vmsl_disasm(const s390_opnd *, HChar *); -HChar *vstebrf_disasm(const s390_opnd *, HChar *); -HChar *vstebrg_disasm(const s390_opnd *, HChar *); -HChar *vstrc_disasm(const s390_opnd *, HChar *); -HChar *va_like_disasm(const s390_opnd *, HChar *); -HChar *vch_like_disasm(const s390_opnd *, HChar *); -HChar *vfa_like_disasm(const s390_opnd *, HChar *); -HChar *wfc_like_disasm(const s390_opnd *, HChar *); -HChar *vfae_like_disasm(const s390_opnd *, HChar *); -HChar *vfce_like_disasm(const s390_opnd *, HChar *); -HChar *vfmix_like_disasm(const s390_opnd *, HChar *); -HChar *fp_convf_disasm(const s390_opnd *, HChar *); -HChar *fp_convt_disasm(const s390_opnd *, HChar *); -HChar *adtra_like_disasm(const s390_opnd *, HChar *); -HChar *rotate_disasm(const s390_opnd *, HChar *); +void s390_disasm(const UChar *); /*---------------------------------------------------------------*/ /*--- end s390_disasm.h ---*/