From: Pan Li Date: Sun, 21 Dec 2025 12:10:14 +0000 (+0800) Subject: RISC-V: Add test for vec_duplicate + vmsleu.vv combine with GR2VR cost 0, 1 and 15 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=3735bbb7d918e88cac9818b477121cf03558a7cc;p=thirdparty%2Fgcc.git RISC-V: Add test for vec_duplicate + vmsleu.vv combine with GR2VR cost 0, 1 and 15 Add asm dump check and run test for vec_duplicate + vmsleu.vv combine to vmsleu.vx, with the GR2VR cost is 0, 2 and 15. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c: Add asm check for vmsleu.vx. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c: Ditto. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h: Add test helper macros. * gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h: Add test data for run test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u16.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u32.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u64.c: New test. * gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u8.c: New test. Signed-off-by: Pan Li --- diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c index cce222672c4..36d8a6434ca 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u32.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c index 664d88da4e8..aab16016dd4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u64.c @@ -42,3 +42,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c index fd5ed561730..dcea470dc5f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-1-u8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-times {vmseq.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsne.vx} 1 } } */ /* { dg-final { scan-assembler-times {vmsltu.vx} 1 } } */ +/* { dg-final { scan-assembler-times {vmsleu.vx} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c index d3cdc4ab239..a3162b1626a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u16.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c index 10f5bf09b43..e90cdf652af 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u32.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c index a7c888848f6..79a2b3fb743 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u64.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c index 55c2a967611..989e1013890 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-2-u8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c index 233613df1b3..ae2216a75fe 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u16.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c index ac68d6e9ebb..348f33e9a79 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u32.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c index bfdf5c15124..85f9085ca62 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u64.c @@ -39,3 +39,4 @@ TEST_WIDEN_TERNARY_VX_UNSIGNED(T, NT) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c index d6e64ef6f92..82e5389f7d3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx-3-u8.c @@ -29,3 +29,4 @@ TEST_TERNARY_VX_UNSIGNED_0(T) /* { dg-final { scan-assembler-not {vmseq.vx} } } */ /* { dg-final { scan-assembler-not {vmsne.vx} } } */ /* { dg-final { scan-assembler-not {vmsltu.vx} } } */ +/* { dg-final { scan-assembler-not {vmsleu.vx} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h index a9bba40a55d..b1a678c130b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary.h @@ -426,6 +426,7 @@ DEF_AVG_CEIL(int32_t, int64_t) DEF_VX_BINARY_CASE_0_WRAP(T, ==, eq) \ DEF_VX_BINARY_CASE_0_WRAP(T, !=, ne) \ DEF_VX_BINARY_CASE_0_WRAP(T, <, ltu) \ + DEF_VX_BINARY_CASE_0_WRAP(T, <=, leu) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_0_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MAX_FUNC_1_WARP(T), max) \ DEF_VX_BINARY_CASE_2_WRAP(T, MIN_FUNC_0_WARP(T), min) \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h index fad479a260f..0cfb0fa5a2a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_binary_data.h @@ -6702,4 +6702,140 @@ int64_t TEST_BINARY_DATA(int64_t, lt)[][3][N] = }, }; +uint8_t TEST_BINARY_DATA(uint8_t, leu)[][3][N] = +{ + { + { 127 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 127, 127, 127, 127, + 128, 128, 128, 128, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 255 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 255, 255, 255, 255, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +uint16_t TEST_BINARY_DATA(uint16_t, leu)[][3][N] = +{ + { + { 32767 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 32767, 32767, 32767, 32767, + 32768, 32768, 32768, 32768, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 65535 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 65535, 65535, 65535, 65535, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +uint32_t TEST_BINARY_DATA(uint32_t, leu)[][3][N] = +{ + { + { 2147483647 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2147483647, 2147483647, 2147483647, 2147483647, + 2147483648, 2147483648, 2147483648, 2147483648, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 4294967295 }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 4294967295, 4294967295, 4294967295, 4294967295, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + +uint64_t TEST_BINARY_DATA(uint64_t, leu)[][3][N] = +{ + { + { 9223372036854775807ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, 9223372036854775807ull, + 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, 9223372036854775808ull, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 0, 0, 0, 0, + }, + }, + { + { 18446744073709551615ull }, + { + 0, 0, 0, 0, + 1, 1, 1, 1, + 2, 2, 2, 2, + 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, 18446744073709551615ull, + }, + { + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + 1, 1, 1, 1, + }, + }, +}; + #endif diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u16.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u16.c new file mode 100644 index 00000000000..a23cd92bc69 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u16.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint16_t +#define NAME leu + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u32.c new file mode 100644 index 00000000000..ed4bd59aa5c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u32.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint32_t +#define NAME leu + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u64.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u64.c new file mode 100644 index 00000000000..70a28114277 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u64.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint64_t +#define NAME leu + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u8.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u8.c new file mode 100644 index 00000000000..bf4dce6d433 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vx_vf/vx_vmsleu-run-1-u8.c @@ -0,0 +1,15 @@ +/* { dg-do run { target { riscv_v } } } */ +/* { dg-additional-options "-std=c99 --param=gpr2vr-cost=0" } */ + +#include "vx_binary.h" +#include "vx_binary_data.h" + +#define T uint8_t +#define NAME leu + +DEF_VX_BINARY_CASE_0_WRAP(T, <=, NAME) + +#define TEST_DATA TEST_BINARY_DATA_WRAP(T, NAME) +#define TEST_RUN(T, NAME, out, in, x, n) RUN_VX_BINARY_CASE_0_WRAP(T, NAME, out, in, x, n) + +#include "vx_binary_run.h"