From: Pan Li Date: Thu, 3 Aug 2023 01:30:24 +0000 (+0800) Subject: RISC-V: Support RVV VFMUL rounding mode intrinsic API X-Git-Tag: basepoints/gcc-15~7201 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=373600087df596b26c10d18eb0c5082c2788808b;p=thirdparty%2Fgcc.git RISC-V: Support RVV VFMUL rounding mode intrinsic API Update in v2: * Sync with upstream for the vfmul duplicated declaration. Original log: This patch would like to support the rounding mode API for the VFMUL for the below samples. * __riscv_vfmul_vv_f32m1_rm * __riscv_vfmul_vv_f32m1_rm_m * __riscv_vfmul_vf_f32m1_rm * __riscv_vfmul_vf_f32m1_rm_m Signed-off-by: Pan Li gcc/ChangeLog: * config/riscv/riscv-vector-builtins-bases.cc (vfmul_frm_obj): New declaration. (Base): Likewise. * config/riscv/riscv-vector-builtins-bases.h: Likewise. * config/riscv/riscv-vector-builtins-functions.def (vfmul_frm): New function definition. * config/riscv/vector.md: Add vfmul to frm_mode. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/float-point-single-mul.c: New test. --- diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc b/gcc/config/riscv/riscv-vector-builtins-bases.cc index ddf694c771c7..3adc11138a33 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc @@ -277,6 +277,7 @@ public: /* Implements below instructions for now. - vfadd + - vfmul */ template class binop_frm : public function_base @@ -2103,6 +2104,7 @@ static CONSTEXPR const widen_binop_frm vfwadd_frm_obj; static CONSTEXPR const widen_binop vfwsub_obj; static CONSTEXPR const widen_binop_frm vfwsub_frm_obj; static CONSTEXPR const binop vfmul_obj; +static CONSTEXPR const binop_frm vfmul_frm_obj; static CONSTEXPR const binop
vfdiv_obj; static CONSTEXPR const reverse_binop
vfrdiv_obj; static CONSTEXPR const widen_binop vfwmul_obj; @@ -2334,6 +2336,7 @@ BASE (vfwadd_frm) BASE (vfwsub) BASE (vfwsub_frm) BASE (vfmul) +BASE (vfmul_frm) BASE (vfdiv) BASE (vfrdiv) BASE (vfwmul) diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h b/gcc/config/riscv/riscv-vector-builtins-bases.h index f40b022239da..9c12a6b4e8f4 100644 --- a/gcc/config/riscv/riscv-vector-builtins-bases.h +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h @@ -152,6 +152,7 @@ extern const function_base *const vfwadd_frm; extern const function_base *const vfwsub; extern const function_base *const vfwsub_frm; extern const function_base *const vfmul; +extern const function_base *const vfmul_frm; extern const function_base *const vfdiv; extern const function_base *const vfrdiv; extern const function_base *const vfwmul; diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def b/gcc/config/riscv/riscv-vector-builtins-functions.def index 58a7224fe0c9..35a83ef239c2 100644 --- a/gcc/config/riscv/riscv-vector-builtins-functions.def +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def @@ -319,6 +319,8 @@ DEF_RVV_FUNCTION (vfmul, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvv_ops) DEF_RVV_FUNCTION (vfdiv, alu, full_preds, f_vvf_ops) DEF_RVV_FUNCTION (vfrdiv, alu, full_preds, f_vvf_ops) +DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvv_ops) +DEF_RVV_FUNCTION (vfmul_frm, alu_frm, full_preds, f_vvf_ops) // 13.5. Vector Widening Floating-Point Multiply DEF_RVV_FUNCTION (vfwmul, alu, full_preds, f_wvv_ops) diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 65f36744f549..5d3e4256cd58 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -866,7 +866,7 @@ ;; Defines rounding mode of an floating-point operation. (define_attr "frm_mode" "rne,rtz,rdn,rup,rmm,dyn,dyn_exit,dyn_call,none" - (cond [(eq_attr "type" "vfalu,vfwalu") + (cond [(eq_attr "type" "vfalu,vfwalu,vfmul") (cond [(match_test "INTVAL (operands[9]) == riscv_vector::FRM_RNE") (const_string "rne") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c new file mode 100644 index 000000000000..e6410ea3a37e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-single-mul.c @@ -0,0 +1,44 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */ + +#include "riscv_vector.h" + +typedef float float32_t; + +vfloat32m1_t +test_riscv_vfmul_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfmul_vv_f32m1_rm (op1, op2, 0, vl); +} + +vfloat32m1_t +test_vfmul_vv_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmul_vv_f32m1_rm_m (mask, op1, op2, 1, vl); +} + +vfloat32m1_t +test_vfmul_vf_f32m1_rm (vfloat32m1_t op1, float32_t op2, size_t vl) { + return __riscv_vfmul_vf_f32m1_rm (op1, op2, 2, vl); +} + +vfloat32m1_t +test_vfmul_vf_f32m1_rm_m (vbool32_t mask, vfloat32m1_t op1, float32_t op2, + size_t vl) { + return __riscv_vfmul_vf_f32m1_rm_m (mask, op1, op2, 3, vl); +} + +vfloat32m1_t +test_riscv_vfmul_vv_f32m1 (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) { + return __riscv_vfmul_vv_f32m1 (op1, op2, vl); +} + +vfloat32m1_t +test_vfmul_vv_f32m1_m (vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2, + size_t vl) { + return __riscv_vfmul_vv_f32m1_m (mask, op1, op2, vl); +} + +/* { dg-final { scan-assembler-times {vfmul\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 6 } } */ +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */