From: Srinath Parvathaneni Date: Mon, 5 Jan 2026 17:50:24 +0000 (+0000) Subject: aarch64: Add support for POE2 instructions X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=37fd5c94289d336a4a983f595b833caa97369f14;p=thirdparty%2Fbinutils-gdb.git aarch64: Add support for POE2 instructions This patch adds support for FEAT_S1POE2 feature enabled by "+poe2" flag along with support for following instructions. * TCHANGEB (immediate) * TCHANGEB (register) * TCHANGEF (immediate) * TCHANGEF (register) A new operand AARCH64_OPND_NOT_BALANCED_17 is added to the code in this patch to support the new optional argument "NB" (not_balanced) which is a 1-bit field in the encoding for all the above mentioned instructions. Co-authored-by: Matthew Malcomson --- diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 41ee673751a..97029ade890 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -6437,6 +6437,10 @@ process_omitted_operand (enum aarch64_opnd type, const aarch64_opcode *opcode, operand->hint_option = aarch64_hint_options + default_value; break; + case AARCH64_OPND_NOT_BALANCED_17: + operand->imm.value = default_value; + break; + default: break; } @@ -8184,6 +8188,24 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->barrier = aarch64_barrier_dsb_nxs_options + val; break; + case AARCH64_OPND_NOT_BALANCED_17: + { + char *p = str; + while (ISALPHA (*str)) + str++; + + if ((strncasecmp (p, "nb", 2) == 0) && (str == p + 2)) + info->imm.value = 1; + else + { + set_default_error (); + /* Turn off backtrack as this optional operand is present. */ + backtrack_pos = 0; + goto failure; + } + break; + } + case AARCH64_OPND_PRFOP: val = parse_pldop (&str); @@ -10829,6 +10851,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"sb", AARCH64_FEATURE (SB), AARCH64_NO_FEATURES}, {"predres", AARCH64_FEATURE (PREDRES), AARCH64_NO_FEATURES}, {"predres2", AARCH64_FEATURE (PREDRES2), AARCH64_FEATURE (PREDRES)}, + {"poe2", AARCH64_FEATURE (POE2), AARCH64_NO_FEATURES}, {"aes", AARCH64_FEATURE (AES), AARCH64_FEATURE (SIMD)}, {"sm4", AARCH64_FEATURE (SM4), AARCH64_FEATURE (SIMD)}, {"sha3", AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)}, diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index cc836a9566a..808acc6db57 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -275,6 +275,8 @@ automatically cause those extensions to be disabled. @tab Enable additional prediction restriction instructions. @item @code{profile} @tab @tab Enable statistical profiling extensions. +@item @code{poe2} @tab + @tab Enable Permission overlays extension 2. @item @code{ras} @tab @tab Enable the Reliability, Availability and Serviceability extension. @item @code{rasv2} @tab @code{ras} diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.d b/gas/testsuite/gas/aarch64/poe2-invalid-1.d new file mode 100644 index 00000000000..abd499e2f7c --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.d @@ -0,0 +1,4 @@ +#name: Invalid poe2 TIndex Change instructions. +#source: poe2-invalid-1.s +#as: -march=armv8-a+poe2 +#error_output: poe2-invalid-1.l diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.l b/gas/testsuite/gas/aarch64/poe2-invalid-1.l new file mode 100644 index 00000000000..06952fff0f7 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.l @@ -0,0 +1,55 @@ +.*: Assembler messages: +.*: Error: constant expression required at operand 2 -- `tchangef x0,x31' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,x3' +.*: Error: comma expected between operands at operand 2 -- `tchangef x7' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangef x15,x30,' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangef x30,x0,x10' +.*: Error: comma expected between operands at operand 2 -- `tchangef x10 x0' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef #1,#100' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef #10,x0' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangef x0,x1,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangef x1,x3 nb' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangef x3,x7,n' +.*: Error: unexpected characters following instruction at operand 3 -- `tchangef x7,x15,nb,nb' +.*: Error: constant expression required at operand 2 -- `tchangef x10,NB,NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,NB' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#128' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x1,#3111' +.*: Error: missing immediate expression at operand 2 -- `tchangef x3,#' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#15' +.*: Error: constant expression required at operand 2 -- `tchangef x10,nb,#127' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x0,#-10,nb' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangef x3,#777,nb' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangef x7,#15,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangef x15,#31 NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef x31,#63,nb' +.*: Error: expected an integer or zero register at operand 1 -- `tchangef NB,x10,#127' +.*: Error: constant expression required at operand 2 -- `tchangef x10,NB,#128' +.*: Error: constant expression required at operand 2 -- `tchangeb x0,x31' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,x3' +.*: Error: comma expected between operands at operand 2 -- `tchangeb x7' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangeb x15,x30,' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangeb x30,x0,x10' +.*: Error: comma expected between operands at operand 2 -- `tchangeb x10 x0' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb #1,#100' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb #10,x0' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangeb x0,x1,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangeb x1,x3 nb' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangeb x3,x7,n' +.*: Error: unexpected characters following instruction at operand 3 -- `tchangeb x7,x15,nb,nb' +.*: Error: constant expression required at operand 2 -- `tchangeb x10,NB,NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,NB' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#128' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x1,#3111' +.*: Error: missing immediate expression at operand 2 -- `tchangeb x3,#' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#15' +.*: Error: constant expression required at operand 2 -- `tchangeb x10,nb,#127' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x0,#-10,nb' +.*: Error: immediate value out of range 0 to 127 at operand 2 -- `tchangeb x3,#777,nb' +.*: Error: operand 3 must be an optional not balanced indicator \(NB\) -- `tchangeb x7,#15,nbb' +.*: Error: comma expected between operands at operand 3 -- `tchangeb x15,#31 NB' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb x31,#63,nb' +.*: Error: expected an integer or zero register at operand 1 -- `tchangeb NB,x10,#127' +.*: Error: constant expression required at operand 2 -- `tchangeb x10,NB,#128' diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-1.s b/gas/testsuite/gas/aarch64/poe2-invalid-1.s new file mode 100644 index 00000000000..7633e4d2dec --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-1.s @@ -0,0 +1,69 @@ +#TCHANGEF (register) instructions + tchangef x0, x31 + tchangef x31, x3 + tchangef x7 + tchangef x15, x30, + tchangef x30, x0, x10 + tchangef x10 x0 + tchangef #1, #100 + tchangef #10, x0 + +#TCHANGEF (register) instructions with not_balanced + tchangef x0, x1, nbb + tchangef x1, x3 nb + tchangef x3, x7, n + tchangef x7, x15, nb, nb + tchangef x10, NB, NB + tchangef NB, x10, NB + +#TCHANGEF (immediate) instructions + tchangef x0, #-10 + tchangef x0, #128 + tchangef x1, #3111 + tchangef x3, # + tchangef x31, #15 + tchangef x10, nb, #127 + +#TCHANGEF (immediate) instructions with not_balanced + tchangef x0, #-10, nb + tchangef x3, #777, nb + tchangef x7, #15, nbb + tchangef x15, #31 NB + tchangef x31, #63, nb + tchangef NB, x10, #127 + tchangef x10, NB, #128 + +#TCHANGEB (register) instructions + tchangeb x0, x31 + tchangeb x31, x3 + tchangeb x7 + tchangeb x15, x30, + tchangeb x30, x0, x10 + tchangeb x10 x0 + tchangeb #1, #100 + tchangeb #10, x0 + +#TCHANGEB (register) instructions with not_balanced + tchangeb x0, x1, nbb + tchangeb x1, x3 nb + tchangeb x3, x7, n + tchangeb x7, x15, nb, nb + tchangeb x10, NB, NB + tchangeb NB, x10, NB + +#TCHANGEB (immediate) instructions + tchangeb x0, #-10 + tchangeb x0, #128 + tchangeb x1, #3111 + tchangeb x3, # + tchangeb x31, #15 + tchangeb x10, nb, #127 + +#TCHANGEB (immediate) instructions with not_balanced + tchangeb x0, #-10, nb + tchangeb x3, #777, nb + tchangeb x7, #15, nbb + tchangeb x15, #31 NB + tchangeb x31, #63, nb + tchangeb NB, x10, #127 + tchangeb x10, NB, #128 diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-2.d b/gas/testsuite/gas/aarch64/poe2-invalid-2.d new file mode 100644 index 00000000000..3cb3b168fa5 --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-2.d @@ -0,0 +1,4 @@ +#name: TIndex Change instructions without +poe2 flag. +#source: poe2.s +#as: -march=armv8-a +#error_output: poe2-invalid-2.l diff --git a/gas/testsuite/gas/aarch64/poe2-invalid-2.l b/gas/testsuite/gas/aarch64/poe2-invalid-2.l new file mode 100644 index 00000000000..3a329016c8c --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2-invalid-2.l @@ -0,0 +1,29 @@ +.*: Assembler messages: +.*: Error: selected processor does not support `tchangef x0,x1' +.*: Error: selected processor does not support `tchangef xzr,x0' +.*: Error: selected processor does not support `tchangef x1,xzr' +.*: Error: selected processor does not support `tchangef x0,x1,nb' +.*: Error: selected processor does not support `tchangef xzr,x0,Nb' +.*: Error: selected processor does not support `tchangef x0,xzr,nB' +.*: Error: selected processor does not support `tchangef x0,x15,NB' +.*: Error: selected processor does not support `tchangef x0,#0' +.*: Error: selected processor does not support `tchangef xzr,#1' +.*: Error: selected processor does not support `tchangef x10,#127' +.*: Error: selected processor does not support `tchangef x0,#0,nb' +.*: Error: selected processor does not support `tchangef xzr,#1,NB' +.*: Error: selected processor does not support `tchangef x30,#63,nB' +.*: Error: selected processor does not support `tchangef x10,#127,Nb' +.*: Error: selected processor does not support `tchangeb x0,x1' +.*: Error: selected processor does not support `tchangeb xzr,x0' +.*: Error: selected processor does not support `tchangeb x0,xzr' +.*: Error: selected processor does not support `tchangeb x0,x1,nb' +.*: Error: selected processor does not support `tchangeb xzr,x0,Nb' +.*: Error: selected processor does not support `tchangeb x0,xzr,nB' +.*: Error: selected processor does not support `tchangeb x0,x15,NB' +.*: Error: selected processor does not support `tchangeb x0,#0' +.*: Error: selected processor does not support `tchangeb xzr,#1' +.*: Error: selected processor does not support `tchangeb x10,#127' +.*: Error: selected processor does not support `tchangeb x0,#0,nb' +.*: Error: selected processor does not support `tchangeb xzr,#1,NB' +.*: Error: selected processor does not support `tchangeb x30,#63,nB' +.*: Error: selected processor does not support `tchangeb x15,#127,Nb' diff --git a/gas/testsuite/gas/aarch64/poe2.d b/gas/testsuite/gas/aarch64/poe2.d new file mode 100644 index 00000000000..3b66742507a --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2.d @@ -0,0 +1,37 @@ +#objdump: -dr +#as: -march=armv8-a+poe2 + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d5800020 tchangef x0, x1 +.*: d580001f tchangef xzr, x0 +.*: d58003e1 tchangef x1, xzr +.*: d5820020 tchangef x0, x1, nb +.*: d582001f tchangef xzr, x0, nb +.*: d58203e0 tchangef x0, xzr, nb +.*: d58201e0 tchangef x0, x15, nb +.*: d5900000 tchangef x0, #0x0 +.*: d590003f tchangef xzr, #0x1 +.*: d5900fea tchangef x10, #0x7f +.*: d5920000 tchangef x0, #0x0, nb +.*: d592003f tchangef xzr, #0x1, nb +.*: d59207fe tchangef x30, #0x3f, nb +.*: d5920fea tchangef x10, #0x7f, nb +.*: d5840020 tchangeb x0, x1 +.*: d584001f tchangeb xzr, x0 +.*: d58403e0 tchangeb x0, xzr +.*: d5860020 tchangeb x0, x1, nb +.*: d586001f tchangeb xzr, x0, nb +.*: d58603e0 tchangeb x0, xzr, nb +.*: d58601e0 tchangeb x0, x15, nb +.*: d5940000 tchangeb x0, #0x0 +.*: d594003f tchangeb xzr, #0x1 +.*: d5940fea tchangeb x10, #0x7f +.*: d5960000 tchangeb x0, #0x0, nb +.*: d596003f tchangeb xzr, #0x1, nb +.*: d59607fe tchangeb x30, #0x3f, nb +.*: d5960fef tchangeb x15, #0x7f, nb diff --git a/gas/testsuite/gas/aarch64/poe2.s b/gas/testsuite/gas/aarch64/poe2.s new file mode 100644 index 00000000000..b32c66ec1ae --- /dev/null +++ b/gas/testsuite/gas/aarch64/poe2.s @@ -0,0 +1,43 @@ +#TCHANGEF (register) instructions + tchangef x0, x1 + tchangef xzr, x0 + tchangef x1, xzr + +#TCHANGEF (register) instructions with not_balanced + tchangef x0, x1, nb + tchangef xzr, x0, Nb + tchangef x0, xzr, nB + tchangef x0, x15, NB + +#TCHANGEF (immediate) instructions + tchangef x0, #0 + tchangef xzr, #1 + tchangef x10, #127 + +#TCHANGEF (immediate) instructions with not_balanced + tchangef x0, #0, nb + tchangef xzr, #1, NB + tchangef x30, #63, nB + tchangef x10, #127, Nb + +#TCHANGEB (register) instructions + tchangeb x0, x1 + tchangeb xzr, x0 + tchangeb x0, xzr + +#TCHANGEB (register) instructions with not_balanced + tchangeb x0, x1, nb + tchangeb xzr, x0, Nb + tchangeb x0, xzr, nB + tchangeb x0, x15, NB + +#TCHANGEB (immediate) instructions + tchangeb x0, #0 + tchangeb xzr, #1 + tchangeb x10, #127 + +#TCHANGEB (immediate) instructions with not_balanced + tchangeb x0, #0, nb + tchangeb xzr, #1, NB + tchangeb x30, #63, nB + tchangeb x15, #127, Nb diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index e3f75de98ff..7797b1812a4 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -279,6 +279,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_F16MM, /* SVE B16MM instructions. */ AARCH64_FEATURE_SVE_B16MM, + /* POE2 instructions. */ + AARCH64_FEATURE_POE2, /* Virtual features. These are used to gate instructions that are enabled by either of two (or more) sets of command line flags. */ @@ -691,6 +693,7 @@ enum aarch64_opnd AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */ AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */ AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */ + AARCH64_OPND_NOT_BALANCED_17, /* an optional not balanced indicator (NB). */ AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for each condition flag. */ diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c index d1b5a5b94ab..8d0a963513b 100644 --- a/opcodes/aarch64-asm-2.c +++ b/opcodes/aarch64-asm-2.c @@ -930,6 +930,7 @@ aarch64_insert_operand (const aarch64_operand *self, case AARCH64_OPND_UNDEFINED: case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: + case AARCH64_OPND_NOT_BALANCED_17: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_PCREL9: case AARCH64_OPND_ADDR_PCREL14: diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c index ac3aa499066..d4c95d4b81e 100644 --- a/opcodes/aarch64-dis-2.c +++ b/opcodes/aarch64-dis-2.c @@ -26871,28 +26871,68 @@ aarch64_opcode_lookup_1 (uint32_t word) { if (((word >> 22) & 0x1) == 0) { - if (((word >> 25) & 0x1) == 0) + if (((word >> 23) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1010101x00xxxxxxxxxxxxxxxxxxxxx. */ - return A64_OPID_d500403f_xaflag; + if (((word >> 25) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010101000xxxxxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d500403f_xaflag; + } + else + { + if (((word >> 10) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010111000xxxxxxxxxx0xxxxxxxxxx. */ + return A64_OPID_d71f0800_braa_Rn_Rd_SP; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x1010111000xxxxxxxxxx1xxxxxxxxxx. */ + return A64_OPID_d71f0c00_brab_Rn_Rd_SP; + } + } } else { - if (((word >> 10) & 0x1) == 0) + if (((word >> 18) & 0x1) == 0) { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1010111x00xxxxxxxxxx0xxxxxxxxxx. */ - return A64_OPID_d71f0800_braa_Rn_Rd_SP; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11000x0xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5800000_tchangef_Rd_Rn_NOT_BALANCED_17; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11001x0xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED_17; + } } else { - /* 33222222222211111111110000000000 - 10987654321098765432109876543210 - x1010111x00xxxxxxxxxx1xxxxxxxxxx. */ - return A64_OPID_d71f0c00_brab_Rn_Rd_SP; + if (((word >> 20) & 0x1) == 0) + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11000x1xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED_17; + } + else + { + /* 33222222222211111111110000000000 + 10987654321098765432109876543210 + x10101x11001x1xxxxxxxxxxxxxxxxxx. */ + return A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED_17; + } } } } @@ -37847,6 +37887,7 @@ aarch64_extract_operand (const aarch64_operand *self, case AARCH64_OPND_UNDEFINED: case AARCH64_OPND_CCMP_IMM: case AARCH64_OPND_SIMM5: + case AARCH64_OPND_NOT_BALANCED_17: case AARCH64_OPND_NZCV: case AARCH64_OPND_ADDR_ADRP: case AARCH64_OPND_ADDR_PCREL9: diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index 6000ed8bfef..7619723aae1 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -104,6 +104,7 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_IMMEDIATE, "UNDEFINED", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16_0}, "a 16-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "CCMP_IMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit unsigned immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "SIMM5", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm5}, "a 5-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "NOT_BALANCED_17", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm17_1}, "an optional not balanced indicator (NB)"}, {AARCH64_OPND_CLASS_IMMEDIATE, "NZCV", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_nzcv}, "a flag bit specifier giving an alternative value for each flag"}, {AARCH64_OPND_CLASS_IMMEDIATE, "LIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_N,FLD_immr,FLD_imms}, "Logical immediate"}, {AARCH64_OPND_CLASS_IMMEDIATE, "AIMM", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_shift,FLD_imm12}, "a 12-bit unsigned immediate with optional left shift of 12 bits"}, diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 0b78e5243d6..6b3ecf2e138 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -5162,6 +5162,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "%s", style_sub_mnem (styler, "dsync")); break; + case AARCH64_OPND_NOT_BALANCED_17: + if (opnd->imm.value) + snprintf (buf, size, "%s", style_sub_mnem (styler, "nb")); + break; + case AARCH64_OPND_BTI_TARGET: snprintf (buf, size, "%s", style_sub_mnem (styler, opnd->hint_option->name)); diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h index 734dd2f5cb2..8fcf7feb978 100644 --- a/opcodes/aarch64-tbl-2.h +++ b/opcodes/aarch64-tbl-2.h @@ -4044,5 +4044,9 @@ enum aarch64_opcode_idx A64_OPID_4ec0ec00_fmmla_Vd_Vn_Vm, A64_OPID_64a0e000_fmmla_SVE_Zd_SVE_Zn_SVE_Zm_16, A64_OPID_64e0e000_bfmmla_SVE_Zd_SVE_Zn_SVE_Zm_16, + A64_OPID_d5800000_tchangef_Rd_Rn_NOT_BALANCED_17, + A64_OPID_d5900000_tchangef_Rd_UIMM7_NOT_BALANCED_17, + A64_OPID_d5840000_tchangeb_Rd_Rn_NOT_BALANCED_17, + A64_OPID_d5940000_tchangeb_Rd_UIMM7_NOT_BALANCED_17, A64_OPID_MAX, }; diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3796a476880..613300a75b1 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -1235,6 +1235,12 @@ QLF2(X, NIL), \ } +/* e.g. TCHANGEF , #{, }. */ +#define QL_X1NIL2 \ +{ \ + QLF3(X,NIL,NIL), \ +} + /* e.g. LDXP , , [{,#0}]. */ #define QL_R2NIL \ { \ @@ -3092,6 +3098,8 @@ static const aarch64_feature_set aarch64_feature_f16mm_sve2p2 = AARCH64_FEATURES (2, F16MM, SVE2p2); static const aarch64_feature_set aarch64_feature_sve_b16mm = AARCH64_FEATURE (SVE_B16MM); +static const aarch64_feature_set aarch64_feature_POE2 = + AARCH64_FEATURE (POE2); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -3226,6 +3234,7 @@ static const aarch64_feature_set aarch64_feature_sve_b16mm = #define F16MM &aarch64_feature_f16mm #define F16MM_SVE2p2 &aarch64_feature_f16mm_sve2p2 #define SVE_B16MM &aarch64_feature_sve_b16mm +#define POE2 &aarch64_feature_POE2 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } @@ -3580,6 +3589,8 @@ static const aarch64_feature_set aarch64_feature_sve_b16mm = { NAME, OPCODE, MASK, CLASS, 0, F16MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } #define SVE_B16MM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, SVE_B16MM, OPS, QUALS, FLAGS | F_STRICT, 0, 0, NULL } +#define POE2_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS, FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, POE2, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -7886,6 +7897,12 @@ const struct aarch64_opcode aarch64_opcode_table[] = /* SVE B16MM instructions. */ SVE_B16MM_INSN("bfmmla", 0x64e0e000, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_HHH, 0), + /* POE2 instructions. */ + POE2_INSN("tchangef", 0xd5800000, 0xfffdfc00, aarch64_misc, OP3 (Rd, Rn, NOT_BALANCED_17), QL_X2NIL, F_OPD2_OPT | F_DEFAULT (0x0)), + POE2_INSN("tchangef", 0xd5900000, 0xfffdf000, aarch64_misc, OP3 (Rd, UIMM7, NOT_BALANCED_17), QL_X1NIL2, F_OPD2_OPT | F_DEFAULT (0x0)), + POE2_INSN("tchangeb", 0xd5840000, 0xfffdfc00, aarch64_misc, OP3 (Rd, Rn, NOT_BALANCED_17), QL_X2NIL, F_OPD2_OPT | F_DEFAULT (0x0)), + POE2_INSN("tchangeb", 0xd5940000, 0xfffdf000, aarch64_misc, OP3 (Rd, UIMM7, NOT_BALANCED_17), QL_X1NIL2, F_OPD2_OPT | F_DEFAULT (0x0)), + {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -8038,6 +8055,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a 5-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ "a 5-bit signed immediate") \ + Y(IMMEDIATE, imm, "NOT_BALANCED_17", 0, F(FLD_imm17_1), \ + "an optional not balanced indicator (NB)") \ Y(IMMEDIATE, imm, "NZCV", 0, F(FLD_nzcv), \ "a flag bit specifier giving an alternative value for each flag") \ Y(IMMEDIATE, limm, "LIMM", 0, F(FLD_N,FLD_immr,FLD_imms), \