From: Daniel Golle Date: Fri, 17 Nov 2023 02:25:09 +0000 (+0000) Subject: mediatek: add support for Adtran SmartRG Bonanza Peak series X-Git-Tag: v23.05.4~94 X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=387e143c682381cad9a2694c42822456f36b0fa4;p=thirdparty%2Fopenwrt.git mediatek: add support for Adtran SmartRG Bonanza Peak series The Bonanza Peak series are a couple of MT7986-powered 2.5 GBit/s Wi-Fi 6 residential gateway, access point and mesh router products. All of them come with an eMMC to boot from, are powered via USB-C and got a USB 3.0 type-A port. All of them got a Dialog (Renesas) DA14531 Bluetooth module connected via UART. If the device was previously running stock firmware, the BT chip's internal flash has been loaded with firmware and it can be attached using hciattach when using OpenWrt. SOC: MediaTek MT7986A RAM: 2 GiB DDR4 eMMC: 8 GiB Bluetooth: BLE5 (DA14531) Serial: 3.3V level, 115200 8n1 on 4-pin connector * SDG-8612 - Dual-band RJ-45 gateway 2x 2.5G MaxLinear PHY for WAN port 3x 1GE LAN ports via MT7531 switch * SDG-8614 - Dual-band SFP gateway 1x SFP cage with up to 2.5G speed 1x 2.5G MaxLinear PHY for LAN port 3x 1GE LAN ports via MT7531 switch * SDG-8622 - Tri-band mesh router 2x 2.5G MaxLinear PHY The MT7986 2G and 5G are used as 2G and 5G high band. There’s a MT7915 PCIe card for 5G low band. * SDG-8632 - Tri-band mesh router with 6 GHz 2x 2.5G MaxLinear PHY The MT7986 serves the 2G and 6G bands. There’s a MT7915 PCIe card for 5G. Installation via U-Boot serial console: 0. setup TFTP server with IP 192.168.1.10/24, place initramfs image renamed to openwrt.XXX where XXX is the internal product number: SDG-8612: XXX = 412 SDG-8614: XXX = 414 SDG-8622: XXX = 422 SDG-8632: XXX = 432 1. connect to the serial console and power on the device. Interrupt the bootloader by pressing 'st' 2. setenv boot_mode openwrt ; saveenv 3. run boot1 Load firmware via TFTP and write to flash 4. run boot2 Now OpenWrt initramfs should boot 5. upload sysupgrade.bin via scp to /tmp 6. sysupgrade Signed-off-by: Daniel Golle (cherry picked from commit 3aa686f8d4d89ab28e749874c4b5e82d46685f3c) --- diff --git a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface index bd0ed335823..8fe5c805522 100644 --- a/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface +++ b/target/linux/mediatek/base-files/lib/preinit/05_set_preinit_iface @@ -11,6 +11,11 @@ set_preinit_iface() { ip link set eth0 up ifname=eth0 ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632) + ip link set lan up + ifname=lan + ;; xiaomi,mi-router-ax3000t|\ xiaomi,mi-router-ax3000t-ubootmod|\ xiaomi,mi-router-wr30u-stock|\ diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts new file mode 100644 index 00000000000..1537fc2c1a4 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8612.dts @@ -0,0 +1,76 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8612"; + compatible = "smartrg,sdg-8612", "mediatek,mt7986a"; +}; + +&gmac0 { + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&gmac1 { + phy-handle = <&phy6>; +}; + +&mdio { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts new file mode 100644 index 00000000000..15cfb1f125e --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8614.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8614"; + compatible = "smartrg,sdg-8614", "mediatek,mt7986a"; + + /* SFP1 cage (WAN) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 62 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 63 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 65 GPIO_ACTIVE_LOW>; + rate-select0-gpios = <&pio 9 GPIO_ACTIVE_HIGH>; + rate-select1-gpios = <&pio 28 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&pio 64 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + maximum-power-milliwatt = <3000>; + }; + + leds { + compatible = "gpio-leds"; + + sfp_red { + color = ; + function = "sfp"; + function-enumerator = <1>; + gpios = <&pio 16 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + sfp_green { + color = ; + function = "sfp"; + function-enumerator = <0>; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; +}; + +&mux_sel { + output-low; + /delete-node/ output-high; +}; + +&gmac0 { + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; +}; + +&gmac1 { + sfp = <&sfp1>; + managed = "in-band-status"; +}; + +&mdio { + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + + port@3 { + reg = <3>; + label = "lan1"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + + phy-mode = "2500base-x"; + phy-handle = <&phy5>; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5170000 5835000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts new file mode 100644 index 00000000000..2c28c8f7b47 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8622.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8622"; + compatible = "smartrg,sdg-8622", "mediatek,mt7986a"; +}; + +&gmac0 { + phy-handle = <&phy5>; + + label = "lan"; +}; + +&gmac1 { + phy-handle = <&phy6>; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&radio0 { + ieee80211-freq-limit = <5170000 5330000>; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5490000 5835000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts new file mode 100644 index 00000000000..bc92f85aa09 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-SDG-8632.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +#include "mt7986a-smartrg-bonanza-peak.dtsi" + +/ { + model = "SmartRG SDG-8632"; + compatible = "smartrg,sdg-8632", "mediatek,mt7986a"; +}; + +&gmac0 { + phy-handle = <&phy5>; + + label = "lan"; +}; + +&gmac1 { + phy-handle = <&phy6>; +}; + +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&radio0 { + ieee80211-freq-limit = <5170000 5835000>; +}; + +&wifi { + ieee80211-freq-limit = <2400000 2500000>, <5945000 7125000>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi new file mode 100644 index 00000000000..038a76ad73c --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-smartrg-bonanza-peak.dtsi @@ -0,0 +1,481 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 SmartRG Inc. + * Author: Chad Monroe + */ + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_white; + led-upgrade = &led_status_blue; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs = "root=/dev/mmcblk0p5"; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0x40000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /delete-node/ramoops@42ff0000; + + bootdata_reserved: bootdata@45000000 { + no-map; + reg = <0x0 0x45000000 0x0 0x00001000>; + }; + + ramoops_reserved: ramoops@45001000 { + no-map; + compatible = "ramoops"; + reg = <0x0 0x45001000 0x0 0x00140000>; + ftrace-size = <0x20000>; + record-size = <0x20000>; + console-size = <0x20000>; + pmsg-size = <0x80000>; + }; + }; + + bootdata { + compatible = "bootdata"; + memory-region = <&bootdata_reserved>; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + pwms = <&pwm 1 40000 0>; + + /** + * set fan speed + * + * 0 = off + * 51 = 20% duty cycle (minimum supported) + * 61 = 24% duty cycle (2020 RPM) + * 77 = 30% duty cycle (3000 RPM) + * 102 = 40% duty cycle (3600 RPM) + * 255 = 100% duty cycle + */ + cooling-levels = <51 61 77 102>; + + interrupt-parent = <&pio>; + interrupts = <25 IRQ_TYPE_EDGE_FALLING>; + pulses-per-revolution = <2>; + + status = "okay"; + }; + + keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&button_pins>; + + button-reset { + label = "reset"; + linux,code = ; + gpios = <&pio 17 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&cpu_thermal { + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 3 */ + cooling-device = <&fan 3 3>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-medium { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_medium>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-active-silent { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_active_silent>; + }; + }; + + trips { + cpu_trip_active_high: active-high { + temperature = <110000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_medium: active-medium { + temperature = <80000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_silent: active-silent { + temperature = <40000>; + hysteresis = <2000>; + type = "active"; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + + phy-mode = "2500base-x"; + }; + + gmac1: mac@1 { + label = "wan"; + + compatible = "mediatek,eth-mac"; + reg = <1>; + + phy-mode = "2500base-x"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + #address-cells = <1>; + #size-cells = <0>; + + reset-gpios = <&pio 6 GPIO_ACTIVE_LOW>; + reset-delay-us = <1500000>; + reset-post-delay-us = <1000000>; + + phy5: ethernet-phy@5 { + /* GPY211 */ + compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45"; + reg = <5>; + + mxl,led-drive-vdd; + mxl,led-config = <0x30 0x40 0x80 0x0>; + }; + + phy6: ethernet-phy@6 { + /* GPY211 */ + compatible = "maxlinear,gpy211", "ethernet-phy-ieee802.3-c45"; + reg = <6>; + + mxl,led-drive-vdd; + mxl,led-config = <0x30 0x40 0x80 0x0>; + }; +}; + +&crypto { + status = "okay"; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "disabled"; + + slot0: pcie@0,0 { + reg = <0x0000 0 0 0 0>; + + radio0: mt7915@0,0 { + reg = <0x0000 0 0 0 0>; + }; + }; +}; + +&pcie_phy { + status = "disabled"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; + +&pio { + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + mediatek,pull-down-adv = <2>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + mediatek,pull-up-adv = <1>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_pereset"; + }; + }; + + button_pins: button-pins { + pins = "GPIO_12"; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_2_rx_tx", "uart1_2_cts_rts"; + }; + }; + + i2c0_pins: i2c0-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + mux_sel: mux-sel-hog { + gpio-hog; + gpios = <23 GPIO_ACTIVE_LOW>; + line-name = "mux-sel"; + output-high; + }; + + mux_oe: mux-oe-hog { + gpio-hog; + gpios = <24 GPIO_ACTIVE_LOW>; + line-name = "mux-oe"; + output-high; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; + + /* DA14531MOD Bluetooth */ + bluetooth { + compatible = "renesas,DA14531"; + reset-gpios = <&pio 27 GPIO_ACTIVE_LOW>; + }; +}; + +&usb_phy { + status = "okay"; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + status = "okay"; + + system-leds { + compatible = "srg,sysled"; + reg = <0x30>; + + led_status_red: led@1 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <1>; + }; + + led_status_green: led@2 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <2>; + }; + + led_status_blue: led@3 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <3>; + }; + + led_status_white: led@4 { + color = ; + function = LED_FUNCTION_STATUS; + reg = <4>; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&watchdog { + interrupts = ; + status = "okay"; +}; diff --git a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network index 4a00b27927f..a8ec200afc2 100644 --- a/target/linux/mediatek/filogic/base-files/etc/board.d/02_network +++ b/target/linux/mediatek/filogic/base-files/etc/board.d/02_network @@ -67,6 +67,10 @@ mediatek_setup_interfaces() zyxel,nwa50ax-pro) ucidef_set_interface_lan "eth0" ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632) + ucidef_set_interfaces_lan_wan lan wan + ;; tplink,tl-xdr6086) ucidef_set_interfaces_lan_wan "lan1 lan2" eth1 ;; @@ -144,6 +148,14 @@ mediatek_setup_macs() wan_mac=$(macaddr_add "$lan_mac" 1) label_mac=$wan_mac ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632) + label_mac=$(mmc_get_mac_ascii mfginfo MFG_MAC) + wan_mac=$label_mac + lan_mac=$(macaddr_add "$label_mac" 1) + ;; xiaomi,mi-router-ax3000t|\ xiaomi,mi-router-ax3000t-ubootmod|\ xiaomi,mi-router-wr30u-stock|\ diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata index bff3be2a9ba..cbbf1871a5d 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/firmware/11-mt76-caldata @@ -7,10 +7,18 @@ board=$(board_name) case "$FIRMWARE" in +"mediatek/mt7915_eeprom.bin") + case "$board" in + smartrg,sdg-8622) + caldata_extract_mmc "factory" 0xa0000 0x1000 + ;; + esac + ;; "mediatek/mt7916_eeprom.bin") case "$board" in - acer,predator-w6) - caldata_extract_mmc "factory" 0xA0000 0x1000 + acer,predator-w6|\ + smartrg,sdg-8632) + caldata_extract_mmc "factory" 0xa0000 0x1000 ;; esac ;; @@ -34,6 +42,12 @@ case "$FIRMWARE" in ln -sf /tmp/tp_data/MT7986_EEPROM.bin \ /lib/firmware/$FIRMWARE ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632) + caldata_extract_mmc "factory" 0x0 0x1000 + ;; esac ;; "mediatek/mt7986_eeprom_mt7976.bin") diff --git a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac index 2d9f9d73d32..745efd84382 100644 --- a/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac +++ b/target/linux/mediatek/filogic/base-files/etc/hotplug.d/ieee80211/11_fix_wifi_mac @@ -101,6 +101,15 @@ case "$board" in [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + [ "$PHYNBR" = "0" ] && macaddr_add $addr 2 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "1" ] && macaddr_add $addr 3 > /sys${DEVPATH}/macaddress + [ "$PHYNBR" = "2" ] && macaddr_add $addr 4 > /sys${DEVPATH}/macaddress + ;; tplink,tl-xdr4288|\ tplink,tl-xdr6086|\ tplink,tl-xdr6088) diff --git a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh index d770b136432..37b5be13343 100644 --- a/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh +++ b/target/linux/mediatek/filogic/base-files/lib/preinit/10_fix_eth_mac.sh @@ -21,6 +21,23 @@ preinit_set_mac_address() { addr=$(get_mac_binary "/tmp/tp_data/default-mac" 0) ip link set dev eth1 address "$(macaddr_add $addr 1)" ;; + smartrg,sdg-8612|\ + smartrg,sdg-8614) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + lan_addr=$(macaddr_add $addr 1) + ip link set dev wan address "$addr" + ip link set dev eth0 address "$lan_addr" + ip link set dev lan1 address "$lan_addr" + ip link set dev lan2 address "$lan_addr" + ip link set dev lan3 address "$lan_addr" + ip link set dev lan4 address "$lan_addr" + ;; + smartrg,sdg-8622|\ + smartrg,sdg-8632) + addr=$(mmc_get_mac_ascii mfginfo MFG_MAC) + ip link set dev wan address "$addr" + ip link set dev lan address "$(macaddr_add $addr 1)" + ;; *) ;; esac diff --git a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh index 693d5753a5e..b92c0fc863e 100755 --- a/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh +++ b/target/linux/mediatek/filogic/base-files/lib/upgrade/platform.sh @@ -63,7 +63,11 @@ platform_do_upgrade() { local board=$(board_name) case "$board" in - acer,predator-w6) + acer,predator-w6|\ + smartrg,sdg-8612|\ + smartrg,sdg-8614|\ + smartrg,sdg-8622|\ + smartrg,sdg-8632) CI_KERNPART="kernel" CI_ROOTPART="rootfs" emmc_do_upgrade "$1" diff --git a/target/linux/mediatek/image/filogic.mk b/target/linux/mediatek/image/filogic.mk index 5caac353ec1..1a714a44e6c 100644 --- a/target/linux/mediatek/image/filogic.mk +++ b/target/linux/mediatek/image/filogic.mk @@ -137,6 +137,44 @@ define Device/acer_predator-w6 endef TARGET_DEVICES += acer_predator-w6 +define Device/adtran_smartrg + DEVICE_VENDOR := Adtran + DEVICE_DTS_DIR := ../dts + DEVICE_PACKAGES := e2fsprogs f2fsck mkf2fs kmod-hwmon-pwmfan \ + kmod-mt7986-firmware mt7986-wo-firmware + IMAGE/sysupgrade.bin := sysupgrade-tar | append-metadata +endef + +define Device/smartrg_sdg-8612 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8612 + DEVICE_DTS := mt7986a-smartrg-SDG-8612 +endef +TARGET_DEVICES += smartrg_sdg-8612 + +define Device/smartrg_sdg-8614 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8614 + DEVICE_DTS := mt7986a-smartrg-SDG-8614 +endef +TARGET_DEVICES += smartrg_sdg-8614 + +define Device/smartrg_sdg-8622 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8622 + DEVICE_DTS := mt7986a-smartrg-SDG-8622 + DEVICE_PACKAGES += kmod-mt7915-firmware +endef +TARGET_DEVICES += smartrg_sdg-8622 + +define Device/smartrg_sdg-8632 +$(call Device/adtran_smartrg) + DEVICE_MODEL := SDG-8632 + DEVICE_DTS := mt7986a-smartrg-SDG-8632 + DEVICE_PACKAGES += kmod-mt7915-firmware +endef +TARGET_DEVICES += smartrg_sdg-8632 + define Device/asus_rt-ax59u DEVICE_VENDOR := ASUS DEVICE_MODEL := RT-AX59U