From: Jonas Jelonek Date: Tue, 13 Jan 2026 10:57:21 +0000 (+0000) Subject: realtek: pcs: rtl930x: add standalone XSGMII setup X-Git-Url: http://git.ipfire.org/cgi-bin/gitweb.cgi?a=commitdiff_plain;h=38803fc11000f083e8db8b91b6a4834646a0ba9b;p=thirdparty%2Fopenwrt.git realtek: pcs: rtl930x: add standalone XSGMII setup Add everything that's needed to have a standalone setup of the XSGMII mode without having to rely on previous U-boot setup. This includes patch sequences for the SerDes and extensions of symbol error reset and reading. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/21762 Signed-off-by: Hauke Mehrtens --- diff --git a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c index a9c84b46879..5065e4ee393 100644 --- a/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.12/drivers/net/pcs/pcs-rtl-otto.c @@ -2353,21 +2353,26 @@ static int rtpcs_930x_sds_sym_err_reset(struct rtpcs_serdes *sds, channels = 1; } - /* TODO: Below reset sequence must run with new xsg_write() function */ - if (hw_mode == RTPCS_SDS_MODE_XSGMII) { - pr_info("%s unsupported PHY-mode\n", __func__); - return -1; - } - for (channel = 0; channel < channels; channel++) { - rtpcs_sds_write_bits(sds, 0x1, 24, 2, 0, channel); - rtpcs_sds_write_bits(sds, 0x1, 3, 15, 8, 0); - rtpcs_sds_write_bits(sds, 0x1, 2, 15, 0, 0); + if (hw_mode == RTPCS_SDS_MODE_XSGMII) { + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x18, 2, 0, channel); + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x3, 15, 8, 0x0); + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x2, 15, 0, 0x0); + } else { + rtpcs_sds_write_bits(sds, 0x1, 0x18, 2, 0, channel); + rtpcs_sds_write_bits(sds, 0x1, 0x3, 15, 8, 0x0); + rtpcs_sds_write_bits(sds, 0x1, 0x2, 15, 0, 0x0); + } } if (channels > 1) { - rtpcs_sds_write_bits(sds, 0x1, 0, 15, 0, 0); - rtpcs_sds_write_bits(sds, 0x1, 1, 15, 8, 0); + if (hw_mode == RTPCS_SDS_MODE_XSGMII) { + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x0, 15, 0, 0x0); + rtpcs_sds_xsg_write_bits(sds, 0x1, 0x1, 15, 8, 0x0); + } else { + rtpcs_sds_write_bits(sds, 0x1, 0x0, 15, 0, 0x0); + rtpcs_sds_write_bits(sds, 0x1, 0x1, 15, 8, 0x0); + } } return 0; @@ -2380,6 +2385,10 @@ static u32 rtpcs_930x_sds_sym_err_get(struct rtpcs_serdes *sds, switch (hw_mode) { case RTPCS_SDS_MODE_XSGMII: + v = rtpcs_sds_read_bits(sds, 0x1, 0x1, 15, 8) << 16; + v |= rtpcs_sds_read_bits(sds, 0x1, 0x0, 15, 0); + break; + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: break; @@ -2637,6 +2646,39 @@ static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_10g_2500bx_odd[] = { {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808}, }; +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_xsgmii_even[] = +{ + {0x00, 0x0E, 0x3053}, + {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, + {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, + {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, + {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0484}, {0x2E, 0x13, 0x027F}, + {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, + {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1017}, {0x2F, 0x03, 0xFFDF}, {0x2F, 0x05, 0x7F7C}, + {0x2F, 0x07, 0x8104}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4}, {0x2F, 0x0A, 0x7C2F}, + {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020}, {0x2F, 0x11, 0x8840}, + {0x2B, 0x13, 0x0050}, {0x2B, 0x18, 0x8E88}, {0x2B, 0x19, 0x4902}, {0x2B, 0x1D, 0x2501}, + {0x2D, 0x13, 0x0050}, {0x2D, 0x18, 0x8E88}, {0x2D, 0x19, 0x4902}, {0x2D, 0x1D, 0x2641}, + {0x2F, 0x13, 0x0050}, {0x2F, 0x18, 0x8E88}, {0x2F, 0x19, 0x4902}, {0x2F, 0x1D, 0x66E1}, +}; + +static const struct rtpcs_sds_config rtpcs_930x_sds_cfg_xsgmii_odd[] = +{ + {0x00, 0x0E, 0x3053}, + {0x21, 0x03, 0x8206}, {0x21, 0x05, 0x40B0}, {0x21, 0x06, 0x0010}, {0x21, 0x07, 0xF09F}, + {0x21, 0x0A, 0x0003}, {0x21, 0x0B, 0x0005}, {0x21, 0x0C, 0x0007}, {0x21, 0x0D, 0x6009}, + {0x21, 0x0E, 0x0000}, {0x21, 0x0F, 0x0008}, + {0x2E, 0x00, 0xA668}, {0x2E, 0x02, 0xD020}, {0x2E, 0x06, 0xC000}, {0x2E, 0x0B, 0x1892}, + {0x2E, 0x0F, 0xFFDF}, {0x2E, 0x11, 0x8280}, {0x2E, 0x12, 0x0484}, {0x2E, 0x13, 0x027F}, + {0x2E, 0x14, 0x1311}, {0x2E, 0x17, 0xA100}, {0x2E, 0x1A, 0x0001}, {0x2E, 0x1C, 0x0400}, + {0x2F, 0x00, 0x820F}, {0x2F, 0x01, 0x0300}, {0x2F, 0x02, 0x1017}, {0x2F, 0x03, 0xFFDF}, + {0x2F, 0x05, 0x7F7C}, {0x2F, 0x07, 0x8104}, {0x2F, 0x08, 0x0001}, {0x2F, 0x09, 0xFFD4}, + {0x2F, 0x0A, 0x7C2F}, {0x2F, 0x0E, 0x003F}, {0x2F, 0x0F, 0x0121}, {0x2F, 0x10, 0x0020}, + {0x2F, 0x11, 0x8840}, + {0x2B, 0x13, 0x3D87}, {0x2B, 0x14, 0x3108}, + {0x2D, 0x13, 0x3C87}, {0x2D, 0x14, 0x1808}, +}; + static void rtpcs_930x_sds_usxgmii_config(struct rtpcs_serdes *sds, int nway_en, u32 opcode, u32 am_period, u32 all_am_markers, u32 an_table, @@ -2697,6 +2739,21 @@ static void rtpcs_930x_sds_patch(struct rtpcs_serdes *sds, } break; + case RTPCS_SDS_MODE_XSGMII: + if (is_even_sds) { + config = rtpcs_930x_sds_cfg_xsgmii_even; + count = ARRAY_SIZE(rtpcs_930x_sds_cfg_xsgmii_even); + } else { + config = rtpcs_930x_sds_cfg_xsgmii_odd; + count = ARRAY_SIZE(rtpcs_930x_sds_cfg_xsgmii_odd); + } + + /* this needs XSG write */ + for (size_t i = 0; i < count; i++) + rtpcs_sds_xsg_write(sds, config[i].page, config[i].reg, config[i].data); + + return; + case RTPCS_SDS_MODE_USXGMII_10GQXGMII: default: return; @@ -2750,6 +2807,7 @@ static int rtpcs_930x_setup_serdes(struct rtpcs_serdes *sds, case RTPCS_SDS_MODE_2500BASEX: case RTPCS_SDS_MODE_10GBASER: case RTPCS_SDS_MODE_USXGMII_10GQXGMII: + case RTPCS_SDS_MODE_XSGMII: break; default: return 0;